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* ubsan: next_char_of_string signed integer overflowAlan Modra2022-01-011-2/+2
| | | | | | Squash another totally useless fuzz report that I should have ignored. * read.c (next_char_of_string): Avoid integer overflow.
* ubsan: signed integer multiply overflowAlan Modra2022-01-011-1/+6
| | | | | | | 9223371018427387904 * 2 cannot be represented in type 'long', yes, but we don't care. * expr.c (expr): Avoid signed overflow.
* gas reloc sortingAlan Modra2021-12-284-42/+30
| | | | | | | | | | | | | | | | | | | | | In some cases, eg. riscv_pre_output_hook, gas generates out-of-order relocations. Various places in the linker assume relocs are sorted by increasing r_offset, which is normally the case. Provide GAS_SORT_RELOCS to handle unsorted relocs. bfd/ PR 28709 * elf32-nds32.c (nds32_insertion_sort): Make static. * elf32-nds32.h (nds32_insertion_sort): Delete declaration. gas/ PR 28709 * write.c (write_relocs): Implement reloc sorting by r_offset when GAS_SORT_RELOCS. * config/tc-nds32.c (compar_relent, nds32_set_section_relocs): Delete. * config/tc-nds32.h (nds32_set_section_relocs): Don't declare. (SET_SECTION_RELOCS): Don't define. (GAS_SORT_RELOCS): Define. * config/tc-riscv.h (GAS_SORT_RELOCS): Define.
* RISC-V: Rewrite the csr testcases.Nelson Chu2021-12-2442-1521/+3567
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Maskray (Fangrui Song) had suggested me before that we should combine multiple testcases into one file as possible as we can. So that we can more easily understand what these test cases are testing, and easier to maintain. Therefore, this patch rewrites all csr testcases, to make them more clean. gas/ * testsuite/gas/riscv/csr-fail-nonexistent.d: Renamed from priv-reg-fail-nonexistent testcase. * testsuite/gas/riscv/csr-fail-nonexistent.: Likewise. * testsuite/gas/riscv/csr-fail-nonexistent.s: Likewise. * testsuite/gas/riscv/csr-insns-pseudo-noalias.d: Renamed from priv-reg-pseudo testcase. * testsuite/gas/riscv/csr-insns-pseudo.d: Likewise. * testsuite/gas/riscv/csr-insns-pseudo.s: Likewise. * testsuite/gas/riscv/csr-insns-read-only.d: Renamed from priv-reg-fail-read-only-02 testcase. * testsuite/gas/riscv/csr-insns-read-only.l: Likewise. * testsuite/gas/riscv/csr-insns-read-only.s: Likewise. * testsuite/gas/riscv/h-ext-32.d: Moved hypervisor csrs to csr.s. * testsuite/gas/riscv/h-ext-32.s: Likewise. * testsuite/gas/riscv/h-ext-64.d: Likewise. * testsuite/gas/riscv/h-ext-64.s: Likewise. * testsuite/gas/riscv/csr.s: Renamed from priv-reg.s, and then added the hypervisor csrs. * testsuite/gas/riscv/csr-version-1p9p1.d: The csr testcase when the privileged spec is 1.9.1. Also tested all invalid csr warnings when -mcsr-check is enabled. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise, but the privileged spec is 1.10.. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise, but the privileged spec is 1.11. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise, but the privileged spec is 1.12. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/priv-reg*: Removed or Renamed.
* RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta2021-12-245-5/+313
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the Hypervisor Extension 1.0 - Hypervisor Memory-Management Instructions HFENCE.VVMA, HFENCE.GVMA, - Hypervisor Virtual Machine Load and Store Instructions HLV.B, HLV.BU, HSV.B, HLV.H, HLV.HU, HLVX.HU, HSB.H, HLV.W, HLV.WU, HLVX.WU, HSV.W, HLV.D, HSV.D - Hypervisor CSRs (some new, some address changed) hstatus, hedeleg, hideleg, hie, hcounteren, hgeie, htval, hip, hvip, htinst, hgeip, henvcfg, henvcfgh, hgatp, hcontext, htimedelta, htimedeltah, vsstatus, vsie, vstvec, vsscratch, vsepc, vscause, vstval, vsip, vsatp, Note that following were added already as part of svinval extension support: HINVAL.GVMA, HINVAL.VVMA Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Nelson Chu <nelson.chu@sifive.com> bfd/ * cpu-riscv.c (riscv_priv_specs): Added entry for 1.12. * cpu-riscv.h (enum riscv_spec_class): Added PRIV_SPEC_CLASS_1P12. gas/ * config/tc-riscv.c (abort_version): Updated comment. (validate_riscv_insn): Annotate switch-break. * testsuite/gas/riscv/h-ext-32.d: New testcase for hypervisor. * testsuite/gas/riscv/h-ext-32.s: Likewise. * testsuite/gas/riscv/h-ext-64.d: Likewise. * testsuite/gas/riscv/h-ext-64.s: Likewise. include/ * opcode/riscv-opc.h: Added encodings for hypervisor csrs and instrcutions. opcodes/ * riscv-opc.c (riscv_opcodes): Added hypervisor instrcutions.
* RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/testsVineet Gupta2021-12-249-90/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | This makes way for a clean 1.12 based Hypervisor Ext support. There are no known implementors of 1.9.1 H-ext. (Per Jim, kendryte k210 is based on priv spec 1.9.1, but it seems unlikely that they implemented H-ext). Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Nelson Chu <nelson.chu@sifive.com> gas/ * testsuite/gas/riscv/csr-dw-regnums.d: Drop the hypervisor csrs defined in the privileged spec 1.9.1. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise. * testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise. * testsuite/gas/riscv/priv-reg.s: Likewise. include/ * opcode/riscv-opc.h: Drop the hypervisor csrs defined in the privileged spec 1.9.1.
* RISC-V: Update Scalar Crypto testcases.jiawei2021-12-2218-144/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | Add opcodes in testcases to make sure every instruction generate right opcode after disassemble. gas/ChangeLog: * testsuite/gas/riscv/k-ext-64.d: Add opcode detect. * testsuite/gas/riscv/k-ext.d: Ditto. * testsuite/gas/riscv/zbkb-32.d: Ditto. * testsuite/gas/riscv/zbkb-64.d: Ditto. * testsuite/gas/riscv/zbkc-32.d: Ditto. * testsuite/gas/riscv/zbkc-64.d: Ditto. * testsuite/gas/riscv/zbkx-32.d: Ditto. * testsuite/gas/riscv/zbkx-64.d: Ditto. * testsuite/gas/riscv/zknd-32.d: Ditto. * testsuite/gas/riscv/zknd-64.d: Ditto. * testsuite/gas/riscv/zkne-32.d: Ditto. * testsuite/gas/riscv/zkne-64.d: Ditto. * testsuite/gas/riscv/zknh-32.d: Ditto. * testsuite/gas/riscv/zknh-64.d: Ditto. * testsuite/gas/riscv/zksed-32.d: Ditto. * testsuite/gas/riscv/zksed-64.d: Ditto. * testsuite/gas/riscv/zksh-32.d: Ditto. * testsuite/gas/riscv/zksh-64.d: Ditto.
* x86: -mfence-as-lock-add=yes doesn't work for 16-bit modeJan Beulich2021-12-211-1/+6
| | | | | | | Rather than trying to fix this (which would require making an assumption on the upper half of %esp being zero), simply issue an error. While at it, since the generated code is in conflict with -momit-lock-prefix=yes, issue an error in that case as well.
* gas/ELF: avoid below-base ref in obj_elf_parse_section_letters()Jan Beulich2021-12-211-13/+11
| | | | | We would better be prepared for 'm' being the first character of the incoming string.
* x86: Terminate mnemonicendp in swap_operand()Vladimir Mezentsev2021-12-178-420/+420
| | | | | | | | | | | | | | | | | | | | | Tested on x86_64-pc-linux-gnu. opcodes/ChangeLog: 2021-12-17 Vladimir Mezentsev <vladimir.mezentsev@oracle.com> * i386-dis.c (swap_operand): Terminate mnemonicendp. gas/ChangeLog: 2021-12-17 Vladimir Mezentsev <vladimir.mezentsev@oracle.com> * testsuite/gas/i386/opts-intel.d: Updated expected disassembly. * testsuite/gas/i386/opts.d: Likewise. * testsuite/gas/i386/sse2avx-opts-intel.d: Likewise. * testsuite/gas/i386/sse2avx-opts.d: Likewise. * testsuite/gas/i386/x86-64-opts-intel.d: Likewise. * testsuite/gas/i386/x86-64-opts.d: Likewise. * testsuite/gas/i386/x86-64-sse2avx-opts-intel.d: Likewise. * testsuite/gas/i386/x86-64-sse2avx-opts.d: Likewise.
* Fix AVR assembler so that it creates relocs that will work with linker ↵Nick Clifton2021-12-167-6/+45
| | | | | | | | | | | | | | | | relaxation. PR 28686 gas * config/tc-avr.h (tc_fix_adjustable): Define. * config/tc-avr.c (avr_fix_adjustable): New function. * testsuite/gas/all/gas.exp: Skip tests that need adjustable fixups. * testsuite/gas/elf/elf.exp: Likewise. * testsuite/gas/avr/diffreloc_withrelax.d: Adjust expected output. * testsuite/gas/avr/pc-relative-reloc.d: Adjust expected output. ld * testsuite/ld-avr/avr-prop-7.d: Adjust expected output. * testsuite/ld-avr/avr-prop-8.d: Likewise. * testsuite/ld-avr/pr13402.d: Likewise.
* arm: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford2021-12-1611-3/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds AArch32 support for -march=armv9.[123]-a. The behaviour of the new options can be expressed using a combination of existing feature flags and tables. The cpu_arch_ver entries for ARM_ARCH_V9_2A and ARM_ARCH_V9_3A are technically redundant but it seemed less surprising to include them anyway. include/ * opcode/arm.h (ARM_ARCH_V9_1A, ARM_ARCH_V9_2A): New macros. (ARM_ARCH_V9_3A): Likewise. gas/ * doc/c-arm.texi: Add armv9.1-a, armv9.2-a and armv9.3-a. * config/tc-arm.c (armv91a_ext_table, armv92a_ext_table): New macros. (armv93a_ext_table): Likewise. (arm_archs): Add armv9.1-a, armv9.2-a and armv9.3-a. (cpu_arch_ver): Add ARM_ARCH_V9_1A, ARM_ARCH_V9_2A and ARM_ARCH_V9_3A. * NEWS: Mention the above. * testsuite/gas/arm/attr-march-armv9_1-a.d: New test. * testsuite/gas/arm/attr-march-armv9_2-a.d: Likewise. * testsuite/gas/arm/attr-march-armv9_3-a.d: Likewise. * testsuite/gas/arm/bfloat16-armv9.1-a.d: Likewise. * testsuite/gas/arm/bfloat16-armv9.2-a.d: Likewise. * testsuite/gas/arm/bfloat16-armv9.3-a.d: Likewise. * testsuite/gas/arm/i8mm-armv9.1-a.d: Likewise. * testsuite/gas/arm/i8mm-armv9.2-a.d: Likewise. * testsuite/gas/arm/i8mm-armv9.3-a.d: Likewise.
* arm: Add support for Armv8.7-A and Armv8.8-ARichard Sandiford2021-12-169-1/+65
| | | | | | | | | | | | | | | | | | | | | | | | | This patch adds AArch32 support for -march=armv8.[78]-a. The behaviour of the new options can be expressed using a combination of existing feature flags and tables. The cpu_arch_ver entries are technically redundant but it seemed less surprising to include them anyway. include/ * opcode/arm.h (ARM_ARCH_V8_7A, ARM_ARCH_V8_8A): New macros. gas/ * doc/c-arm.texi: Add armv8.7-a and armv8.8-a. * config/tc-arm.c (armv87a_ext_table, armv88a_ext_table): New macros. (arm_archs): Add armv8.7-a and armv8.8-a. (cpu_arch_ver): Add ARM_ARCH_V8_7A and ARM_ARCH_V8_8A. * NEWS: Mention the above. * testsuite/gas/arm/attr-march-armv8_7-a.d: New test. * testsuite/gas/arm/attr-march-armv8_8-a.d: Likewise. * testsuite/gas/arm/bfloat16-armv8.7-a.d: Likewise. * testsuite/gas/arm/bfloat16-armv8.8-a.d: Likewise. * testsuite/gas/arm/i8mm-armv8.7-a.d: Likewise. * testsuite/gas/arm/i8mm-armv8.8-a.d: Likewise.
* aarch64: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford2021-12-1618-2/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds AArch64 support for -march=armv9.[123]-a. The behaviour of the new options can be expressed using a combination of existing feature flags, so we don't need to eat into the vanishing number of spare AARCH64_FEATURE_* bits. Hoewver, it was more convenient to separate out the |s of feature flags so that Armv9.1-A could reuse the set for Armv8.6-A, and so on. include/ * opcode/aarch64.h (AARCH64_ARCH_V8_FEATURES): New macro, split out from... (AARCH64_ARCH_V8): ...here. (AARCH64_ARCH_V8_1_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_1): ...here. (AARCH64_ARCH_V8_2_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_2): ...here. (AARCH64_ARCH_V8_3_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_3): ...here. (AARCH64_ARCH_V8_4_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_4): ...here. (AARCH64_ARCH_V8_5_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_5): ...here. (AARCH64_ARCH_V8_6_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_6): ...here. (AARCH64_ARCH_V8_7_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_7): ...here. (AARCH64_ARCH_V8_8_FEATURES): New macro, split out from... (AARCH64_ARCH_V8_8): ...here. (AARCH64_ARCH_V9_FEATURES): New macro, split out from... (AARCH64_ARCH_V9): ...here. (AARCH64_ARCH_V9_1_FEATURES, AARCH64_ARCH_V9_1): New macros. (AARCH64_ARCH_V9_2_FEATURES, AARCH64_ARCH_V9_2): New macros. (AARCH64_ARCH_V9_3_FEATURES, AARCH64_ARCH_V9_3): New macros. gas/ * doc/c-aarch64.texi: Add armv9.1-a, armv9-2-a and armv9.3-a. * config/tc-aarch64.c (aarch64_archs): Likewise. * NEWS: Mention the above. * testsuite/gas/aarch64/armv9_invalid.d, testsuite/gas/aarch64/armv9_invalid.s, testsuite/gas/aarch64/armv9_invalid.l: New test. * testsuite/gas/aarch64/armv9_1.d, testsuite/gas/aarch64/armv9_1.s: Likewise. * testsuite/gas/aarch64/armv9_1_invalid.d, testsuite/gas/aarch64/armv9_1_invalid.s, testsuite/gas/aarch64/armv9_1_invalid.l: Likewise. * testsuite/gas/aarch64/armv9_2.d, testsuite/gas/aarch64/armv9_2.s: Likewise. * testsuite/gas/aarch64/armv9_2_invalid.d, testsuite/gas/aarch64/armv9_2_invalid.s, testsuite/gas/aarch64/armv9_2_invalid.l: Likewise. * testsuite/gas/aarch64/armv9_3.d, testsuite/gas/aarch64/armv9_3.s: Likewise.
* RISC-V: Support svinval extension with frozen version 1.0.Nelson Chu2021-12-162-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the privileged spec, there are five new instructions for svinval extension. Two of them (HINVAL.VVMA and HINVAL.GVMA) need to enable the hypervisor extension. But there is no implementation of hypervisor extension in mainline for now, so let's consider the related issues later. 31..25 24..20 19..15 14..12 11...7 6..2 1..0 sinval.vma 0001011 rs2 rs1 000 00000 11100 11 sfence.w.inval 0001100 00000 00000 000 00000 11100 11 sfence.inval.ir 0001100 00001 00000 000 00000 11100 11 hinval.vvma 0010011 rs2 rs1 000 00000 11100 11 hinval.gvma 0110011 rs2 rs1 000 00000 11100 11 This patch is cherry-picked from the riscv integration branch since the svinval extension is frozen for now. Besides, we fix the funct7 encodings of hinval.vvma and hinval.gvma, from 0x0011011 and 0x0111011 to 0x0010011 and 0x0110011. bfd/ * elfxx-riscv.c (riscv_supported_std_s_ext): Added svinval. (riscv_multi_subset_supports): Handle INSN_CLASS_SVINVAL. gas/ * testsuite/gas/riscv/svinval.d: New testcase. * testsuite/gas/riscv/svinval.s: Likewise. include/ * opcode/riscv-opc.h: Added encodings for svinval. * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_SVINVAL. opcodes/ * riscv-opc.c (riscv_opcodes): Added svinval instructions.
* loongarch64 build failure on 32-bit hostAlan Modra2021-12-151-6/+6
| | | | | | | | | | | | | | gas/config/tc-loongarch.c: In function ‘loongarch_args_parser_can_match_arg_helper’: gas/config/tc-loongarch.c:661:13: error: cast from pointer to integer of different size [-Werror=pointer -to-int-cast] 661 | imm = (offsetT) str_hash_find (r_htab, arg); | ^ Cast it to the correct size int, relying on normal integer promotions if offsetT is larger than a pointer. * config/tc-loongarch.c (loongarch_args_parser_can_match_arg_helper): Cast return from str_hash_find to intptr_t, not offsetT.
* RISC-V: Clarify the behavior of .option arch directive.Nelson Chu2021-12-098-9/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * To be consistent with -march option, removed the "=" operator when user want to reset the whole architecture string. So the formats are, .option arch, +<extension><version>, ... .option arch, -<extension> .option arch, <ISA string> * Don't allow to add or remove the base extensions in the .option arch directive. Instead, users should reset the whole architecture string while they want to change the base extension. * The operator "+" won't update the version of extension, if the extension is already in the subset list. bfd/ * elfxx-riscv.c (riscv_add_subset): Don't update the version if the extension is already in the subset list. (riscv_update_subset): To be consistent with -march option, removed the "=" operator when user want to reset the whole architecture string. Besides, Don't allow to add or remove the base extensions in the .option arch directive. gas/ * testsuite/gas/riscv/option-arch-01.s: Updated since we cannot add or remove the base extensions in the .option arch directive. * testsuite/gas/riscv/option-arch-02.s: Likewise. * testsuite/gas/riscv/option-arch-fail.l: Likewise. * testsuite/gas/riscv/option-arch-fail.s: Likewise. * testsuite/gas/riscv/option-arch-01a.d: Set -misa-spec=2.2. * testsuite/gas/riscv/option-arch-01b.d: Likewise. * testsuite/gas/riscv/option-arch-02.d: Updated since the .option arch, + won't change the version of extension, if the extension is already in the subset list. * testsuite/gas/riscv/option-arch-03.s: Removed the "=" operator when resetting the whole architecture string.
* aarch64: Update gas/NEWS for recent changesRichard Sandiford2021-12-021-1/+4
| | | | | gas/ * NEWS: Mention support for Armv8.8-A and for new system registers.
* aarch64: Add BC instructionRichard Sandiford2021-12-027-0/+90
| | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the Armv8.8-A BC instruction. [https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions/BC-cond--Branch-Consistent-conditionally-?lang=en] include/ * opcode/aarch64.h (AARCH64_FEATURE_HBC): New macro. (AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_HBC. opcodes/ * aarch64-tbl.h (aarch64_feature_hbc): New variable. (HBC, HBC_INSN): New macros. (aarch64_opcode_table): Add BC.C. * aarch64-dis-2.c: Regenerate. gas/ * doc/c-aarch64.texi: Document +hbc. * config/tc-aarch64.c (aarch64_features): Add "hbc". * testsuite/gas/aarch64/hbc.s, testsuite/gas/aarch64/hbc.d: New test. * testsuite/gas/aarch64/hbc-invalid.s, testsuite/gas/aarch64/hbc-invalid.l, testsuite/gas/aarch64/hbc-invalid.d: New test.
* aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford2021-12-024-10/+202
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MOPS instructions should be used as a triple, such as: cpyfp [x0]!, [x1]!, x2! cpyfm [x0]!, [x1]!, x2! cpyfe [x0]!, [x1]!, x2! The registers should also be the same for each writeback operand. This patch adds a warning for code that doesn't follow this rule, along similar lines to the warning that we already emit for invalid uses of MOVPRFX. include/ * opcode/aarch64.h (C_SCAN_MOPS_P, C_SCAN_MOPS_M, C_SCAN_MOPS_E) (C_SCAN_MOPS_PME): New macros. (AARCH64_OPDE_A_SHOULD_FOLLOW_B): New aarch64_operand_error_kind. (AARCH64_OPDE_EXPECTED_A_AFTER_B): Likewise. (aarch64_operand_error): Make each data value a union between an int and a string. opcodes/ * aarch64-tbl.h (MOPS_CPY_OP1_OP2_INSN): Add scan flags. (MOPS_SET_OP1_OP2_INSN): Likewise. * aarch64-opc.c (set_out_of_range_error): Update after change to aarch64_operand_error. (set_unaligned_error, set_reg_list_error): Likewise. (init_insn_sequence): Use a 3-instruction sequence for MOPS P instructions. (verify_mops_pme_sequence): New function. (verify_constraints): Call it. * aarch64-dis.c (print_verifier_notes): Handle AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B. gas/ * config/tc-aarch64.c (operand_mismatch_kind_names): Add entries for AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B. (operand_error_higher_severity_p): Check that AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B come between AARCH64_OPDE_RECOVERABLE and AARCH64_OPDE_SYNTAX_ERROR; their relative order is not significant. (record_operand_error_with_data): Update after change to aarch64_operand_error. (output_operand_error_record): Likewise. Handle AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B. * testsuite/gas/aarch64/mops_invalid_2.s, testsuite/gas/aarch64/mops_invalid_2.d, testsuite/gas/aarch64/mops_invalid_2.l: New test.
* aarch64: Add support for +mopsRichard Sandiford2021-12-027-0/+1592
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for FEAT_MOPS, an Armv8.8-A extension that provides memcpy and memset acceleration instructions. I took the perhaps controversial decision to generate the individual instruction forms using macros rather than list them out individually. This becomes useful with a follow-on patch to check that code follows the correct P/M/E sequence. [https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions?lang=en] include/ * opcode/aarch64.h (AARCH64_FEATURE_MOPS): New macro. (AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_MOPS. (AARCH64_OPND_MOPS_ADDR_Rd): New aarch64_opnd. (AARCH64_OPND_MOPS_ADDR_Rs): Likewise. (AARCH64_OPND_MOPS_WB_Rn): Likewise. opcodes/ * aarch64-asm.h (ins_x0_to_x30): New inserter. * aarch64-asm.c (aarch64_ins_x0_to_x30): New function. * aarch64-dis.h (ext_x0_to_x30): New extractor. * aarch64-dis.c (aarch64_ext_x0_to_x30): New function. * aarch64-tbl.h (aarch64_feature_mops): New feature set. (aarch64_feature_mops_memtag): Likewise. (MOPS, MOPS_MEMTAG, MOPS_INSN, MOPS_MEMTAG_INSN) (MOPS_CPY_OP1_OP2_PME_INSN, MOPS_CPY_OP1_OP2_INSN, MOPS_CPY_OP1_INSN) (MOPS_CPY_INSN, MOPS_SET_OP1_OP2_PME_INSN, MOPS_SET_OP1_OP2_INSN) (MOPS_SET_INSN): New macros. (aarch64_opcode_table): Add MOPS instructions. (aarch64_opcode_table): Add entries for AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. (verify_three_different_regs): New function. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. gas/ * doc/c-aarch64.texi: Document +mops. * config/tc-aarch64.c (parse_x0_to_x30): New function. (parse_operands): Handle AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. (aarch64_features): Add "mops". * testsuite/gas/aarch64/mops.s, testsuite/gas/aarch64/mops.d: New test. * testsuite/gas/aarch64/mops_invalid.s, * testsuite/gas/aarch64/mops_invalid.d, * testsuite/gas/aarch64/mops_invalid.l: Likewise.
* aarch64: Add Armv8.8-A system registersRichard Sandiford2021-12-025-0/+46
| | | | | | | | | | | | | | | | | | | Armv8.8-A defines two new system registers: allint and icc_nmiar1_el1. Both of them were previously unmapped. allint supports a 0/1 immediate. [https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/ALLINT--All-Interrupt-Mask-Bit?lang=en] [https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/ICC-NMIAR1-EL1--Interrupt-Controller-Non-maskable-Interrupt-Acknowledge-Register-1?lang=en] opcodes/ * aarch64-opc.c (SR_V8_8): New macro. (aarch64_sys_regs): Add allint and icc_nmiar1_el1. (aarch64_pstatefields): Add allint. gas/ * testsuite/gas/aarch64/armv8_8-a-sysregs.s, * testsuite/gas/aarch64/armv8_8-a-sysregs.d: New test. * testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.s, * testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.l, * testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.d: New test.
* aarch64: Add id_aa64isar2_el1Richard Sandiford2021-12-025-0/+8
| | | | | | | | | | | | | | | | | | | Armv8.8-A defines a read-only system register called id_aa64isar2_el1. The register was previously RES0 and should therefore be accepted at all architecture levels. [https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/ID-AA64ISAR2-EL1--AArch64-Instruction-Set-Attribute-Register-2?lang=en] opcodes/ * aarch64-opc.c (aarch64_sys_regs): Add id_aa64isar2_el1. gas/ * testsuite/gas/aarch64/sysreg-diagnostic.s: Test writes to id_aa64isar2_el1. * testsuite/gas/aarch64/sysreg-diagnostic.d: Update accordingly. * testsuite/gas/aarch64/sysreg-diagnostic.l: Likewise. * testsuite/gas/aarch64/sysreg.s: Test reads from id_aa64isar2_el1. * testsuite/gas/aarch64/sysreg.d: Update accordingly.
* aarch64: Add support for Armv8.8-ARichard Sandiford2021-12-024-2/+10
| | | | | | | | | | | | | | | This patch adds skeleton support for -march=armv8.8-a, testing only that it correctly inherits from armv8.7-a. include/ * opcode/aarch64.h (AARCH64_FEATURE_V8_8): New macro. (AARCH64_ARCH_V8_8): Likewise. gas/ * doc/c-aarch64.texi: Document armv8.8-a. * config/tc-aarch64.c (aarch64_archs): Add armv8-8-a * testsuite/gas/aarch64/v8-8-a.s, * testsuite/gas/aarch64/v8-8-a.d: New test.
* aarch64: Provide line info for unclosed sequencesRichard Sandiford2021-12-025-15/+17
| | | | | | | | | | | | | | | | | | | | | | We warn about MOVPRFX instructions that have no following instruction. This patch adds a line number to the message, which is useful if the assembly code has multiple text sections. The new code is unconditional since OBJ_ELF is always defined for aarch64. gas/ * config/tc-aarch64.h (aarch64_segment_info_type): Add last_file and last_line. * config/tc-aarch64.c (now_instr_sequence): Delete. (force_automatic_sequence_close): Provide a line number when reporting unclosed sequences. (md_assemble): Record the location of the instruction in tc_segment_info. * testsuite/gas/aarch64/sve-movprfx_4.l: Add line number to error message. * testsuite/gas/aarch64/sve-movprfx_7.l: Likewise. * testsuite/gas/aarch64/sve-movprfx_8.l: Likewise.
* aarch64: Add maximum immediate value to aarch64_sys_regRichard Sandiford2021-12-029-39/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The immediate form of MSR has a 4-bit immediate field (in CRm). However, many forms of MSR require a smaller immediate. These cases are identified by value in operand_general_constraint_met_p, but they're now the common case rather than the exception. This patch therefore adds the maximum value to the sys_reg description and gets the range from there. It also enforces the minimum of 0, which avoids a situation in which: msr dit, #2 would give the expected: Error: immediate value out of range 0 to 1 whereas: msr dit, #-1 would give: Error: immediate value out of range 0 to 15 (from the later UIMM4 checking). Also: - we were reporting the first error above against the wrong operand - TCO takes a single-bit immediate, but we previously allowed all 16 values. [https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions/MSR--immediate---Move-immediate-value-to-Special-Register-?lang=en] opcodes/ * aarch64-opc.h (F_REG_MAX_VALUE, F_GET_REG_MAX_VALUE): New macros. * aarch64-opc.c (operand_general_constraint_met_p): Read the maximum MSR immediate value from aarch64_pstatefields. (aarch64_pstatefields): Add the maximum immediate value for each register. gas/ * testsuite/gas/aarch64/sysreg-4.s: Use an immediate value of 1 rather than 8 for the TCO test. * testsuite/gas/aarch64/sysreg-4.d: Update accordingly. * testsuite/gas/aarch64/armv8_2-a-illegal.l: Fix operand number in MSR immediate error messages. * testsuite/gas/aarch64/diagnostic.l: Likewise. * testsuite/gas/aarch64/pan-illegal.l: Likewise. * testsuite/gas/aarch64/ssbs-illegal1.l: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4b.s, * testsuite/gas/aarch64/illegal-sysreg-4b.d, * testsuite/gas/aarch64/illegal-sysreg-4b.l: New test.
* gas: re-generate configureSimon Marchi2021-12-021-2/+1
| | | | | | | | | | When configuring gas, I get: config.status: error: cannot find input file: `doc/Makefile.in' This is because configure is out-of-date, re-generate it. Change-Id: Iaa5980c282900d9fd23b90f0df25bf8ba3676498
* gas: merge doc subdir up a levelMike Frysinger2021-12-016-1163/+671
| | | | | This avoids a recursive make into the doc subdir and speeds up the build slightly. It also allows for more parallelism.
* aarch64: Add missing system registers [PR27145]Richard Sandiford2021-11-3010-6/+877
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for various system registers, up to Armv8.7-A. This includes all the registers that were mentioned in the PR and that hadn't become supported since. opcodes/ PR aarch64/27145 * aarch64-opc.c (SR_V8_4): Remove duplicate definition. (SR_V8_6, SR_V8_7, SR_GIC, SR_AMU): New macros. (aarch64_sys_regs): Add missing entries (up to Armv8.7-A). gas/ PR aarch64/27145 * testsuite/gas/aarch64/sysreg-8.s, * testsuite/gas/aarch64/sysreg-8.d, * testsuite/gas/aarch64/illegal-sysreg-8.s, * testsuite/gas/aarch64/illegal-sysreg-8.d, * testsuite/gas/aarch64/illegal-sysreg-8.l, * testsuite/gas/aarch64/illegal-sysreg-8b.s, * testsuite/gas/aarch64/illegal-sysreg-8b.d, * testsuite/gas/aarch64/illegal-sysreg-8b.l: New tests. * testsuite/gas/aarch64/sysreg.s: Change system register numbers to ones that are still unallocated. * testsuite/gas/aarch64/sysreg.d: Update accordingly.
* aarch64: Make LOR registers conditional on +lorRichard Sandiford2021-11-304-1/+13
| | | | | | | | | | | | | | | | | We have a +lor feature flag for the Limited Ordering Regions extension, but the associated registers didn't use it. opcodes/ * aarch64-opc.c (SR_LOR): New macro. (aarch64_sys_regs): Use it for lorc_el1, lorea_el1, lorn_el1 and lorsa_el1. gas/ * testsuite/gas/aarch64/sysreg-7.s: Enable +lor. * testsuite/gas/aarch64/illegal-sysreg-7.s: Test for LOR registers without +lor. * testsuite/gas/aarch64/illegal-sysreg-7.d: Update accordingly. * testsuite/gas/aarch64/illegal-sysreg-7.l: Likewise.
* aarch64: Remove ZIDR_EL1Richard Sandiford2021-11-303-7/+0
| | | | | | | | | | | | | ZIDR_EL1 was part of an early version of SVE, but didn't make it to the final release. opcodes/ * aarch64-opc.c (aarch64_sys_regs): Remove zidr_el1 entry. gas/ * testsuite/gas/aarch64/sve-sysreg.s: Remove zidr_el1. * testsuite/gas/aarch64/sve-sysreg.d: Update accordingly. * testsuite/gas/aarch64/sve-sysreg-invalid.l: Likewise.
* aarch64: Allow writes to MFAR_EL3Richard Sandiford2021-11-305-20/+13
| | | | | | | | | | | | | | | | MFAR_EL3 is a read/write register, but was incorrectly marked as read-only [https://developer.arm.com/documentation/ddi0601/2021-09/AArch64-Registers/MFAR-EL3--PA-Fault-Address-Register?lang=en] opcodes/ * aarch64-opc.c (aarch64_sys_regs): Mark mfar_el3 as read-write. gas/ * testsuite/gas/aarch64/rme.s: Test writing to mfar_el3. * testsuite/gas/aarch64/rme.d: Update accordingly. * testsuite/gas/aarch64/rme-invalid.s: Delete. * testsuite/gas/aarch64/rme-invalid.l: Likewise. * testsuite/gas/aarch64/rme-invalid.d: Likewise.
* aarch64: Mark PMSIDR_EL1 as read-onlyRichard Sandiford2021-11-305-3/+8
| | | | | | | | | | | | | | | | We were incorrectly allowing writes to PMSIDR_EL1, which is a read-only register. [https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/PMSIDR-EL1--Sampling-Profiling-ID-Register?lang=en] opcodes/ * aarch64-opc.c (aarch64_sys_regs): Make pmsidr_el1 as F_REG_READ. gas/ * testsuite/gas/aarch64/msr.s: Remove write to pmsidr_el1. * testsuite/gas/aarch64/msr.d: Update accordingly. * testsuite/gas/aarch64/illegal-sysreg-2.s, * testsuite/gas/aarch64/illegal-sysreg-2.d, * testsuite/gas/aarch64/illegal-sysreg-2.l: New test.
* aarch64: Remove duplicate system register entriesRichard Sandiford2021-11-302-4/+0
| | | | | | | | | | | | | | | There is a lot of overlap between the ETM and ETE system registers, so some registers were listed twice. Already tested by etm.[sd] and ete.[sd]. opcodes/ * aarch64-opc.c (aarch64_sys_regs): Combine ETE and ETM blocks and remove redundant entries. gas/ * testsuite/gas/aarch64/etm.s: Remove duplicated test. * testsuite/gas/aarch64/etm.d: Update accordingly.
* aarch64: Check for register aliases before mnemonicsRichard Sandiford2021-11-306-34/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we would not accept: A .req B if A happened to be the name of an instruction. Adding new instructions could therefore invalidate existing register aliases. I noticed this with a test that used "zero" as a register alias for "xzr", where "zero" is now also the name of an SME instruction. I don't have any evidence that "real" code is doing this, but it seems at least plausible. This patch switches things so that we check for register aliases first. It might slow down parsing slightly, but the difference is unlikely to be noticeable. Things like: b .req + 0 still work, since create_register_alias checks for " .req ", and with the input scrubber, we'll only keep whitespace after .req if it's followed by another name. If there's some valid expression that I haven't thought about that is scrubbed to " .req ", users could avoid the ambiguity by wrapping .req in parentheses. The new test for invalid aliases already passed. I just wanted something to exercise the !dot condition. I can't find a way of exercising the (existing) p == base condition, but I'm not brave enough to say that it can never happen. If it does happen, get_mnemonic_name would return an empty string. gas/ * config/tc-aarch64.c (opcode_lookup): Move mnemonic extraction code to... (md_assemble): ...here. Check for register aliases first. * testsuite/gas/aarch64/register_aliases.d, testsuite/gas/aarch64/register_aliases.s: Test for a register alias called "zero". * testsuite/gas/aarch64/register_aliases_invalid.d, testsuite/gas/aarch64/register_aliases_invalid.l, testsuite/gas/aarch64/register_aliases_invalid.s: New test.
* RISC-V: The vtype immediate with more than the defined 8 bits are preserved.Nelson Chu2021-11-302-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According the rvv spec, https://github.com/riscv/riscv-v-spec/blob/master/vtype-format.adoc The bits of vtype immediate from 8 to (xlen - 1) should be reserved. Therefore, we should also dump the vtype immediate as numbers, when they are set over 8-bits. I think this is a bug that we used to support vediv extension and use the bit 8 and 9 of vtype, but forgot to update the behavior when removing the vediv. Consider the testcases, vsetvli a0, a1, 0x700 # the reserved bit 10, 9 and 8 are used. vsetvli a0, a1, 0x400 # the reserved bit 10 is used. vsetvli a0, a1, 0x300 # the reserved bit 9 and 8 are used. vsetvli a0, a1, 0x100 # the reserved bit 8 is used. vsetivli a0, 0xb, 0x300 # the reserved bit 9 and 8 are used. vsetivli a0, 0xb, 0x100 # the reserved bit 8 is used. The original objdump shows the following result, 0000000000000000 <.text>: 0: 7005f557 vsetvli a0,a1,1792 4: 4005f557 vsetvli a0,a1,1024 8: 3005f557 vsetvli a0,a1,e8,m1,tu,mu c: 1005f557 vsetvli a0,a1,e8,m1,tu,mu 10: f005f557 vsetivli a0,11,e8,m1,tu,mu 14: d005f557 vsetivli a0,11,e8,m1,tu,mu But in fact the correct result should be, 0000000000000000 <.text>: 0: 7005f557 vsetvli a0,a1,1792 4: 4005f557 vsetvli a0,a1,1024 8: 3005f557 vsetvli a0,a1,768 c: 1005f557 vsetvli a0,a1,256 10: f005f557 vsetivli a0,11,768 14: d005f557 vsetivli a0,11,256 gas/ * testsuite/gas/riscv/vector-insns.d: Added testcases to test the reserved bit 8 to (xlen-1) of vtype. * testsuite/gas/riscv/vector-insns.s: Likewise. include/ * opcode/riscv.h: Removed OP_MASK_VTYPE_RES and OP_SH_VTYPE_RES, since they are different for operand Vc and Vb. opcodes/ * riscv-dis.c (print_insn_args): Updated imm_vtype_res to extract the reserved immediate of vtype correctly.
* RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved.Nelson Chu2021-11-302-68/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consider the following case, vsetvli a0, a1, 0x4 # unrecognized vlmul vsetvli a0, a1, 0x20 # unrecognized vsew vsetivli a0, 0xb, 0x4 # unrecognized vlmul vsetivli a0, 0xb, 0x20 # unrecognized vsew For the current dis-assembler, we get the result, 0000000000000000 <.text>: 0: 0045f557 vsetvli a0,a1,e8,(null),tu,mu 4: 0205f557 vsetvli a0,a1,e128,m1,tu,mu 8: c045f557 vsetivli a0,11,e8,(null),tu,mu c: c205f557 vsetivli a0,11,e128,m1,tu,mu The vsew e128 and vlmul (null) are preserved according to the spec, so dump these fields looks wrong. Consider that we are used to dump the unrecognized csr as csr numbers directly, we should also dump the whole vset[i]vli immediates as numbers, once the vsew or vlmul is reserved. Therefore, following is what I expected, 0000000000000000 <.text>: 0: 0045f557 vsetvli a0,a1,4 4: 0205f557 vsetvli a0,a1,32 8: c045f557 vsetivli a0,11,4 c: c205f557 vsetivli a0,11,32 gas/ * testsuite/gas/riscv/vector-insns.d: Rewrite the vset[i]vli testcases since we should dump the immediate as numbers once the vsew or vlmul is reserved. * testsuite/gas/riscv/vector-insns.s: Likewise. opcodes/ * riscv-dis.c (print_insn_args): The reserved vsew and vlmul are NULL string in the riscv_vsew and riscv_vlmul, so dump the whole imm as numbers once one of them is NULL. * riscv-opc.c (riscv_vsew): Set the reserved vsew to NULL. (riscv_vlmul): Set the reserved vlmul to NULL.
* PR28629 NIOS2 falloutAlan Modra2021-11-291-1/+1
| | | | | | | The test exactly matched wrong output. PR 28629 * testsuite/gas/nios2/relax.d: Update expected output.
* gas: Update commit 4780e5e4933H.J. Lu2021-11-262-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update commit 4780e5e4933a2497a5aecc4ceabbbb8e82aaf822 Author: Tom de Vries <tdevries@suse.de> Date: Fri Nov 26 09:59:45 2021 +0100 [gas] Fix file 0 dir with -gdwarf-5 1. Replace i with j in for (j = 0; i < NUM_MD5_BYTES; ++j) 2. Pass -W to readelf to force CU: in output due to: if (do_wide || strlen (directory) < 76) printf (_("CU: %s/%s:\n"), directory, file_table[0].name); else printf ("%s:\n", file_table[0].name); PR gas/28629 * dwarf2dbg.c (out_dir_and_file_list): Fix a typo in commit 4780e5e4933. * testsuite/gas/elf/dwarf-5-nop-for-line-table.d: Pass -W to readelf.
* [gas] Fix file 0 dir with -gdwarf-5Tom de Vries2021-11-263-3/+16
| | | | | | | | | | | | | | | | In out_dir_and_file_list, if file 0 is copied from file 1, only the filename is copied, and the dir and md5 fields are left to their default values. Fix this by adding the copy of the dir and md5 fields. gas/ChangeLog: 2021-11-26 Tom de Vries <tdevries@suse.de> PR 28629 * dwarf2dbg.c (out_dir_and_file_list): When copying file 1 to file 0, also copy dir and md5 fields. * testsuite/gas/i386/dwarf5-line-4.d: Adjust expected output.
* gas: enable silent build rulesMike Frysinger2021-11-252-2/+42
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* Update bug reporting addressAlan Modra2021-11-232-6/+2
| | | | | | | | | | | | | | | | | | | | | | | https://sourceware.org/bugzilla/ everywhere bfd/ * configure.ac (ACX_BUGURL): Set to https://sourceware.org/bugzilla/ * po/Make-in (msgid-bugs-address): Likewise. * README: Report bugs to the above. * configure: Regenerate. binutils/ * po/Make-in (msgid-bugs-address): Update. gas/ * README: Update bug address. Delete mention of gcc. * po/Make-in: Update bug address. gold/ * po/Make-in: Update bug address. gprof/ * po/Make-in: Update bug address. ld/ * po/Make-in: Update bug address. opcodes/ * po/Make-in: Update bug address.
* RISC-V: Replace .option rvc/norvc with .option arch, +c/-c.Nelson Chu2021-11-2216-18/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | Since the .option rvc/norvc directives are obsolete, replace them with the new proposed diretives: .option arch, +c/-c. And also reset the riscv_opts.rvc flag for the .option arch directives. gas/ * config/tc-riscv.c (s_riscv_option): Reset the riscv_opts.rvc for the .option arch directives. * testsuite/gas/riscv/align-1.s: Replace the obsolete .option rvc/norvc with .option arch, +c/-c. * testsuite/gas/riscv/c-add-addi.s: Likewise. * testsuite/gas/riscv/c-nonzero-imm.s: Likewise. * testsuite/gas/riscv/c-nonzero-reg.s: Likewise. * testsuite/gas/riscv/c-zero-imm-64.s: Likewise. * testsuite/gas/riscv/c-zero-imm.s: Likewise. * testsuite/gas/riscv/c-zero-reg.s: Likewise. * testsuite/gas/riscv/ext.s: Likewise. * testsuite/gas/riscv/mapping-01.s: Likewise. * testsuite/gas/riscv/mapping-02.s: Likewise. * testsuite/gas/riscv/mapping-03.s: Likewise. * testsuite/gas/riscv/mapping-04.s: Likewise. * testsuite/gas/riscv/no-relax-align-2.s: Likewise. * testsuite/gas/riscv/shamt-32.s: Likewise. * testsuite/gas/riscv/shamt-64.s: Likewise.
* RISC-V: Support new .option arch directive.Nelson Chu2021-11-1912-18/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/riscv/riscv-asm-manual/pull/67 Format: .option arch, +<extension><version>, ... .option arch, -<extension> .option arch, =<ISA string> The new direcitve is used to enable/disable extensions for the specific code region. For example, .attribute arch, "rv64ic" # arch = rv64i2p0_c2p0 .option push .option arch, +d2p0, -c # arch = rv64i2p0_f2p0_d2p0, f is added implied .option arch, =rv32gc # arch = rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0 .option pop # arch = rv64i2p0_c2p0 Note that, 1. ".option rvc/norvc" have the same behavior as ".option arch +c/-c". 2. ".option arch -i" is illegal, since we cannot remove base i extension. 3. If arch=rv64i2p0, then ".option arch, +i3p0" will update the i's version from 2.0 to 3.0. 4. If arch=rv64i3p0, then ".option arch, +i" will update the i's version from 2.0 to the default one according to the chosen isa spec. bfd/ * elfxx-riscv.c (riscv_add_subset): If the subset is already added, and the new versions are not RISCV_UNKNOWN_VERSION, then update the versions to the subset list. (riscv_copy_subset): New function. Copy the subset from list. (riscv_copy_subset_list): New function. Return the new copyed list. (riscv_update_subset): Updated to make .option arch directives workable. * elfxx-riscv.h: Updated. gas/ * config/tc-riscv.c (riscv_subsets): Defined as a pointer. (riscv_rps_as): Init the subset_list to NULL, we will set it later once riscv_opts_stack is created or updated. (struct riscv_option_stack, riscv_opts_stack): Moved forward. (riscv_set_arch): Updated. (s_riscv_option): Support new .option arch directive, to add, remove or update subsets for the specific code region. (riscv_write_out_attrs): Updated. * doc/c-riscv.texi: Added document for new .option arch directive. * testsuite/gas/riscv/option-arch-01a.d: New testcase. * testsuite/gas/riscv/option-arch-01b.d: Likewise. * testsuite/gas/riscv/option-arch-01.s: Likewise.. * testsuite/gas/riscv/option-arch-02.d: Likewise. * testsuite/gas/riscv/option-arch-02.s: Likewise. * testsuite/gas/riscv/option-arch-fail.d: Likewise. * testsuite/gas/riscv/option-arch-fail.l: Likewise. * testsuite/gas/riscv/option-arch-fail.s: Likewise.
* Re: Add multibyte character warning option to the assembler.Alan Modra2021-11-191-10/+10
| | | | | | | | On hppa*-hp-hpux* run_dump_test edits the test file, adjusting .comm directives to suit those target's unusual syntax. Thus gas is passed a temporary file name. * testsuite/gas/all/multibyte1.l: Ignore file name.
* RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC.Nelson Chu2021-11-196-0/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the original discussion, https://github.com/riscv/riscv-elf-psabi-doc/pull/190 And here is the glibc part, https://sourceware.org/pipermail/libc-alpha/2021-August/129931.html For binutils part, we need to support a new direcitve: .variant_cc. The function symbol marked by .variant_cc means it need to be resolved directly without resolver for dynamic linker. We also add a new dynamic entry, STO_RISCV_VARIANT_CC, to indicate there are symbols with the special attribute in the dynamic symbol table of the object. I heard that llvm already have supported this in their mainline, so I think it's time to commit this. bfd/ * elfnn-riscv.c (riscv_elf_link_hash_table): Added variant_cc flag. It is used to check if relocations for variant CC symbols may be present. (allocate_dynrelocs): If the symbol has STO_RISCV_VARIANT_CC flag, then raise the variant_cc flag of riscv_elf_link_hash_table. (riscv_elf_size_dynamic_sections): Added dynamic entry for variant_cc. (riscv_elf_merge_symbol_attribute): New function, used to merge non-visibility st_other attributes, including STO_RISCV_VARIANT_CC. binutils/ * readelf.c (get_riscv_dynamic_type): New function. (get_dynamic_type): Called get_riscv_dynamic_type for riscv targets. (get_riscv_symbol_other): New function. (get_symbol_other): Called get_riscv_symbol_other for riscv targets. gas/ * config/tc-riscv.c (s_variant_cc): Marked symbol that it follows a variant CC convention. (riscv_elf_copy_symbol_attributes): Same as elf_copy_symbol_attributes, but without copying st_other. If a function symbol has special st_other value set via directives, then attaching an IFUNC resolver to that symbol should not override the st_other setting. (riscv_pseudo_table): Support variant_cc diretive. * config/tc-riscv.h (OBJ_COPY_SYMBOL_ATTRIBUTES): Defined. * testsuite/gas/riscv/variant_cc-set.d: New testcase. * testsuite/gas/riscv/variant_cc-set.s: Likewise. * testsuite/gas/riscv/variant_cc.d: Likewise. * testsuite/gas/riscv/variant_cc.s: Likewise. include/ * elf/riscv.h (DT_RISCV_VARIANT_CC): Defined to (DT_LOPROC + 1). (STO_RISCV_VARIANT_CC): Defined to 0x80. ld/ * testsuite/ld-riscv-elf/variant_cc-1.s: New testcase. * testsuite/ld-riscv-elf/variant_cc-2.s: Likewise. * testsuite/ld-riscv-elf/variant_cc-now.d: Likewise. * testsuite/ld-riscv-elf/variant_cc-r.d: Likewise. * testsuite/ld-riscv-elf/variant_cc-shared.d: Likewise. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* Add multibyte character warning option to the assembler.Nick Clifton2021-11-1814-10/+205
| | | | | | | | | | | | | | | | | | | | | | * as.c (parse_args): Add support for --multibyte-handling. * as.h (multibyte_handling): Declare. * app.c (scan_for_multibyte_characters): New function. (do_scrub_chars): Call the new function if multibyte warning is enabled. * input-scrub,c (input_scrub_next_buffer): Call the multibyte scanning function if multibyte warnings are enabled. * symbols.c (struct symbol_flags): Add multibyte_warned bit. (symbol_init): Call the multibyte scanning function if multibyte symbol warnings are enabled. (S_SET_SEGMENT): Likewise. * NEWS: Mention the new feature. * doc/as.texi: Document the new feature. * testsuite/gas/all/multibyte.s: New test source file. * testsuite/gas/all/multibyte1.d: New test driver file. * testsuite/gas/all/multibyte1.l: New test expected output. * testsuite/gas/all/multibyte2.d: New test driver file. * testsuite/gas/all/multibyte2.l: New test expected output. * testsuite/gas/all/gas.exp: Run the new tests.
* RISC-V: Add testcases for z[fdq]inxjiawei2021-11-186-0/+222
| | | | | | | | | | | | | | | | Use gpr when the zfinx enable, the testcases contain float instructions that reuse by z[fdq]inx. gas/ChangeLog: * testsuite/gas/riscv/zdinx.d: New test. * testsuite/gas/riscv/zdinx.s: New test. * testsuite/gas/riscv/zfinx.d: New test. * testsuite/gas/riscv/zfinx.s: New test. * testsuite/gas/riscv/zqinx.d: New test. * testsuite/gas/riscv/zqinx.s: New test. Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
* RISC-V: Add instructions and operand set for z[fdq]inxjiawei2021-11-181-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Reuse float instructions in INSN_CLASS_F/D/Q, use riscv_subset_supports to verify if z*inx enabled and use gpr instead of fpr when z*inx is enable. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Added support for z*inx extension. gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Added register choice for z*inx. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Reused INSN_CLASS_* for z*inx. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Added disassemble check for z*inx. * riscv-opc.c: Reused INSN_CLASS_* for z*inx. Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
* aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus2021-11-176-0/+348
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is adding new SVE2 instructions added to support SME extension. The following SVE2 instructions are added by the SME architecture: * PSEL, * REVD, SCLAMP and UCLAMP. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_pred_reg_with_index): New parser. (parse_operands): New parser. * testsuite/gas/aarch64/sme-9-illegal.d: New test. * testsuite/gas/aarch64/sme-9-illegal.l: New test. * testsuite/gas/aarch64/sme-9-illegal.s: New test. * testsuite/gas/aarch64/sme-9.d: New test. * testsuite/gas/aarch64/sme-9.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_SME_PnT_Wm_imm. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_sme_pred_reg_with_index): New inserter. * aarch64-dis.c (aarch64_ext_sme_pred_reg_with_index): New extractor. * aarch64-opc.c (aarch64_print_operand): Printout of OPND_SME_PnT_Wm_imm. * aarch64-opc.h (enum aarch64_field_kind): New bitfields FLD_SME_Rm, FLD_SME_i1, FLD_SME_tszh, FLD_SME_tszl. * aarch64-tbl.h (OP_SVE_NN_BHSD): New qualifier. (OP_SVE_QMQ): New qualifier. (struct aarch64_opcode): New instructions PSEL, REVD, SCLAMP and UCLAMP. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
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