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* ChangeLog formatting fixesAlan Modra2016-12-221-2/+2
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* Support aligning text section from odd addressesAndrew Waterman2016-12-222-6/+21
| | | | | | | | | | | | | | Previously, the alignment directives were not correctly supported in the text section when current alignment was only 1 byte (i.e., when the address was odd). Since there are no 1-byte instructions in RISC-V, this patch resolves the bug by writing a zero byte to obtain 2-byte alignment, at which point a 2-byte NOP can be used to obtain 4-byte alignment. Resolves https://github.com/riscv/riscv-gnu-toolchain/issues/205 * config/tc-riscv.c (riscv_make_nops): Emit 2-byte NOPs. (riscv_frag_align_code): Correct frag_align_code arg.
* Fix a const-safety issue on GCC-4.9 and aboveTim Newsome2016-12-222-1/+6
| | | | | * config/tc-riscv.c (riscv_pre_output_hook): Remove const from loc4_frag.
* Remove high bit set charactersAlan Modra2016-12-213-6/+11
| | | | | | | | | | | | | gas/ * doc/c-lm32.texi: Fix chars with high bit set. * testsuite/gas/bfin/vector2.s: Likewise. gold/ * arm.cc: Fix comment chars with high bit set. include/ * coff/pe.h: Fix comment chars with high bit set. * opcode/xgate.h: Likewise. ld/ * testsuite/ld-scripts/sysroot-prefix.exp: Fix chars with high bit set.
* Document character escape sequencesAlan Modra2016-12-212-6/+12
| | | | | PR gas/10946 * doc/as.texinfo (Chars): Document escape sequences.
* MIPS16/opcodes: Respect ISA and ASE in disassemblyMaciej W. Rozycki2016-12-2015-0/+1681
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Limit MIPS16 instruction disassembly according to the ISA level and ASE set selected, as with the regular MIPS and microMIPS instruction sets. Retain the property of `objdump -m mips:16' disassembling all MIPS16 instructions however, regardless of any ISA level recorded in the binary examined. To validate the disassembler use the GAS test suite for its convenience of running tests across multiple ISAs, even though placing the tests in the binutils test suite would be more appropriate. Adjust the single binutils test which depends on 64-bit instruction disassembly to have the ISA level required actually recorded in the binary examined. opcodes/ * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry. (print_insn_mips16): Check opcode entries for validity against the ISA level and ASE set selected. binutils/ * testsuite/binutils-all/mips/mips16-undecoded.s: Use `.module' rather than `.set' to set the ISA level. gas/ * testsuite/gas/mips/mips16-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16-sub.d: New test. * testsuite/gas/mips/mips16e-32@mips16-sub.d: New test. * testsuite/gas/mips/mips16e-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16e-sub.d: New test. * testsuite/gas/mips/mips16-64@mips16e-sub.d: New test. * testsuite/gas/mips/mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-64@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16e-32@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-sub.s: New test source. * testsuite/gas/mips/mips16e-sub.s: New test source. * testsuite/gas/mips/mips16e-64-sub.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
* MIPS/GAS/testsuite: Add RESTORE instruction to `mips16e' testMaciej W. Rozycki2016-12-203-1/+8
| | | | | | | | Add a RESTORE instruction smoke test to the `mips16e' GAS test. gas/ * testsuite/gas/mips/mips16e.s: Add a RESTORE instruction. * testsuite/gas/mips/mips16e.d: Adjust accordingly.
* MIPS/GAS/testsuite: Extend MIPS16 testing over multiple ISAsMaciej W. Rozycki2016-12-2024-167/+1990
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Run the `mips16', `mips16-64', `mips16e-64', `mips16-macro', `mips16-macro-e' and `mips16-macro-t' GAS tests over multiple MIPS16 ISAs. gas/ * testsuite/gas/mips/mips16.d: Adjust test for multiple MIPS16 ISA testing. * testsuite/gas/mips/mips16-64.d: Adjust test for multiple MIPS16 ISA testing. * testsuite/gas/mips/mips16e-64.d: Adjust test for multiple MIPS16 ISA testing. * testsuite/gas/mips/mips16-macro.d: Adjust test for multiple MIPS16 ISA testing. * testsuite/gas/mips/mips16e-64.s: Ensure MIPS16 ISA annotation. * testsuite/gas/mips/mips16e-64.l: Rename to... * testsuite/gas/mips/mips16e-32@mips16e-64.l: ... this. * testsuite/gas/mips/mips16-64@mips16.d: New test. * testsuite/gas/mips/mips16-64@mips16-64.d: New test. * testsuite/gas/mips/mips16e-32@mips16e-64.d: New test. * testsuite/gas/mips/mips16-32@mips16-macro.d: New test. * testsuite/gas/mips/mips16-64@mips16-macro.d: New test. * testsuite/gas/mips/mips16e-32@mips16-macro.d: New test. * testsuite/gas/mips/mips16-32@mips16-macro-e.d: New test. * testsuite/gas/mips/mips16e-32@mips16-macro-e.d: New test. * testsuite/gas/mips/mips16-32@mips16-macro-t.d: New test. * testsuite/gas/mips/mips16e-32@mips16-macro-t.d: New test. * testsuite/gas/mips/mips16e-32@mips16e-64.l: New stderr output. * testsuite/gas/mips/mips16-32@mips16-macro.l: New stderr output. * testsuite/gas/mips/mips16e-32@mips16-macro.l: New stderr output. * testsuite/gas/mips/mips16-32@mips16-macro-e.l: New stderr output. * testsuite/gas/mips/mips16e-32@mips16-macro-e.l: New stderr output. * testsuite/gas/mips/mips16-32@mips16-macro-t.l: New stderr output. * testsuite/gas/mips/mips16e-32@mips16-macro-t.l: New stderr output. * testsuite/gas/mips/mips.exp: Run `mips16', `mips16-64', `mips16-macro', `mips16-macro-t', `mips16-macro-e' and `mips16e-64' testing across multiple MIPS16 ISAs. Fold `mips16-macro' and `mips16e-64' list test invocations into corresponding dump tests.
* MIPS/GAS/testsuite: Implement individual MIPS16 ISA testingMaciej W. Rozycki2016-12-206-7/+177
| | | | | | | | | | | | | | | | | | Implement individual MIPS16 ISA GAS testing for the 32-bit and 64-bit variants of the base MIPS16 and the MIPS16e ISA each. gas/ * testsuite/gas/mips/mips.exp (run_dump_test_arch): Add `mips16e' and `mips16' prefixes. (run_list_test_arch): Likewise. Rename `mips16' architecture to `mips16-32'. Add `mips16-64', `mips16e-32' and `mips16e-64' architectures. Update `rol64', `mips16e', `elf${el}-rel2' and `elf-rel4' test invocations accordingly. * testsuite/gas/mips/mips16e@branch-swap-3.d: New test. * testsuite/gas/mips/mips16e@branch-swap-4.d: New test. * testsuite/gas/mips/mips16e@loc-swap-dis.d: New test. * testsuite/gas/mips/mips16e@loc-swap.d: New test.
* MIPS/GAS/testsuite: Fix trailing padding in `loc-swap.s'Maciej W. Rozycki2016-12-205-4/+11
| | | | | | | | | | | | Pad alignment with zeros rather than NOP instructions, for sensible multi-ISA MIPS16 testing. gas/ * testsuite/gas/mips/loc-swap.s: Use zeros rather than NOPs for trailing alignment padding. * testsuite/gas/mips/loc-swap.d: Adjust accordingly. * testsuite/gas/mips/micromips@loc-swap.d: Likewise. * testsuite/gas/mips/mips16@loc-swap-dis.d: Likewise.
* MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki2016-12-2014-24/+375
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch to 32-bit MIPS16 opcode table entry interpretation, similar to how the microMIPS opcode table is handled, for both the `match' and `mask' fields, removing special casing for JAL and JALX instructions and their `a' and `i' operand codes throughout, while retaining automatic processing of extendable opcodes in assembly and disassembly. In assembly disallow size enforcement suffixes as appropriate: `.t' for both 32-bit instructions and macros and `.e' for macros only, making macro handling consistent with the microMIPS instruction set. In disassembly fully decode EXTEND prefixes prepended to unsupported instruction encodings (according to the ISA selection) rather than dumping them as hexadecimal data along with the following instruction, removing all special casing for the EXTEND prefix and making its handling rely on its opcode table entry, except where it is considered a part of an extendable instruction. include/ * opcode/mips.h (mips_opcode_32bit_p): New inline function. gas/ * config/tc-mips.c (micromips_insn_length): Use `mips_opcode_32bit_p'. (is_size_valid): Adjust description. (is_size_valid_16): New function. (validate_mips_insn): Use `mips_opcode_32bit_p' in MIPS16 operand decoding. (validate_mips16_insn): Remove `a' and `i' operand code special casing, use `mips_opcode_32bit_p' to determine instruction width. (append_insn): Adjust forced MIPS16 instruction size determination. (match_mips16_insn): Likewise. Don't shift the instruction's opcode with the `a' and `i' operand codes. Use `mips_opcode_32bit_p' in operand decoding. (match_mips16_insns): Check for forced instruction size's validity. (mips16_ip): Don't force instruction size in the `noautoextend' mode. * testsuite/gas/mips/mips16-jal-e.d: New test. * testsuite/gas/mips/mips16-jal-t.d: New test. * testsuite/gas/mips/mips16-macro-e.d: New test. * testsuite/gas/mips/mips16-macro-t.d: New test. * testsuite/gas/mips/mips16-jal-t.l: New stderr output. * testsuite/gas/mips/mips16-macro-e.l: New stderr output. * testsuite/gas/mips/mips16-macro-t.l: New stderr output. * testsuite/gas/mips/mips16-jal-e.s: New test source. * testsuite/gas/mips/mips16-jal-t.s: New test source. * testsuite/gas/mips/mips16-macro-e.s: New test source. * testsuite/gas/mips/mips16-macro-t.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. opcodes/ * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and `insn' together, with `extend' as the high-order 16 bits. (match_kind): New enum. (print_insn_mips16): Rework for 32-bit instruction matching. Do not dump EXTEND prefixes here. * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end. Recode `match' and `mask' fields as 32-bit in absolute "jal" and "jalx" entries. binutils/ * testsuite/binutils-all/mips/mips16-extend-noinsn.d: Adjust test for separate EXTEND prefix disassembly.
* MIPS16/opcodes: Correct 64-bit macros' ISA membershipMaciej W. Rozycki2016-12-203-0/+18
| | | | | | | | | | | | | | | | | | | Limit the DDIV, DDIVU, DREM, DREMU and DSUBU macros to the MIPS III rather than MIPS I ISA. These macros expand to machine code sequences including 64-bit instructions which require a 64-bit ISA. Entries for those instructions are already correctly marked, however the marking is ignored if entries are used in the process of macro expansion rather than directly, making it possible to indirectly produce 64-bit machine code even when output requested has been limited to a 32-bit ISA. opcodes/ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu" INSN_MACRO entries. gas/ * testsuite/gas/mips/mips16-macro.l: New list test. * testsuite/gas/mips/mips.exp: Run the new test.
* MIPS16/opcodes: Correct I64/SDRASP opcode's ISA membershipMaciej W. Rozycki2016-12-205-0/+20
| | | | | | | | | | | | | | | | | | Limit the `SD ra, offset(sp)' instruction (I64/SDRASP major/minor opcode) to the MIPS III rather than MIPS I ISA. This is a 64-bit instruction requiring a 64-bit ISA. This bug has been there since forever. opcodes/ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather than I1 for the SP-relative "sd"/$ra entry (SDRASP minor opcode). gas/ * testsuite/gas/mips/mips16-sdrasp.d: New test. * testsuite/gas/mips/mips16-sdrasp.l: New stderr output. * testsuite/gas/mips/mips16-sdrasp.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
* MIPS/GAS/testsuite: Correct NewABI test selectionMaciej W. Rozycki2016-12-202-27/+84
| | | | | | | | | Make sure all tests that require NewABI support are only run with `has_newabi' targets, removing numerous `mips-sgi-irix5' failures. gas/ * testsuite/gas/mips/mips.exp: Limit remaining tests that require NewABI support to `has_newabi' targets.
* Don't define RISC-V .p2alignAndrew Waterman2016-12-203-42/+82
| | | | | | | | | | | | | | * config/tc-riscv.c (riscv_pseudo_table): Remove "align", "p2align", and "balign". (s_align): Remove. (riscv_handle_align): New function. (riscv_frag_align_code): Likewise. (riscv_make_nops): Likewise. * config/tc-riscv.h (MAX_MEM_FOR_RS_ALIGN_CODE): Change to 7. (HANDLE_ALIGN): Define. (md_do_align): Define. (riscv_handle_align): Declare. (riscv_frag_align_code): Likewise.
* Re-work RISC-V gas flags: now we just support -mabi and -marchAndrew Waterman2016-12-205-123/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've decided to standardize on two flags for RISC-V: "-march" sets the target architecture (which determines which instructions can be generated), and "-mabi" sets the target ABI. We needed to rework this because the old flag set didn't support soft-float or single-float ABIs, and didn't support an x32-style ABI on RISC-V. Additionally, we've changed the behavior of the -march flag: it's now a lot stricter and only parses things we can actually understand. Additionally, it's now lowercase-only: the rationale is that while the RISC-V ISA manual specifies that ISA strings are case-insensitive, in Linux-land things are usually case-sensitive. Since this flag can be used to determine library paths, we didn't want to bake some case-insensitivity in there that would case trouble later. This patch implements these two new flags and removes the old flags that could conflict with these. There wasn't a RISC-V release before, so we want to just support a clean flag set. include/ * elf/riscv.h (EF_RISCV_SOFT_FLOAT): Don't define. (EF_RISCV_FLOAT_ABI, EF_RISCV_FLOAT_ABI_SOFT): Define. (EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI_DOUBLE): Define. (EF_RISCV_FLOAT_ABI_QUAD): Define. bfd/ * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Use EF_RISCV_FLOAT_ABI_SOFT instead of EF_RISCV_SOFT_FLOAT. binutils/ * readelf.c (get_machine_flags): Use EF_RISCV_FLOAT_ABI_{SOFT,SINGLE,DOBULE,QUAD) instead of EF_RISCV_{SOFT,HARD}_FLOAT. gas/ * config/tc-riscv.h (xlen): Delete. * config/tc-riscv.c (xlen): Make static. (abi_xlen): New variable. (options): Replace OPTION_{M32,M64,MSOFT_FLOAT,MHARD_FLOAT,MRVC} with OPTION_MABI. (md_longopts): Likewise. (md_parse_option): Likewise. (riscv_elf_final_processing): Likewise. * doc/as.texinfo (Target RISC-V options): Likewise. * doc/c-riscv.texi (OPTIONS): Likewise. * config/tc-riscv.c (float_mode): Removed. (float_abi): New type, specifies the floating-point ABI. (riscv_set_abi): New function. (riscv_add_subset): Only allow lower-case ISA names and require them to start with "rv". (riscv_after_parse_args): Likewise. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's XLEN when none is provided.
* Rework RISC-V relocationsAndrew Waterman2016-12-203-54/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit we didn't cleanly support CFI directives because the internal offsets used to get relaxed which broke them. This patch significantly reworks how we handle linker relaxations: * DWARF is now properly supported * There is a ".option norelax" to disable relaxations, for when users write assembly that can't be relaxed (if it's to be later patched up, for example). * There is an additional _RELAX relocation that specifies when previous relocations can be relaxed. We're in the process of documenting the RISC-V ELF ABI, which will include documentation of our relocations https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md but we expect that this relocation set will remain ABI compatible in the future (ie, it's safe to release). Thanks to Kuan-Lin Chen for figuring out how to correctly relax the debug info! include/ * elf/riscv.h: Add R_RISCV_TPREL_I through R_RISCV_SET32. bfd/ * reloc.c (BFD_RELOC_RISCV_TPREL_I): New relocation. (BFD_RELOC_RISCV_TPREL_S): Likewise. (BFD_RELOC_RISCV_RELAX): Likewise. (BFD_RELOC_RISCV_CFA): Likewise. (BFD_RELOC_RISCV_SUB6): Likewise. (BFD_RELOC_RISCV_SET8): Likewise. (BFD_RELOC_RISCV_SET8): Likewise. (BFD_RELOC_RISCV_SET16): Likewise. (BFD_RELOC_RISCV_SET32): Likewise. * elfnn-riscv.c (perform_relocation): Handle the new relocations. (_bfd_riscv_relax_tls_le): Likewise. (_bfd_riscv_relax_align): Likewise. (_bfd_riscv_relax_section): Likewise. (howto_table): Likewise. (riscv_reloc_map): Likewise. (relax_func_t): New type. (_bfd_riscv_relax_call): Add reserve_size argument, which controls the maximal offset pessimism. Correct type of max_alignment. (_bfd_riscv_relax_lui): Likewise. (_bfd_riscv_relax_tls_le): Likewise. (_bfd_riscv_relax_align): Likewise. (_bfd_riscv_relax_section): Compute the required reserve size when relocating and use it to when calling relax_func. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. gas/ * config/tc-riscv.c (riscv_set_options): Add relax. (riscv_opts): Likewise. (s_riscv_option): Add relax and norelax. (riscv_apply_const_reloc): New function. (append_insn): Move constant relocation handling to riscv_apply_const_reloc. (md_pcrel_from): Likewise. (parse_relocation): Skip BFD_RELOC_UNUSED. (md_pcrel_from): Handle BFD_RELOC_RISCV_SUB6, BFD_RELOC_RISCV_RELAX, BFD_RELOC_RISCV_CFA. (md_apply_fix): Likewise. (riscv_pre_output_hook): New function. * config/tc-riscv.h (md_pre_output_hook): Define. (riscv_pre_output_hook): Declare. (DWARF_CIE_DATA_ALIGNMENT): Always -4.
* Formatting changes for RISC-VAndrew Waterman2016-12-202-27/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | This is a mixed bag of format changes: * Replacing constants with macros (0xffffffff with MINUS_ONE, for example). There's one technically functional change in here (some MINUS_ONEs are changed to 0), but it only changes the behavior of an otherwise-unused field. * Using 0 instead of 0x0 in the relocation table. * There were some missing spaces before parens, the spaces have been added. * A handful of comments are now more descriptive. * A bunch of whitespace-only changes, mostly alignment and brace newlines. bfd/ * elfnn-riscv.c: Formatting and comment fixes throughout. * elfxx-riscv.c: Likewise. (howto_table): Change the src_mask field from MINUS_ONE to 0 for R_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPMOD64, R_RISCV_TLS_DTPREL32, R_RISCV_TLS_DTPREL64, R_RISCV_TLS_TPREL32, R_RISCV_TLS_TPREL64. opcodes/ * riscv-opc.c: Formatting fixes. gas/ * config/tc-riscv.c: Formatting and comment fixes throughout.
* MIPS16/GAS: Fix assertion failures with relocations on 16-bit instructionsMaciej W. Rozycki2016-12-148-3/+50
| | | | | | | | | | | | | | | | | | | | | Complement commit c9775dde3277 ("MIPS16: Add R_MIPS16_PC16_S1 branch relocation support)" and report an assembly error when a relocation is required for an instruction, currently a branch only, that has been forced to use its unextended encoding, either with the use of an explicit `.t' mnemonic suffix, or by means of `.set noautoextend' being active, fixing an assertion failure currently caused instead. gas/ * config/tc-mips.c (md_convert_frag): Report an error instead of asserting on `ext'. * testsuite/gas/mips/mips16-branch-unextended-1.d: New test. * testsuite/gas/mips/mips16-branch-unextended-2.d: New test. * testsuite/gas/mips/mips16-branch-unextended-1.s: New test source. * testsuite/gas/mips/mips16-branch-unextended-2.s: New test. * testsuite/gas/mips/mips16-branch-unextended.l: New stderr output. * testsuite/gas/mips/mips.exp: Run the new tests.
* MIPS16: Fix SP-relative SD instruction annotationMaciej W. Rozycki2016-12-144-0/+51
| | | | | | | | | | | | | | | | Fix the annotation of SP-relative SD instructions incorrectly marked as reading from the PC rather than SP, which in turn prevented their 16-bit forms from being scheduled into jump delay slots. This bug has been there since forever. opcodes/ * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in `pinfo2' with SP-relative "sd" entries. gas/ * testsuite/gas/mips/mips16-sprel-swap.d: New test. * testsuite/gas/mips/mips16-sprel-swap.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
* [Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li2016-12-134-123/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The internal CN register representation for coprocessor fields used in aarch64 sys, sysl instructions are removed in this patch. After the change, those fields are represented as immediate. Related checks are added as well. opcodes/ * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range qualifier. (operand_general_constraint_met_p): Remove case for CP_REG. (aarch64_print_operand): Print CRn, CRm operand using imm field. * aarch64-tbl.h (QL_SYS): Use CR qualifier. (QL_SYSL): Likewise. (aarch64_opcode_table): Change CRn, CRm operand class and type. * aarch64-opc-2.c : Regenerate. * aarch64-asm-2.c : Likewise. * aarch64-dis-2.c : Likewise. include/ * opcode/aarch64.h (aarch64_operand_class): Remove AARCH64_OPND_CLASS_CP_REG. (enum aarch64_opnd): Change AARCH64_OPND_Cn to AARCH64_OPND_CRn, AARCH64_OPND_Cm to AARCH64_OPND_CRm. (aarch64_opnd_qualifier): Define AARCH64_OPND_QLF_CR qualifier. gas/ * config/tc-aarch64.c (AARCH64_REG_TYPES): Remove CN register. (get_reg_expected_msg): Remove CN register case. (parse_operands): rewrite parser for CRn, CRm operand. (reg_names): Remove CN register. * testsuite/gas/aarch64/diagnostic.s: Add a new test case. * testsuite/gas/aarch64/diagnostic.l: Adjust error message.
* [AArch64] Make GAS testcases support ILP32 modeJiong Wang2016-12-13110-210/+346
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ * gas/testsuite/gas/aarch64/addsub.d: Support ILP32 mode. * gas/testsuite/gas/aarch64/advsimd-across.d: Likewise. * gas/testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise. * gas/testsuite/gas/aarch64/advsimd-fp16.d: Likewise. * gas/testsuite/gas/aarch64/advsimd-misc.d: Likewise. * gas/testsuite/gas/aarch64/advsisd-copy.d: Likewise. * gas/testsuite/gas/aarch64/advsisd-misc.d: Likewise. * gas/testsuite/gas/aarch64/alias.d: Likewise. * gas/testsuite/gas/aarch64/armv8-ras-1.d: Likewise. * gas/testsuite/gas/aarch64/b_1.d: Likewise. * gas/testsuite/gas/aarch64/beq_1.d: Likewise. * gas/testsuite/gas/aarch64/bitfield-dump: Likewise. * gas/testsuite/gas/aarch64/bitfield-no-aliases.d: Likewise. * gas/testsuite/gas/aarch64/codealign.d: Likewise. * gas/testsuite/gas/aarch64/codealign_1.d: Likewise. * gas/testsuite/gas/aarch64/crc32-directive.d: Likewise. * gas/testsuite/gas/aarch64/crc32.d: Likewise. * gas/testsuite/gas/aarch64/crypto-directive.d: Likewise. * gas/testsuite/gas/aarch64/crypto.d: Likewise. * gas/testsuite/gas/aarch64/dwarf.d: Likewise. * gas/testsuite/gas/aarch64/float-fp16.d: Likewise. * gas/testsuite/gas/aarch64/floatdp2.d: Likewise. * gas/testsuite/gas/aarch64/fp-armv8_3.d: Likewise. * gas/testsuite/gas/aarch64/fp-const0-parse.d: Likewise. * gas/testsuite/gas/aarch64/fp_cvt_int.d: Likewise. * gas/testsuite/gas/aarch64/fpmov.d: Likewise. * gas/testsuite/gas/aarch64/inst-directive.d: Likewise. * gas/testsuite/gas/aarch64/ldr_1.d: Likewise. * gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Likewise. * gas/testsuite/gas/aarch64/ldst-exclusive.d: Likewise. * gas/testsuite/gas/aarch64/ldst-reg-imm-post-ind.d: Likewise. * gas/testsuite/gas/aarch64/ldst-reg-imm-pre-ind.d: Likewise. * gas/testsuite/gas/aarch64/ldst-reg-pair.d: Likewise. * gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d: Likewise. * gas/testsuite/gas/aarch64/ldst-reg-uns-imm.d: Likewise. * gas/testsuite/gas/aarch64/ldst-reg-unscaled-imm.d: Likewise. * gas/testsuite/gas/aarch64/lor-directive.d: Likewise. * gas/testsuite/gas/aarch64/lor.d: Likewise. * gas/testsuite/gas/aarch64/lse-atomic.d: Likewise. * gas/testsuite/gas/aarch64/mapmisc.d: Likewise. * gas/testsuite/gas/aarch64/mov-no-aliases.d: Likewise. * gas/testsuite/gas/aarch64/mov.d: Likewise. * gas/testsuite/gas/aarch64/movi.d: Likewise. * gas/testsuite/gas/aarch64/movw_label.d: Likewise. * gas/testsuite/gas/aarch64/msr.d: Likewise. * gas/testsuite/gas/aarch64/neon-fp-cvt-int.d: Likewise. * gas/testsuite/gas/aarch64/neon-frint.d: Likewise. * gas/testsuite/gas/aarch64/neon-ins.d: Likewise. * gas/testsuite/gas/aarch64/neon-not.d: Likewise. * gas/testsuite/gas/aarch64/neon-vfp-reglist-post.d: Likewise. * gas/testsuite/gas/aarch64/neon-vfp-reglist.d: Likewise. * gas/testsuite/gas/aarch64/no-aliases.d: Likewise. * gas/testsuite/gas/aarch64/optional.d: Likewise. * gas/testsuite/gas/aarch64/pac.d: Likewise. * gas/testsuite/gas/aarch64/pan-directive.d: Likewise. * gas/testsuite/gas/aarch64/pan.d: Likewise. * gas/testsuite/gas/aarch64/rdma-directive.d: Likewise. * gas/testsuite/gas/aarch64/rdma.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_g0.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_g0_nc.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_g1.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_hi12.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_lo12-1.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc.d: Likewise. * gas/testsuite/gas/aarch64/reloc-tlsldm-1.d: Likewise. * gas/testsuite/gas/aarch64/reloc-tlsldm-page-1.d: Likewise. * gas/testsuite/gas/aarch64/reloc-tlsldm_lo12_nc-1.d: Likewise. * gas/testsuite/gas/aarch64/shifted.d: Likewise. * gas/testsuite/gas/aarch64/sve.d: Likewise. * gas/testsuite/gas/aarch64/symbol.d: Likewise. * gas/testsuite/gas/aarch64/sysreg-1.d: Likewise. * gas/testsuite/gas/aarch64/sysreg-2.d: Likewise. * gas/testsuite/gas/aarch64/sysreg-3.d: Likewise. * gas/testsuite/gas/aarch64/sysreg.d: Likewise. * gas/testsuite/gas/aarch64/system-2.d: Likewise. * gas/testsuite/gas/aarch64/system-3.d: Likewise. * gas/testsuite/gas/aarch64/system.d: Likewise. * gas/testsuite/gas/aarch64/tbz_1.d: Likewise. * gas/testsuite/gas/aarch64/tlbi_op.d: Likewise. * gas/testsuite/gas/aarch64/tls.d: Likewise. * gas/testsuite/gas/aarch64/uao-directive.d: Likewise. * gas/testsuite/gas/aarch64/uao.d: Likewise. * gas/testsuite/gas/aarch64/virthostext-directive.d: Likewise. * gas/testsuite/gas/aarch64/virthostext.d: Likewise. * gas/testsuite/gas/aarch64/adr_1.d: Restrict test under -mabi=lp64. * gas/testsuite/gas/aarch64/int-insns.d: Likewise. * gas/testsuite/gas/aarch64/programmer-friendly.d: Likewise. * gas/testsuite/gas/aarch64/reloc-data.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_g1_nc.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_g2.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst16.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst32.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst64.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst8.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst16.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst32.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst64.d: Likewise. * gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst8.d: Likewise. * gas/testsuite/gas/aarch64/reloc-gotoff_g0_nc.d: Likewise. * gas/testsuite/gas/aarch64/reloc-gotoff_g1.d: Likewise. * gas/testsuite/gas/aarch64/reloc-gottprel_g0_nc.d: Likewise. * gas/testsuite/gas/aarch64/reloc-gottprel_g1.d: Likewise. * gas/testsuite/gas/aarch64/reloc-insn.d: Likewise. * gas/testsuite/gas/aarch64/reloc-tlsdesc_off_g0_nc.d: Likewise. * gas/testsuite/gas/aarch64/reloc-tlsdesc_off_g1.d: Likewise. * gas/testsuite/gas/aarch64/reloc-tlsgd_g0_nc.d: Likewise. * gas/testsuite/gas/aarch64/reloc-tlsgd_g1.d: Likewise. * gas/testsuite/gas/aarch64/tail_padding.d: Likewise. * gas/testsuite/gas/aarch64/tls-desc.d: Likewise.
* MIPS16: Remove unused `>' operand codeMaciej W. Rozycki2016-12-092-1/+4
| | | | | | | | | | | | | | | | This code has never been used throughout the repository history, and likely not before either, as due to the assymetry of MIPS16 instruction set encoding there are no 32-bit shift operations having their immediate shift count placed in the position of the usual `rx' instruction field. gas/ * config/tc-mips.c (mips16_macro_build) <'>'>: Remove case. include/ * opcode/mips.h: Remove references to `>' operand code. opcodes/ * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
* MIPS16/opcodes: Use hexadecimal interpretation for the `e' operand codeMaciej W. Rozycki2016-12-094-0/+46
| | | | | | | | | | | | | | | | | | Make the `e' operand code used with raw EXTEND instructions use the hexadecimal rather than decimal format, for consistency with what is actually produced by code in `print_insn_mips16' dedicated to EXTEND disassembly. Due to that special handling the operand code is only interpreted for assembly however, which accepts either format either way, so there is no functional change here. opcodes/ * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather than UINT. gas/ * testsuite/gas/mips/mips16-extend.d: New test. * testsuite/gas/mips/mips16-extend.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
* ARC/GAS: Correct a `spaces' global shadowing errorMaciej W. Rozycki2016-12-082-5/+10
| | | | | | | | | | | | | | | | | | Fix a commit a9752fdf8398 ("[ARC] Sync cpu names with the ones accepted by GCC.") build regression: cc1: warnings being treated as errors .../gas/config/tc-arc.c: In function 'arc_show_cpu_list': .../gas/config/tc-arc.c:3452: error: declaration of 'spaces' shadows a global declaration .../gas/../include/libiberty.h:248: error: shadowed declaration is here make[4]: *** [tc-arc.o] Error 1 in a way following commit 91d6fa6a035c ("Add -Wshadow to the gcc command line options used when compiling the binutils."). gas/ * config/tc-arc.c (arc_show_cpu_list): Rename `spaces' local variable to `space_buf'.
* ARM/GAS: Correct an `index' global shadowing errorMaciej W. Rozycki2016-12-082-4/+9
| | | | | | | | | | | | | | | | | | | Fix a commit 008a97eff0ca ("[GAS][ARM]Generate unpredictable warning for pc used in data processing instructions with register-shifted register operand.") build regression: cc1: warnings being treated as errors .../gas/config/tc-arm.c: In function 'encode_arm_shift': .../gas/config/tc-arm.c:7439: error: declaration of 'index' shadows a global declaration /usr/include/string.h:303: error: shadowed declaration is here make[4]: *** [tc-arm.o] Error 1 in a way following commit 91d6fa6a035c ("Add -Wshadow to the gcc command line options used when compiling the binutils."). gas/ * config/tc-arm.c (encode_arm_shift): Rename `index' local variable to `op_index'.
* sync binutils config/ with gccAlan Modra2016-12-082-1/+5
| | | | | | | | | | | | | | | | | config/ * acx.m4: Import from gcc. * bootstrap-asan.mk: Likewise. * multi.m4: Likewise. / * configure: Regnerate. gas/ * configure: Regnerate. ld/ * configure: Regnerate. libiberty/ * configure: Regnerate. zlib/ * configure: Regnerate.
* MIPS/GAS: Use local `isa' consistently in `is_opcode_valid'Maciej W. Rozycki2016-12-072-1/+6
| | | | | | | | | Replace a global `mips_opts.isa' reference in `is_opcode_valid' and use a local copy just made in `isa'. No functional change. gas/ * config/tc-mips.c (is_opcode_valid): Use local `isa' consistently.
* fix typoNick Clifton2016-12-061-1/+1
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* Stop the assembler from running out of memory when asked to generate a huge ↵Nick Clifton2016-12-062-5/+18
| | | | | | | | number of spaces. PR gas/20901 * read.c (s_space): Place an upper limit on the number of spaces generated.
* Fix mmix assembler test to account for changes in the error messages ↵Nick Clifton2016-12-062-2/+9
| | | | | | | | produced by the assembler. PR gas/20896 * testsuite/gas/mmix/err-byte1.s: Adjust expected warning messages to account for patch to next_char_of_string.
* Fix fault in assembler when passed a bogus input file.Nick Clifton2016-12-052-0/+16
| | | | | | PR gas/20902 * read.c (next_char_of_string): Do end advance past the end of the buffer.
* Fix ICE in assembler when passed a bogus input file.Nick Clifton2016-12-053-2/+11
| | | | | | PR gas/20904 * as.h (SKIP_ALL_WHITESPACE): New macro. * expr.c (operand): Use it.
* [ARM] Add ARMv8.3 VCMLA and VCADD instructionsSzabolcs Nagy2016-12-057-0/+281
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for VCMLA and VCADD advanced SIMD complex number instructions. The command line option is -march=armv8.3-a+fp16+simd for enabling all instructions. In arm-dis.c the formatting syntax was abused a bit to select between 0 vs 90 or 180 vs 270 or 90 vs 270 based on a bit value instead of duplicating entries in the opcode table. gas/ * config/tc-arm.c (do_vcmla, do_vcadd): Define. (neon_scalar_for_vcmla): Define. (enum operand_parse_code): Add OP_IROT1 and OP_IROT2. (NEON_ENC_TAB): Add DDSI and QQSI variants. (insns): Add vcmla and vcadd. * testsuite/gas/arm/armv8_3-a-simd.d: New. * testsuite/gas/arm/armv8_3-a-simd.s: New. * testsuite/gas/arm/armv8_3-a-simd-bad.d: New. * testsuite/gas/arm/armv8_3-a-simd-bad.l: New. * testsuite/gas/arm/armv8_3-a-simd-bad.s: New. opcodes/ * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd. (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
* [ARC] Don't check extAuxRegister second argument for sign.Claudiu Zissulescu2016-12-056-11/+47
| | | | | | | | | | | | | | | gas/ 2016-12-05 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/textauxregister-1.d: New file. * testsuite/gas/arc/textauxregister-1.s: Likewise. * testsuite/gas/arc/textcondcode-err.s: Likewise. * testsuite/gas/arc/textcoreregister-err.s: Likewise. * config/tc-arc.c (tokenize_extregister): Return bfd_boolean, don't check second argument of extension auxiliary register for signess. (arc_extcorereg): Consider the return of tokenize_extregister function call.
* [ARM] Add ARMv8.3 VJCVT instructionSzabolcs Nagy2016-12-057-0/+68
| | | | | | | | | | | | | | | | Add support for VJCVT javascript conversion instruction. gas/ * config/tc-arm.c (arm_ext_v8_3, do_vjcvt): Define. (insns): Add vjcvt. * testsuite/gas/aarch64/armv8_3-a-fp.s: New. * testsuite/gas/aarch64/armv8_3-a-fp.d: New. * testsuite/gas/aarch64/armv8_3-a-fp-bad.s: New. * testsuite/gas/aarch64/armv8_3-a-fp-bad.d: New. * testsuite/gas/aarch64/armv8_3-a-fp-bad.l: New. opcodes/ * arm-dis.c (coprocessor_opcodes): Add vjcvt.
* [ARM] Add ARMv8.3 command line option and feature flagSzabolcs Nagy2016-12-053-0/+7
| | | | | | | | | | | | | | | | ARMv8.3 is an architectural extension of ARMv8. Add the feature macro and -march=armv8.3-a gas command line option for the ARM target. https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions gas/ * config/tc-arm.c (arm_archs): Add "armv8.3-a". * doc/c-arm.texi (-march): Add "armv8.3-a". include/ * opcode/arm.h (ARM_EXT2_V8_3A, ARM_AEXT2_V8_3A): New. (ARM_ARCH_V8_3A): New.
* [ARC] Sync cpu names with the ones accepted by GCC.Claudiu Zissulescu2016-12-029-22/+237
| | | | | | | | | | | | | | | | | | | | | | | | gas/ 2016-12-02 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/cpu-em-err.s: New file. * testsuite/gas/arc/cpu-em4-err.s: Likewise. * testsuite/gas/arc/cpu-fpuda-err.s: Likewise. * testsuite/gas/arc/cpu-hs-err.s: Likewise. * testsuite/gas/arc/cpu-quarkse-err.s: Likewise. * testsuite/gas/arc/noargs_a7.s: Add .cpu. * config/tc-arc.c (ARC_CPU_TYPE_A6xx): Define. (ARC_CPU_TYPE_A7xx): Likewise. (ARC_CPU_TYPE_AV2EM): Likewise. (ARC_CPU_TYPE_AV2HS): Likewise. (cpu_types): Update list of known CPU names. (arc_show_cpu_list): New function. (md_show_usage): Print accepted CPU names. (cl_features): New variable. (arc_select_cpu): Use cl_features. (arc_option): Allow various .cpu names. (md_parse_option): Set cl_features. * doc/c-arc.texi: Update -mcpu and .cpu documentation.
* Add support for Fushia OS.Josh Conner2016-12-022-0/+7
| | | | | | | | | | | | | | | | * configure.ac: Add fuchsia to targets that use ELF. * configure: Regenerated. bfd * configure.tgt: Add support for fuchsia (OS). gas * configure.tgt: Add support for fuchsia (OS). ld * Makefile.am: Add dependency information for earmelf_fuchsia.c. * Makefile.in: Regenerate. * configure.tgt: Add support for aarch64-*-fuchsia, arm*-*-fuchsia*, and x86_64-*-fuchsia* targets. * emulparams/armelf_fuchsia.sh: New file. * emulparams/armelfb_fuchsia.sh: New file.
* Fix seg fault attempting to unget an EOF character.Nick Clifton2016-12-012-1/+4
| | | | | PR gas/20898 * app.c (do_scrub_chars): Do not attempt to unget EOF.
* Fix seg-fault printing assembler statistics when the output file was not ↵Nick Clifton2016-12-012-0/+8
| | | | | | | | created. PR gas/20897 * subsegs.c (subsegs_print_statistics): Do nothing if no output file was created.
* Fix ICE in assembler when passed a corrupt input file.Nick Clifton2016-12-012-1/+16
| | | | | | PR gas/20895 * symbols.c (resolve_symbol_value): Gracefully handle erroneous symbolic expressions.
* [ARC] Add checking for LP_COUNT reg usage, improve error reporting.Claudiu Zissulescu2016-11-294-16/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (find_opcode_match): New function argument errmsg. (assemble_tokens): Collect and report the eventual error message found during opcode matching process. * testsuite/gas/arc/lpcount-err.s: New file. * testsuite/gas/arc/add_s-err.s: Update error message. opcode/ 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (insert_ra_chk): New function. (insert_rb_chk): Likewise. (insert_rad): Update text error message. (insert_rcd): Likewise. (insert_rhv2): Likewise. (insert_r0): Likewise. (insert_r1): Likewise. (insert_r2): Likewise. (insert_r3): Likewise. (insert_sp): Likewise. (insert_gp): Likewise. (insert_pcl): Likewise. (insert_blink): Likewise. (insert_ilink1): Likewise. (insert_ilink2): Likewise. (insert_ras): Likewise. (insert_rbs): Likewise. (insert_rcs): Likewise. (insert_simm3s): Likewise. (insert_rrange): Likewise. (insert_fpel): Likewise. (insert_blinkel): Likewise. (insert_pcel): Likewise. (insert_nps_3bit_dst): Likewise. (insert_nps_3bit_dst_short): Likewise. (insert_nps_3bit_src2_short): Likewise. (insert_nps_bitop_size_2b): Likewise. (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise. (RA_CHK): Define. (RB): Adjust. (RB_CHK): Define. (RC): Adjust. * arc-dis.c (print_insn_arc): Add LOAD and STORE class. * arc-tbl.h (div, divu): All instructions are DIVREM class. Change first insn argument to check for LP_COUNT usage. (rem): Likewise. (ld, ldd): All instructions are LOAD class. Change first insn argument to check for LP_COUNT usage. (st, std): All instructions are STORE class. (mac, mpy, dmac, mul, dmpy): All instructions are MPY class. Change first insn argument to check for LP_COUNT usage. (mov): All instructions are MOVE class. Change first insn argument to check for LP_COUNT usage. include/ 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE instruction classes.
* X86: Ignore REX_B bit for 32-bit XOP instructionsAmit Pawar2016-11-284-0/+37
| | | | | | | | | | | | | | | | | | While decoding 32-bit XOP instructions, 64 bit registers names are printed. This patch fixes this by ignoring REX_B bit in 32-bit mode. opcodes/ PR binutils/20637 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP instructions. gas/ PR binutils/20637 * testsuite/gas/i386/xop32reg.d: New file. * testsuite/gas/i386/xop32reg.s: New file. * testsuite/gas/i386/i386.exp: Run new test.
* Fix spelling in comments in .y files (binutils)Ambrogino Modigliani2016-11-271-0/+4
| | | | * arparse.y: Fix spelling in comments.
* Fix spelling in comments in .l files (gas)Ambrogino Modigliani2016-11-272-1/+5
| | | | * config/bfin-lex.l: Fix spelling in comments.
* Fix spelling in comments in Expect scripts (gas)Ambrogino Modigliani2016-11-278-11/+21
| | | | | | | | | | * testsuite/gas/all/gas.exp: Fix spelling in comments. * testsuite/gas/cris/cris.exp: Fix spelling in comments. * testsuite/gas/hppa/basic/basic.exp: Fix spelling in comments. * testsuite/gas/hppa/parse/parse.exp: Fix spelling in comments. * testsuite/gas/hppa/reloc/reloc.exp: Fix spelling in comments. * testsuite/gas/sh/arch/arch.exp: Fix spelling in comments. * testsuite/gas/tic4x/tic4x.exp: Fix spelling in comments.
* Fix spelling in comments in Assembler files (gas)Ambrogino Modigliani2016-11-2713-13/+28
| | | | | | | | | | | | | | | * testsuite/gas/arm/local_function.d: Fix spelling in comments. * testsuite/gas/arm/req.s: Fix spelling in comments. * testsuite/gas/arm/vfp1.s: Fix spelling in comments. * testsuite/gas/arm/vfp1_t2.s: Fix spelling in comments. * testsuite/gas/arm/vfp1xD.s: Fix spelling in comments. * testsuite/gas/arm/vfp1xD_t2.s: Fix spelling in comments. * testsuite/gas/mcore/allinsn.s: Fix spelling in comments. * testsuite/gas/mips/24k-triple-stores-5.s: Fix spelling in comments. * testsuite/gas/mips/delay.d: Fix spelling in comments. * testsuite/gas/mips/nodelay.d: Fix spelling in comments. * testsuite/gas/mips/r5900-full.s: Fix spelling in comments. * testsuite/gas/mips/r5900.s: Fix spelling in comments.
* Fix spelling in comments in C source files (gas)Ambrogino Modigliani2016-11-2745-87/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * as.h: Fix spelling in comments. * config/obj-ecoff.c: Fix spelling in comments. * config/obj-macho.c: Fix spelling in comments. * config/tc-aarch64.c: Fix spelling in comments. * config/tc-arc.c: Fix spelling in comments. * config/tc-arm.c: Fix spelling in comments. * config/tc-avr.c: Fix spelling in comments. * config/tc-cr16.c: Fix spelling in comments. * config/tc-epiphany.c: Fix spelling in comments. * config/tc-frv.c: Fix spelling in comments. * config/tc-hppa.c: Fix spelling in comments. * config/tc-hppa.h: Fix spelling in comments. * config/tc-i370.c: Fix spelling in comments. * config/tc-m68hc11.c: Fix spelling in comments. * config/tc-m68k.c: Fix spelling in comments. * config/tc-mcore.c: Fix spelling in comments. * config/tc-mep.c: Fix spelling in comments. * config/tc-metag.c: Fix spelling in comments. * config/tc-mips.c: Fix spelling in comments. * config/tc-mn10200.c: Fix spelling in comments. * config/tc-mn10300.c: Fix spelling in comments. * config/tc-nds32.c: Fix spelling in comments. * config/tc-nios2.c: Fix spelling in comments. * config/tc-ns32k.c: Fix spelling in comments. * config/tc-pdp11.c: Fix spelling in comments. * config/tc-ppc.c: Fix spelling in comments. * config/tc-riscv.c: Fix spelling in comments. * config/tc-rx.c: Fix spelling in comments. * config/tc-score.c: Fix spelling in comments. * config/tc-score7.c: Fix spelling in comments. * config/tc-sparc.c: Fix spelling in comments. * config/tc-tic54x.c: Fix spelling in comments. * config/tc-vax.c: Fix spelling in comments. * config/tc-xgate.h: Fix spelling in comments. * config/tc-xtensa.c: Fix spelling in comments. * config/tc-z80.c: Fix spelling in comments. * dwarf2dbg.c: Fix spelling in comments. * input-file.h: Fix spelling in comments. * itbl-ops.c: Fix spelling in comments. * read.c: Fix spelling in comments. * stabs.c: Fix spelling in comments. * symbols.c: Fix spelling in comments. * write.c: Fix spelling in comments. * testsuite/gas/all/itbl-test.c: Fix spelling in comments. * testsuite/gas/tic4x/opclasses.h: Fix spelling in comments.
* gas: fix CBCOND diagnostics for invalid immediate operands.Jose E. Marchesi2016-11-255-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes two problems in the SPARC assembler: - The diagnostic message Error: Illegal operands: Immediate value in cbcond is out of range. is incorrectly issued for non-CBCOND instructions that feature a simm5 immediate field, such as MPMUL, MONTMUL, etc. - When an invalid immediate operand is used in a CBCOND instruction, two redundant error messages are issued to the user, the second due to a stale fixup (this happens since commit 85024cd8bcb93f4112470ecdbd6c10fc2aea724f). Some diagnostic tests for the CBCOND instructions are also included in the patch. Tested in both sparc64-linux-gnu and sparcv9-linux-gnu targets. gas/ChangeLog: 2016-11-25 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (sparc_ip): Avoid emitting a cbcond error messages for non-cbcond instructions. * testsuite/gas/sparc/cbcond-diag.s: New file. * testsuite/gas/sparc/cbcond-diag.l: Likewise. * testsuite/gas/sparc/sparc.exp (gas_64_check): Run cbcond-diag tests.
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