| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | x86/Intel: don't accept malformed EXTRQ / INSERTQ | Jan Beulich | 2022-11-09 | 4 | -16/+17 |
| * | RISC-V: xtheadfmemidx: Use fp register in mnemonics | Christoph Müllner | 2022-11-09 | 4 | -48/+50 |
| * | Support Intel RAO-INT | Kong Lingling | 2022-11-08 | 10 | -1/+115 |
| * | configure: require libzstd >= 1.4.0 | Christophe Lyon | 2022-11-07 | 1 | -10/+10 |
| * | RISC-V: Remove RV32EF conflict | Tsukasa OI | 2022-11-07 | 2 | -5/+0 |
| * | x86: adjust recently introduced testcases | Jan Beulich | 2022-11-04 | 8 | -0/+8 |
| * | Support Intel AVX-NE-CONVERT | konglin1 | 2022-11-04 | 10 | -0/+1023 |
| * | Support multiple .eh_frame sections | Jojo R | 2022-11-04 | 3 | -3/+35 |
| * | gas/doc/internals.texi: fix typo | Jojo R | 2022-11-04 | 1 | -2/+1 |
| * | x86: simplify expressions in update_imm() | Jan Beulich | 2022-11-02 | 1 | -23/+14 |
| * | RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment. | Nelson Chu | 2022-11-02 | 4 | -38/+67 |
| * | Support Intel MSRLIST | Hu, Lin1 | 2022-11-02 | 9 | -1/+47 |
| * | Support Intel WRMSRNS | Hu, Lin1 | 2022-11-02 | 9 | -1/+44 |
| * | Add handler for more i386_cpu_flags | Kong Lingling | 2022-11-02 | 1 | -0/+17 |
| * | Support Intel CMPccXADD | Haochen Jiang | 2022-11-02 | 9 | -1/+818 |
| * | Support Intel AVX-VNNI-INT8 | Cui,Lili | 2022-11-02 | 10 | -1/+547 |
| * | Support Intel AVX-IFMA | Hongyu Wang | 2022-11-02 | 15 | -15/+252 |
| * | opcodes/arm: use '@' consistently for the comment character | Andrew Burgess | 2022-11-01 | 121 | -2291/+2291 |
| * | x86: minor improvements to optimize_imm() (part III) | Jan Beulich | 2022-10-31 | 1 | -9/+8 |
| * | x86: Silence GCC 12 warning on tc-i386.c | H.J. Lu | 2022-10-31 | 2 | -5/+5 |
| * | Support Intel PREFETCHI | Cui, Lili | 2022-10-31 | 13 | -3/+103 |
| * | RX assembler: switch arguments of thw MVTACGU insn. | Yoshinori Sato | 2022-10-31 | 2 | -4/+8 |
| * | RISC-V: Always generate mapping symbols at the start of the sections. | Nelson Chu | 2022-10-29 | 3 | -41/+0 |
| * | gas: NEWS: Note support for RISC-V Zawrs | Palmer Dabbelt | 2022-10-28 | 1 | -0/+2 |
| * | gas: NEWS: Add a missing newline | Palmer Dabbelt | 2022-10-28 | 1 | -0/+1 |
| * | RISC-V: Improve "bits undefined" diagnostics | Tsukasa OI | 2022-10-28 | 1 | -2/+2 |
| * | RISC-V: Fallback for instructions longer than 64b | Tsukasa OI | 2022-10-28 | 1 | -5/+8 |
| * | RISC-V/gas: fix build with certain gcc versions | Jan Beulich | 2022-10-28 | 1 | -7/+7 |
| * | RISC-V: Fix build failure for -Werror=maybe-uninitialized | Tsukasa OI | 2022-10-28 | 1 | -1/+1 |
| * | RISC-V: Output mapping symbols with ISA string. | Nelson Chu | 2022-10-28 | 24 | -328/+404 |
| * | PowerPC: Add support for RFC02658 - MMA+ Outer-Product Instructions | Peter Bergner | 2022-10-27 | 4 | -2/+81 |
| * | PowerPC: Add support for RFC02653 - Dense Math Facility | Peter Bergner | 2022-10-27 | 6 | -65/+270 |
| * | re: Support Intel AMX-FP16 | Alan Modra | 2022-10-27 | 2 | -0/+2 |
| * | x86: consolidate VPCLMUL tests | Jan Beulich | 2022-10-24 | 15 | -268/+156 |
| * | x86: consolidate VAES tests | Jan Beulich | 2022-10-24 | 15 | -352/+211 |
| * | x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns | Jan Beulich | 2022-10-24 | 31 | -361/+361 |
| * | Support Intel AMX-FP16 | Cui,Lili | 2022-10-21 | 9 | -1/+97 |
| * | x86: Check VEX/EVEX encoding before checking vector operands | H.J. Lu | 2022-10-20 | 5 | -4/+8 |
| * | x86: re-work AVX-VNNI support | Jan Beulich | 2022-10-20 | 7 | -12/+36 |
| * | aarch64-pe support for LD, GAS and BFD | Jedidiah Thompson | 2022-10-19 | 8 | -25/+108 |
| * | x86: generalize gas documentation for disabling of ISA extensions | Jan Beulich | 2022-10-18 | 1 | -49/+5 |
| * | Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp} | CaiJingtao | 2022-10-17 | 5 | -205/+566 |
| * | PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many | Alan Modra | 2022-10-16 | 5 | -56/+55 |
| * | PowerPC SPE disassembly and tests | Alan Modra | 2022-10-14 | 4 | -14/+11 |
| * | e200 LSP support | Alan Modra | 2022-10-14 | 5 | -12/+38 |
| * | RISC-V: Imply 'Zicsr' from privileged extensions with CSRs | Tsukasa OI | 2022-10-14 | 1 | -0/+6 |
| * | RISC-V: Test DWARF register number for "fp" | Tsukasa OI | 2022-10-14 | 2 | -0/+4 |
| * | x86: drop "regmask" static variable | Jan Beulich | 2022-10-12 | 1 | -3/+2 |
| * | Re: Error: attempt to get value of unresolved symbol `L0' | Nick Clifton | 2022-10-11 | 4 | -10/+26 |
| * | add --enable-default-compressed-debug-sections-algorithm configure option | Martin Liska | 2022-10-11 | 5 | -3/+40 |
