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* Support Intel AMX-FP16Cui,Lili2022-10-219-1/+97
* x86: Check VEX/EVEX encoding before checking vector operandsH.J. Lu2022-10-205-4/+8
* x86: re-work AVX-VNNI supportJan Beulich2022-10-207-12/+36
* aarch64-pe support for LD, GAS and BFDJedidiah Thompson2022-10-198-25/+108
* x86: generalize gas documentation for disabling of ISA extensionsJan Beulich2022-10-181-49/+5
* Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp}CaiJingtao2022-10-175-205/+566
* PowerPC se_rfmci and VLE, SPE2 and LSP insns with -manyAlan Modra2022-10-165-56/+55
* PowerPC SPE disassembly and testsAlan Modra2022-10-144-14/+11
* e200 LSP supportAlan Modra2022-10-145-12/+38
* RISC-V: Imply 'Zicsr' from privileged extensions with CSRsTsukasa OI2022-10-141-0/+6
* RISC-V: Test DWARF register number for "fp"Tsukasa OI2022-10-142-0/+4
* x86: drop "regmask" static variableJan Beulich2022-10-121-3/+2
* Re: Error: attempt to get value of unresolved symbol `L0'Nick Clifton2022-10-114-10/+26
* add --enable-default-compressed-debug-sections-algorithm configure optionMartin Liska2022-10-115-3/+40
* refactor usage of compressed_debug_section_typeMartin Liska2022-10-111-25/+9
* Error: attempt to get value of unresolved symbol `L0'Nick Clifton2022-10-112-2/+12
* x86/gas: support quoted address scale factor in AT&T syntaxJan Beulich2022-10-054-12/+35
* Arm64: support CLEARBHB aliasJan Beulich2022-10-052-1/+3
* gas: NEWS: Mention the T-Head extensions that were recently addedPalmer Dabbelt2022-10-041-0/+5
* Re: compress .gnu.debuglto_.debug_* sections if requestedAlan Modra2022-10-041-13/+7
* compress .gnu.debuglto_.debug_* sections if requestedMartin Liska2022-10-041-1/+3
* RISC-V/gas: allow generating up to 176-bit instructions with .insnJan Beulich2022-10-047-10/+82
* RISC-V/gas: don't open-code insn_length()Jan Beulich2022-10-041-1/+1
* RISC-V/gas: drop stray call to install_insn()Jan Beulich2022-10-041-1/+0
* RISC-V/gas: drop riscv_subsets static variableJan Beulich2022-10-041-18/+14
* RISC-V: don't cast expressions' X_add_number to long in diagnosticsJan Beulich2022-10-041-4/+4
* RISC-V: Assign DWARF numbers to vector registersTsukasa OI2022-10-033-2/+73
* RISC-V: Add testcase for DWARF register numbersTsukasa OI2022-10-032-0/+296
* RISC-V: Relax "fmv.[sdq]" requirementsTsukasa OI2022-09-306-0/+6
* RISC-V: Reorganize and enhance 'Zfinx' testsTsukasa OI2022-09-306-106/+207
* RISC-V: Eliminate long-casts of X_add_number in diagnosticsChristoph Müllner2022-09-301-8/+8
* RISC-V: fallout from "re-arrange opcode table for consistent alias handling"Jan Beulich2022-09-304-14/+14
* RISC-V: fix build after "Add support for arbitrary immediate encoding formats"Jan Beulich2022-09-301-4/+4
* RISC-V: drop stray INSN_ALIAS flagsJan Beulich2022-09-302-0/+35
* RISC-V: re-arrange opcode table for consistent alias handlingJan Beulich2022-09-3021-159/+375
* x86: improve match_template()'s diagnosticsJan Beulich2022-09-307-67/+86
* x86/Intel: restrict suffix derivationJan Beulich2022-09-306-61/+230
* LoongArch: Update ELF e_flags handling according to specification.liuzhensong2022-09-301-10/+10
* The help document of as misses some many optionsNick Clifton2022-09-284-34/+90
* binutils, gdb: support zstd compressed debug sectionsFangrui Song2022-09-2612-47/+380
* RISC-V: Add Zawrs ISA extension supportChristoph Müllner2022-09-233-0/+25
* RISC-V: Add T-Head MemPair vendor extensionChristoph Müllner2022-09-226-0/+88
* RISC-V: Add support for literal instruction argumentsChristoph Müllner2022-09-221-0/+10
* RISC-V: Add T-Head MemIdx vendor extensionChristoph Müllner2022-09-226-0/+137
* RISC-V: Add T-Head FMemIdx vendor extensionChristoph Müllner2022-09-226-0/+85
* RISC-V: Add T-Head MAC vendor extensionChristoph Müllner2022-09-223-0/+27
* RISC-V: Add T-Head CondMov vendor extensionChristoph Müllner2022-09-223-0/+19
* RISC-V: Add T-Head Bitmanip vendor extensionChristoph Müllner2022-09-2216-0/+141
* RISC-V: Add support for arbitrary immediate encoding formatsChristoph Müllner2022-09-221-0/+74
* RISC-V: Add T-Head SYNC vendor extensionChristoph Müllner2022-09-226-0/+40
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