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* Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina2017-11-165-2/+15
* Correct AArch64 crypto dependencies.Tamar Christina2017-11-161-0/+7
* Update documentation for Arvm8.4-A changes to AArch64.Tamar Christina2017-11-162-3/+16
* Add assembler and disassembler support for the new Armv8.4-a instructions for...Tamar Christina2017-11-1613-0/+12823
* x86: ignore high register select bit(s) in 32- and 16-bit modesJan Beulich2017-11-163-4/+82
* ix86/Intel: don't require memory operand size specifier for PTWRITEJan Beulich2017-11-165-1/+13
* i386: Replace .code64/.code32 with .byteH.J. Lu2017-11-162-13/+13
* Separate the new FP16 instructions backported from Armv8.4-a to Armv8.2-a int...Tamar Christina2017-11-157-5/+24
* Add support to readelf and objdump for following links to separate debug info...Nick Clifton2017-11-1513-12/+29
* x86: use correct register namesJan Beulich2017-11-153-0/+27
* x86: drop VEXI4_Fixup()Jan Beulich2017-11-154-0/+28
* x86-64: don't allow use of %axl as accumulatorJan Beulich2017-11-159-0/+85
* First part of fix for riscv gas lns-common-1 failure.Jim Wilson2017-11-142-0/+5
* x86: add disassembler support for XOP VPCOM* pseudo-opsJan Beulich2017-11-144-1194/+1199
* x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich2017-11-147-0/+224
* x86: string insns don't allow displacementsJan Beulich2017-11-146-33/+52
* gas/arm64: don't emit stack pointer symbol table entriesJan Beulich2017-11-132-5/+11
* gas/ia64: fix testsuite failuresJan Beulich2017-11-134-11/+18
* x86: don't default variable shift count insns to 8-bit operand sizeJan Beulich2017-11-134-1/+20
* x86/Intel: don't mistake riz/eiz as base registerJan Beulich2017-11-134-1/+20
* x86-64/Intel: issue diagnostic for out of range displacementJan Beulich2017-11-135-29/+56
* Fix riscv dwarf2-10 gas testsuite failure.Jim Wilson2017-11-092-1/+5
* Enable the Dot Product extension by default for Armv8.4-a.Tamar Christina2017-11-093-0/+17
* Add assembler and disassembler support for the new Armv8.4-a registers for AA...Tamar Christina2017-11-096-0/+555
* Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina2017-11-092-0/+17
* Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options...Tamar Christina2017-11-092-0/+11
* Fix typo in changelogNick Clifton2017-11-081-1/+1
* Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio...Nick Clifton2017-11-082-1/+13
* Adds command line support for Armv8.4-A, via the new command line option -mar...Jiong Wang2017-11-0812-3/+1552
* xtensa message pluralizationAlan Modra2017-11-082-4/+18
* RISC-V: Fix riscv g++ testsuite EH failures.Jim Wilson2017-11-075-0/+47
* RISC-V: Add satp as an alias for sptbrPalmer Dabbelt2017-11-075-0/+23
* This patch similarly to the AArch64 one enables Dot Product support by defaul...Tamar Christina2017-11-072-68/+87
* bundle_lock message tidyAlan Modra2017-11-073-13/+20
* readelf ngettext fixesAlan Modra2017-11-0732-132/+167
* gas and ld pluralization fixesAlan Modra2017-11-0715-42/+127
* ngettext supportAlan Modra2017-11-072-2/+13
* Add option for Qualcomm Saphira partSiddhesh Poyarekar2017-11-033-0/+10
* [ARM] Help wince objdump on coproc testsThomas Preud'homme2017-11-023-2/+8
* FT32B is a new FT32 family member. It has a code compression scheme, which re...James Bowman2017-11-0121-375/+2909
* [ARM] Fix Coprocessor instructions availabilityThomas Preud'homme2017-11-0126-35/+328
* x86: Check invalid XMM register in AVX512 gathersH.J. Lu2017-10-2614-1/+41
* testsuite/gas/all/fill-1.s: Use L2 rather than .L2.Hans-Peter Nilsson2017-10-262-2/+6
* PR22348, conflicting global vars in crx and cr16Alan Modra2017-10-252-10/+18
* Yet another fill-1 test fixAlan Modra2017-10-253-11/+17
* RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0Andrew Waterman2017-10-248-0/+26
* RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2Andrew Waterman2017-10-245-0/+15
* Fix my previous gas/ChangeLog entryPalmer Dabbelt2017-10-241-2/+2
* i386: Support .code64 directive only with 64-bit bfdH.J. Lu2017-10-247-4/+54
* RISC-V: Don't emit 2-byte NOPs if the C extension is disabledPalmer Dabbelt2017-10-232-1/+6
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