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* Fix typo in changelogNick Clifton2017-11-081-1/+1
* Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio...Nick Clifton2017-11-082-1/+13
* Adds command line support for Armv8.4-A, via the new command line option -mar...Jiong Wang2017-11-0812-3/+1552
* xtensa message pluralizationAlan Modra2017-11-082-4/+18
* RISC-V: Fix riscv g++ testsuite EH failures.Jim Wilson2017-11-075-0/+47
* RISC-V: Add satp as an alias for sptbrPalmer Dabbelt2017-11-075-0/+23
* This patch similarly to the AArch64 one enables Dot Product support by defaul...Tamar Christina2017-11-072-68/+87
* bundle_lock message tidyAlan Modra2017-11-073-13/+20
* readelf ngettext fixesAlan Modra2017-11-0732-132/+167
* gas and ld pluralization fixesAlan Modra2017-11-0715-42/+127
* ngettext supportAlan Modra2017-11-072-2/+13
* Add option for Qualcomm Saphira partSiddhesh Poyarekar2017-11-033-0/+10
* [ARM] Help wince objdump on coproc testsThomas Preud'homme2017-11-023-2/+8
* FT32B is a new FT32 family member. It has a code compression scheme, which re...James Bowman2017-11-0121-375/+2909
* [ARM] Fix Coprocessor instructions availabilityThomas Preud'homme2017-11-0126-35/+328
* x86: Check invalid XMM register in AVX512 gathersH.J. Lu2017-10-2614-1/+41
* testsuite/gas/all/fill-1.s: Use L2 rather than .L2.Hans-Peter Nilsson2017-10-262-2/+6
* PR22348, conflicting global vars in crx and cr16Alan Modra2017-10-252-10/+18
* Yet another fill-1 test fixAlan Modra2017-10-253-11/+17
* RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0Andrew Waterman2017-10-248-0/+26
* RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2Andrew Waterman2017-10-245-0/+15
* Fix my previous gas/ChangeLog entryPalmer Dabbelt2017-10-241-2/+2
* i386: Support .code64 directive only with 64-bit bfdH.J. Lu2017-10-247-4/+54
* RISC-V: Don't emit 2-byte NOPs if the C extension is disabledPalmer Dabbelt2017-10-232-1/+6
* Add missing ChangeLog entriesIgor Tsimbalist2017-10-231-0/+162
* MIPS: Preset EF_MIPS_ABI2 with n32 ELF objectsMaciej W. Rozycki2017-10-232-3/+6
* Enable Intel AVX512_BITALG instructions.Igor Tsimbalist2017-10-2315-0/+1046
* Enable Intel AVX512_VNNI instructions.Igor Tsimbalist2017-10-2315-1/+977
* Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist2017-10-2333-1/+738
* Enable Intel VAES instructions.Igor Tsimbalist2017-10-2333-0/+1349
* Enable Intel GFNI instructions.Igor Tsimbalist2017-10-2332-1/+1865
* Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist2017-10-2315-2/+3409
* Fix spurious left-over quotes from last edit.Hans-Peter Nilsson2017-10-222-3/+8
* Improve handling of REPT pseudo op with a negative count.Nick Clifton2017-10-208-9/+46
* RISC-V: Relax RISCV_PCREL_* to RISCV_GPREL_*Palmer Dabbelt2017-10-192-1/+10
* Fix the AVR assembler so that it will correctly issue warnings about skipped ...Nick Clifton2017-10-196-4/+49
* Fix fill-1 testcaseAndreas Krebbel2017-10-194-6/+23
* RISC-V: Mark unsupported gas testcasesPalmer Dabbelt2017-10-189-1/+38
* Update Cris assembler tests for checks that now pass where they used to fail.Nick Clifton2017-10-183-6/+9
* Update the Swedish translation in the GAS subdirectory.Nick Clifton2017-10-182-4238/+6054
* Fix segfault processing nios2 pseudo-instructions with too few arguments.Sandra Loosemore2017-10-165-30/+145
* FT32: support for FT32B processor - part 1James Bowman2017-10-122-3/+20
* Disable the inclusion of logical input files in the assembler listing output ...Nick Clifton2017-10-114-13/+38
* S/390: Sync with latest POP - 3 new instructionsAndreas Krebbel2017-10-094-1/+14
* Add missing changelog entriesAndreas Krebbel2017-10-091-0/+11
* Replace nop in fill-1.s testcase.Andreas Krebbel2017-10-091-1/+1
* Enable .fill forward labelsAndreas Krebbel2017-10-093-1/+8
* Fix the MSP430 assembler so that it detects and reports extraneous text at th...Nick Clifton2017-10-056-27/+114
* Add an assembler test for PR gas/21167H.J. Lu2017-10-044-0/+22
* PR21167, relocation sections not included in groupsAlan Modra2017-10-058-31/+62
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