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* Add option for Qualcomm Saphira partSiddhesh Poyarekar2017-11-033-0/+10
* [ARM] Help wince objdump on coproc testsThomas Preud'homme2017-11-023-2/+8
* FT32B is a new FT32 family member. It has a code compression scheme, which re...James Bowman2017-11-0121-375/+2909
* [ARM] Fix Coprocessor instructions availabilityThomas Preud'homme2017-11-0126-35/+328
* x86: Check invalid XMM register in AVX512 gathersH.J. Lu2017-10-2614-1/+41
* testsuite/gas/all/fill-1.s: Use L2 rather than .L2.Hans-Peter Nilsson2017-10-262-2/+6
* PR22348, conflicting global vars in crx and cr16Alan Modra2017-10-252-10/+18
* Yet another fill-1 test fixAlan Modra2017-10-253-11/+17
* RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0Andrew Waterman2017-10-248-0/+26
* RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2Andrew Waterman2017-10-245-0/+15
* Fix my previous gas/ChangeLog entryPalmer Dabbelt2017-10-241-2/+2
* i386: Support .code64 directive only with 64-bit bfdH.J. Lu2017-10-247-4/+54
* RISC-V: Don't emit 2-byte NOPs if the C extension is disabledPalmer Dabbelt2017-10-232-1/+6
* Add missing ChangeLog entriesIgor Tsimbalist2017-10-231-0/+162
* MIPS: Preset EF_MIPS_ABI2 with n32 ELF objectsMaciej W. Rozycki2017-10-232-3/+6
* Enable Intel AVX512_BITALG instructions.Igor Tsimbalist2017-10-2315-0/+1046
* Enable Intel AVX512_VNNI instructions.Igor Tsimbalist2017-10-2315-1/+977
* Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist2017-10-2333-1/+738
* Enable Intel VAES instructions.Igor Tsimbalist2017-10-2333-0/+1349
* Enable Intel GFNI instructions.Igor Tsimbalist2017-10-2332-1/+1865
* Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist2017-10-2315-2/+3409
* Fix spurious left-over quotes from last edit.Hans-Peter Nilsson2017-10-222-3/+8
* Improve handling of REPT pseudo op with a negative count.Nick Clifton2017-10-208-9/+46
* RISC-V: Relax RISCV_PCREL_* to RISCV_GPREL_*Palmer Dabbelt2017-10-192-1/+10
* Fix the AVR assembler so that it will correctly issue warnings about skipped ...Nick Clifton2017-10-196-4/+49
* Fix fill-1 testcaseAndreas Krebbel2017-10-194-6/+23
* RISC-V: Mark unsupported gas testcasesPalmer Dabbelt2017-10-189-1/+38
* Update Cris assembler tests for checks that now pass where they used to fail.Nick Clifton2017-10-183-6/+9
* Update the Swedish translation in the GAS subdirectory.Nick Clifton2017-10-182-4238/+6054
* Fix segfault processing nios2 pseudo-instructions with too few arguments.Sandra Loosemore2017-10-165-30/+145
* FT32: support for FT32B processor - part 1James Bowman2017-10-122-3/+20
* Disable the inclusion of logical input files in the assembler listing output ...Nick Clifton2017-10-114-13/+38
* S/390: Sync with latest POP - 3 new instructionsAndreas Krebbel2017-10-094-1/+14
* Add missing changelog entriesAndreas Krebbel2017-10-091-0/+11
* Replace nop in fill-1.s testcase.Andreas Krebbel2017-10-091-1/+1
* Enable .fill forward labelsAndreas Krebbel2017-10-093-1/+8
* Fix the MSP430 assembler so that it detects and reports extraneous text at th...Nick Clifton2017-10-056-27/+114
* Add an assembler test for PR gas/21167H.J. Lu2017-10-044-0/+22
* PR21167, relocation sections not included in groupsAlan Modra2017-10-058-31/+62
* Add new mnemonics for VLE multiple load instructionsAlexander Fedotov2017-10-014-0/+71
* Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions,...Nick Clifton2017-09-274-0/+25
* readelf: Handle E_MIPS_MACH_5900Maciej W. Rozycki2017-09-223-0/+28
* PR gas/21762: MIPS: Fix .stabs directive marking labels as MIPS16James Cowgill2017-09-227-0/+49
* Reduce excessive .eh_frame alignment for powerpcAlan Modra2017-09-212-0/+5
* PR22127, as segfaults assembling invalid .relocAlan Modra2017-09-142-1/+7
* x86: Remove restriction on NOTRACK prefix positionH.J. Lu2017-09-0912-228/+266
* RISC-V: Avoid emitting invalid instructions in mixed RVC/no-RVC codePalmer Dabbelt2017-09-072-17/+13
* Missing relocation R_PPC_VLE_ADDR20 and add VLE flag to details in readelfAlexander Fedotov-B556132017-09-054-2/+33
* Enable support for the AArch64 dot-prod instruction in the Cortex A55 and A75...Tamar Christina2017-09-012-2/+7
* MIPS/BFD: Correct microMIPS cross-mode BAL to JALX relaxationMaciej W. Rozycki2017-08-306-0/+114
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