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* Set version to 2.34, turn off development, add changelog entriesbinutils-2_34Nick Clifton2020-02-013-184/+188
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* arm: PR gas/25472 Enable DSP instructions with +mveAndre Vieira2020-01-313-6/+159
| | | | | | | | | | | | | | | | | | | We noticed +mve was not enabling DSP instructions as it should, reported in PR 25472. The MVE architecture extension for Armv8.1-M Mainline implies DSP extensions. This patch reflects that in the '+mve' command line option. gas/ChangeLog: 2020-01-31 Andre Vieira <andre.simoesdiasvieira@arm.com> Backport from mainline. 2020-01-31 Andre Vieira <andre.simoesdiasvieira@arm.com> PR gas/25472 * config/tc-arm.c (armv8m_main_ext_table): Refactored +dsp adding. (armv8_1m_main_ext_table): Refactored +dsp adding and enabled dsp for +mve. * testsuite/gas/arm/mve_dsp.d: New test.
* Fix compile time build problem building the s390 assembler.Nick Clifton2020-01-312-1/+6
| | | | | * config/tc-s390.c (s390_elf_suffix): Return ELF_SUFFIX_NONE rather than BFD_RELOC_NONE.
* [ARM]: Add support for vldmia/vldmdb/vstmia/vstmdb instructions in MVE.Srinath Parvathaneni2020-01-314-4/+75
| | | | | | | | | | | | | | | | | | | | | This patch adds support for assembly instructions vldmia, vldmdb, vstmia and vstmdb in MVE. This instructions are already supported for Armv8-M Floating-point Extension. gas/ChangeLog: 2020-01-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/tc-arm.c (fldmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VLDMIA instruction for MVE. (fldmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VLDMDB instruction for MVE. (fstmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMIA instruction for MVE. (fstmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMDB instruction for MVE. * testsuite/gas/arm/mve-ldst.d: New test. * testsuite/gas/arm/mve-ldst.s: Likewise.
* Updated translations for some of the binutils sub-directoriesNick Clifton2020-01-313-6008/+7790
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* AArch64: Fix cfinv disassembly issuesTamar Christina2020-01-273-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the preferred disassembly for cfinv. The Armv8.4-a instruction overlaps with the possible encoding space for msr. This because msr allows you to use unallocated encoding space using the general sA_B_cC_cD_E form. However when an encoding does become allocated then we need to ensure that it's used as the preferred disassembly. The problem with cfinv is that its mask has all bits sets because it has no arguments. This causes issues for the Alias resolver in gas as it uses the mask to build alias graph. In this case it can't do it since it thinks almost everything would alias with cfinv. So instead we can only fix this by moving cfinv before msr. gas/ChangeLog: PR 25403 * testsuite/gas/aarch64/armv8_4-a.d: Add cfinv. * testsuite/gas/aarch64/armv8_4-a.s: Likewise. opcodes/ChangeLog: PR 25403 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv. * aarch64-asm-2.c: Regenerate * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. (cherry picked from commit 7568c93bf95a518797dfb2987b04911164c14a36)
* x86: VCVTNEPS2BF16{X,Y} should permit broadcastingJan Beulich2020-01-215-0/+25
| | | | | | | | | | | | | | | Just like other VCVT*{X,Y} templates do, and to allow the programmer flexibility (might be relevant in particular when heavily macro-izing code), the two templates should also have Broadcast set, just like their X/Y-suffix-less counterparts. This in turn requires them to also have * Dword set on their memory operands, to cover the logic added to i386gen by 4a1b91eabbe7 ("x86: Expand Broadcast to 3 bits"), * RegXMM/RegYMM set on their source operands, to satisfy broadcast sizing logic in gas itself. Otherwise ATTSyntax templates wouldn't need such operand size attributes. While extending the test cases, also add Intel syntax broadcast forms without explicit size specifiers.
* Updated translations for various binutils sub-directoriesNick Clifton2020-01-202-3001/+3886
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* Set BFD_VERSION to 2.33.90. Regenerate configure and pot files.Nick Clifton2020-01-183-472/+482
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* Add markers for 2.34 branch to the NEWS files and ChangeLogs.Nick Clifton2020-01-182-0/+6
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* x86: Add {vex} pseudo prefixH.J. Lu2020-01-175-11/+22
| | | | | | | | | | | | | | | | | | | | | | | There are 2-byte VEX prefix and 3-byte VEX prefix. 2-byte VEX prefix can't encode all operands. By default, assembler tries 2-byte VEX prefix first. {vex3} can be used to force 3-byte VEX prefix. This patch adds {vex} pseudo prefix and keeps {vex2} for backward compatibility. gas/ * config/tc-i386.c (_i386_insn): Replace vex_encoding_vex2 with vex_encoding_vex. (parse_insn): Likewise. * doc/c-i386.texi: Replace {vex2} with {vex}. Update {vex} and {vex3} documentation. * testsuite/gas/i386/pseudos.s: Replace 3 {vex2} tests with {vex}. * testsuite/gas/i386/x86-64-pseudos.s: Likewise. opcodes/ * i386-opc.tbl: Add {vex} pseudo prefix. * i386-tbl.h: Regenerated.
* Forgot to add testcases to commit for [binutils][arm] PR25376 Change MVE ...Andre Vieira2020-01-174-0/+30
| | | | The original commit was 2da2eaf4ce299c84c5a1f1bc6f7944266cb36d6e
* [binutils][arm] PR25376 Change MVE into a CORE_HIGH featureAndre Vieira2020-01-162-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves MVE feature bits into the CORE_HIGH section. This makes sure .fpu and -mfpu does not reset the bits set by MVE. This is important because .fpu has no option to "set" these same bits and thus, mimic'ing GCC, we choose to define MVE as an architecture extension rather than put it together with other the legacy fpu features. This will enable the following behavior: .arch armv8.1-m.main .arch mve .fpu fpv5-sp-d16 #does not disable mve. vadd.i32 q0, q1, q2 This patch also makes sure MVE is not taken into account during auto-detect. This was already the case, but because we moved the MVE bits to the architecture feature space we must make sure ARM_ANY does not include MVE. gas/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH. (armv8_1m_main_ext_table): Use CORE_HIGH for mve. * testsuite/arm/armv8_1-m-fpu-mve-1.s: New. * testsuite/arm/armv8_1-m-fpu-mve-1.d: New. * testsuite/arm/armv8_1-m-fpu-mve-2.s: New. * testsuite/arm/armv8_1-m-fpu-mve-2.d: New. include/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to... (ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space. (ARM_ANY): Redefine to not include any MVE bits. (ARM_FEATURE_ALL): Removed. opcodes/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits. (neon_opcodes): Likewise. (select_arm_features): Make sure we enable MVE bits when selecting armv8.1-m.main. Make sure we do not enable MVE bits when not selecting any architecture.
* x86: drop found_cpu_match local variableJan Beulich2020-01-162-8/+7
| | | | | 50aecf8c5f could have done so right away; perhaps the variable shouldn't have been introduced in the first place.
* x86: VPEXTRQ/VPINSRQ are unavailable outside of 64-bit modeJan Beulich2020-01-164-0/+42
| | | | | | | | | | | | | | The AVX512DQ patterns lacking a Cpu64 attribute made the memory operand forms accepted even outside of 64-bit mode, and this even without any {evex} pseudo-prefix (otherwise one could argue that this is an attempt to follow one possible, albeit somewhat odd, interpretation of the SDM wording to this effect). For consistency between the various involved templates drop the * (now) unnecessary IgnoreSize attributes * unnecessary (due to VexW1) Size64 attributes from VEX encoded forms * redundant (with Reg64) Qword operand attributes uniformly.
* MSP430: Fix relocation overflow when using #lo(EXP) macroJozef Lawrynowicz2020-01-155-11/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ChangeLog: 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * config/tc-msp430.c (CHECK_RELOC_MSP430): Always generate 430X relocations when the target is 430X, except when extracting part of an expression. (msp430_srcoperand): Adjust comment. Initialize the expp member of the msp430_operand_s struct as appropriate. (msp430_dstoperand): Likewise. * testsuite/gas/msp430/msp430.exp: Run new test. * testsuite/gas/msp430/reloc-lo-430x.d: New test. * testsuite/gas/msp430/reloc-lo-430x.s: New test. include/ChangeLog: 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * opcode/msp430.h (enum msp430_expp_e): New. (struct msp430_operand_s): Add expp member to struct. ld/ChangeLog: 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * testsuite/ld-msp430-elf/msp430-elf.exp: Run new test. * testsuite/ld-msp430-elf/reloc-lo-430x.s: New test.
* Reinstate gas em=freebsd for sparc-freebsdAlan Modra2020-01-152-0/+5
| | | | | | | | In commit c9098af41e3 I over-simplified the sparc target decoding, missing the fact that prior to that patch sparc-*-freebsd fell through to the generic *-*-freebsd match. * configure.tgt: Add sparc-*-freebsd case.
* x86: Updated align branch tests for Darwin and i686-pc-elfLili Cui2020-01-1422-179/+246
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Update align branch assembler tests to match Darwin disassembler outputs. 2. Skip unsupported "call *foo" tests in 64-bit mode on Darwin. 3. Update align branch linker test to match any addresses for i686-pc-elf. gas/ * testsuite/gas/i386/align-branch-1a.d: Updated for Darwin. * testsuite/gas/i386/align-branch-1b.d: Likewise. * testsuite/gas/i386/align-branch-1c.d: Likewise. * testsuite/gas/i386/align-branch-1d.d: Likewise. * testsuite/gas/i386/align-branch-1e.d: Likewise. * testsuite/gas/i386/align-branch-1f.d: Likewise. * testsuite/gas/i386/align-branch-1g.d: Likewise. * testsuite/gas/i386/align-branch-1h.d: Likewise. * testsuite/gas/i386/align-branch-1i.d: Likewise. * testsuite/gas/i386/align-branch-5.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1a.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1b.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1c.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1d.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1e.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1f.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1g.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1h.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1i.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-5.d: Likewise. * testsuite/gas/i386/i386.exp: Skip x86-64-align-branch-2a, x86-64-align-branch-2b and x86-64-align-branch-2c on Darwin. ld/ * testsuite/ld-i386/align-branch-1.d: Updated for i686-pc-elf.
* Fix various assembler testsuite failures for the Z80 target.Sergey Belyashov2020-01-1411-126/+244
| | | | | | | | | | | | | | | | | | PR 25377 gas * config/tc-z80.c: Add support for half precision, single precision and double precision floating point values. * config/tc-z80.h b/gas/config/tc-z80.h: Disable string escapes. * doc/as.texi: Add new z80 command line options. * doc/c-z80.texi: Document new z80 command line options. * testsuite/gas/z80/ez80_pref_dis.s: New test. * testsuite/gas/z80/ez80_pref_dis.d: New test driver. * testsuite/gas/z80/z80.exp: Run the new test. * testsuite/gas/z80/fp_math48.d: Use correct command line option. * testsuite/gas/z80/fp_zeda32.d: Likewise. * testsuite/gas/z80/strings.d: Update expected output. opcodes * z80-dis.c (suffix): Use .db instruction to generate double prefix.
* [gas][aarch64] Turn on SVE when using f32mm or f64mm extensionsMatthew Malcomson2020-01-132-2/+7
| | | | | | | | | | | | | | | | There are no instructions under these matrix multiply extensions that can be used without having SVE enabled. Since these extensions require SVE, we make that explicit in the options table. Tested on aarch64-none-elf without regressions. gas/ChangeLog: 2020-01-13 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (f64mm, f32mm): Add sve as a feature dependency.
* [ARC][committed] Code cleanup and improvements.Claudiu Zissulescu2020-01-134-4/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Code clean up and improvements when changing the cpu from command line. Also, remove unused/old emulations. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (arc_select_cpu): Re-init the bfd if we change the CPU. * config/tc-arc.h: Add header if/defs. * testsuite/gas/arc/pseudos.d: Improve matching pattern. ls/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * Makefile.am: Remove earcelf_prof.c and earclinux_prof.c emulations. * Makefile.in: Regenerate. * configure.tgt: Likewise. * emulparams/arcelf_prof.sh: Remove file. * emulparams/arclinux_prof.sh: Likewise. opcodes/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (C_NE): Make it required.
* ubsan: wasm32: signed integer overflowAlan Modra2020-01-132-2/+6
| | | | | | | | | | | | | | | | | | | The signed integer overflow occurred when adding one to target_count for (i = 0; i < target_count + 1; i++) but that's the least of the worries here. target_count was long and i int, leading to the possibility of a loop that never ended. So to avoid this type of vulnerability, this patch uses what I believe to be the proper types for arguments of various wasm32 opcodes, rather than using "long" which may change in size. gas/ * testsuite/gas/wasm32/allinsn.d: Update expected output. opcodes/ * wasm32-dis.c (print_insn_wasm32): Localise variables. Store result of wasm_read_leb128 in a uint64_t and check that bits are not lost when copying to other locals. Use uint32_t for most locals. Use PRId64 when printing int64_t.
* tic4x: sign extension using shiftsAlan Modra2020-01-132-1/+6
| | | | | | | | | | | | | | | | | Don't do that. Especially don't use shift counts that assume the type being shifted is 32 bits when the type is long/unsigned long. Also reverts part of a change I made on 2019-12-11 to tic4x_print_register that on closer inspection turns out to be unnecessary. include/ * opcode/tic4x.h (EXTR): Delete. (EXTRU, EXTRS, INSERTU, INSERTS): Rewrite without zero/sign extension using shifts. Do trim INSERTU value to specified bitfield. opcodes/ * tic4x-dis.c (tic4x_print_register): Remove dead code. gas/ * config/tc-tic4x.c (tic4x_operands_match): Correct tic3x trap insertion.
* HPUX gas testsuite fixesAlan Modra2020-01-103-2/+8
| | | | | * testsuite/gas/elf/pr14891.s: Don't start directives in first column. * testsuite/gas/elf/pr21661.d: Don't run on hpux.
* Fix compile time warnings about comparisons always being false.Sergey Belyashov2020-01-092-89/+101
| | | | | | | | | | | | PR 25224 gas * config/tc-z80.c (emit_ld_m_rr): Use integer types when checking opcode byte values. (emit_ld_r_r): Likewise. (emit_ld_rr_m): Likewise. (emit_ld_rr_nn): Likewise. opcodes * z80-dis.c (ld_ii_ii): Use character constant when checking opcode byte value.
* x86: refine when to trigger optimizationsJan Beulich2020-01-092-10/+15
| | | | | | | | | | Checking just the base opcode without also checking this isn't a VEX encoding, and without there being other insn properties avoiding a match once respective VEX/XOP/EXEX-encoded insns would appear, is at least dangerous. Add respective checks. At the same time there's no real need to check the extension opcode to be None for the 0xA8 form - there's nothing it can be confused with, and non-VEX-and-alike forms also can't appear.
* x86-64: assert sane internal state for REX conversionsJan Beulich2020-01-092-1/+8
| | | | | For the comments about "hi" registers to be really applicable, RegRex may not be set on the respective registers. Assert this is the case.
* x86: consistently convert to byte registers for TEST w/ imm optimizationJan Beulich2020-01-092-11/+15
| | | | | | Commit ac0ab1842d ("i386: Also check R12-R15 registers when optimizing testq to testb") didn't go quite far enough: In order to avoid confusing other code registers would better be converted to byte ones uniformly.
* x86: SYSENTER/SYSEXIT are unavailable in 64-bit mode on AMDJan Beulich2020-01-097-0/+60
| | | | | | The disassembler change is such that in default mode we'd disassemble the insns (for there not ebing any conflicts), but when AMD64 mode was explicitly requested, we'd show them as "(bad)".
* Document the fact that the assembler's alignment pseudo-ops can be issued ↵Nick Clifton2020-01-082-9/+20
| | | | | | | | | | without any argumemtns. PR 25284 * doc/as.texi (Align): Document the fact that all arguments can be omitted. (Balign): Likewise. (P2align): Likewise.
* Make the assembler generate an error if there is an attempt to define a ↵Nick Clifton2020-01-086-0/+34
| | | | | | | | | | | | section with the same name as an already defined symbol. PR 14891 * config/obj-elf.c (obj_elf_section): Fail if the section name is already defined as a different symbol type. * testsuite/gas/elf/pr14891.s: New test source file. * testsuite/gas/elf/pr14891.d: New test driver. * testsuite/gas/elf/pr14891.s: New test expected error output. * testsuite/gas/elf/elf.exp: Run the new test.
* ubsan: z8k: index 10 out of bounds for type 'unsigned int const[10]'Alan Modra2020-01-082-2/+7
| | | | | | | | | | | | | | | | | | | The fix is the additional ARRAY_SIZE test, the rest just tidies variable types rather than adding a cast to avoid warnings. opcodes/ * z8k-dis.c: Include libiberty.h (instr_data_s): Make max_fetched unsigned. (z8k_lookup_instr): Make nibl_index and tabl_index unsigned. Don't exceed byte_info bounds. (output_instr): Make num_bytes unsigned. (unpack_instr): Likewise for nibl_count and loop. * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and idx unsigned. * z8k-opc.h: Regenerate. gas/ * config/tc-z8k.c (md_begin): Make idx unsigned. (get_specific): Likewise for this_index.
* [ARC] Improve parsing instruction operands.Claudiu Zissulescu2020-01-072-91/+117
| | | | | | | | | | | | | | | | | | We use gas' expression function to parse the operands of an instruction in a generic way. There are situations when we have labels and registers having the same name as well as the substraction sign doesn't always stands for the arithmetical operation but for the register range (e.g. enter instruction). This patch improves parsing symbols found in a instruction operand, cleans up code and avoids using default or undefined variables. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (parse_reloc_symbol): New function. (tokenize_arguments): Clean up, use parse_reloc_symbol function. (md_operand): Set X_md to absent. (arc_parse_name): Check for X_md.
* Allow individual targets to decide if string escapes should be allowed. ↵Sergey Belyashov2020-01-037-9/+22
| | | | | | | | | | | | Disable for PPC and Z80. PR 25311 * as.h (TC_STRING_ESCAPES): Provide a default definition. * app.c (do_scrub_chars): Use TC_STRING_ESCAPES instead of NO_STRING_ESCAPES. * read.c (next_char_of_string): Likewise. * config/tc-ppc.h (TC_STRING_ESCAPES): Define. * config/tc-z80.h (TC_STRING_ESCAPES): Define.
* Updated Swedish translation for the GAS subdirectory.Nick Clifton2020-01-032-408/+185
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* Arm64: correct address index operands for LD1RO{H,W,D}Jan Beulich2020-01-033-24/+29
| | | | | Just like their LD1RQ{H,W,D} counterparts, as per the specification the index registers get scaled by element size.
* Arm64: correct {su,us}dot SIMD encodingsJan Beulich2020-01-033-12/+34
| | | | | | | | According to the specification these permit the Q bit to control the vector length operated on, and hence this bit should not already be set in the opcode table entries (it rather needs setting dynamically). Note how the test case output did also not match its input. Besides correcting the test case also extend it to cover both forms.
* Arm64: correct uzp{1,2} mnemonicsJan Beulich2020-01-033-8/+13
| | | | | According to the specification, and in line with the pre-existing predicate forms, the mnemonics do not include an 'i'.
* Arm64: correct 64-bit element fmmla encodingJan Beulich2020-01-033-3/+8
| | | | | There's just one bit of difference to the 32-bit element form, as per the documentation.
* Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. ↵Sergey Belyashov2020-01-0269-3430/+15547
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an ELF based target for these as well. PR 25224 bfd * Makefile.am: Add z80-elf target support. * configure.ac: Likewise. * targets.c: Likewise. * config.bfd: Add z80-elf target support and new arches: ez80 and z180. * elf32-z80.c: New file. * archures.c: Add new z80 architectures: eZ80 and Z180. * coffcode.h: Likewise. * cpu-z80.c: Likewise. * bfd-in2.h: Likewise plus additional Z80 relocations. * coff-z80.c: Add new relocations for Z80 target and local label check. gas * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support for assembler code generated by SDCC. Add new relocation types. Add z80-elf target support. * config/tc-z80.h: Add z80-elf target support. Enable dollar local labels. Local labels starts from ".L". * testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict. * testsuite/gas/all/fwdexp.s: Likewise. * testsuite/gas/z80/suffix.d: Fix failure on ELF target. * testsuite/gas/z80/z80.exp: Add new tests * testsuite/gas/z80/dollar.d: New file. * testsuite/gas/z80/dollar.s: New file. * testsuite/gas/z80/ez80_adl_all.d: New file. * testsuite/gas/z80/ez80_adl_all.s: New file. * testsuite/gas/z80/ez80_adl_suf.d: New file. * testsuite/gas/z80/ez80_isuf.s: New file. * testsuite/gas/z80/ez80_z80_all.d: New file. * testsuite/gas/z80/ez80_z80_all.s: New file. * testsuite/gas/z80/ez80_z80_suf.d: New file. * testsuite/gas/z80/r800_extra.d: New file. * testsuite/gas/z80/r800_extra.s: New file. * testsuite/gas/z80/r800_ii8.d: New file. * testsuite/gas/z80/r800_z80_doc.d: New file. * testsuite/gas/z80/z180.d: New file. * testsuite/gas/z80/z180.s: New file. * testsuite/gas/z80/z180_z80_doc.d: New file. * testsuite/gas/z80/z80_doc.d: New file. * testsuite/gas/z80/z80_doc.s: New file. * testsuite/gas/z80/z80_ii8.d: New file. * testsuite/gas/z80/z80_ii8.s: New file. * testsuite/gas/z80/z80_in_f_c.d: New file. * testsuite/gas/z80/z80_in_f_c.s: New file. * testsuite/gas/z80/z80_op_ii_ld.d: New file. * testsuite/gas/z80/z80_op_ii_ld.s: New file. * testsuite/gas/z80/z80_out_c_0.d: New file. * testsuite/gas/z80/z80_out_c_0.s: New file. * testsuite/gas/z80/z80_reloc.d: New file. * testsuite/gas/z80/z80_reloc.s: New file. * testsuite/gas/z80/z80_sli.d: New file. * testsuite/gas/z80/z80_sli.s: New file. ld * Makefile.am: Add new target z80-elf * configure.tgt: Likewise. * emultempl/z80.em: Add support for eZ80 and Z180 architectures. * emulparams/elf32z80.sh: New file. * emultempl/z80elf.em: Likewise. * testsuite/ld-z80/arch_ez80_adl.d: Likewise. * testsuite/ld-z80/arch_ez80_z80.d: Likewise. * testsuite/ld-z80/arch_r800.d: Likewise. * testsuite/ld-z80/arch_z180.d: Likewise. * testsuite/ld-z80/arch_z80.d: Likewise. * testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z180.d: Likewise. * testsuite/ld-z80/labels.s: Likewise. * testsuite/ld-z80/relocs.s: Likewise. * testsuite/ld-z80/relocs_b_ez80.d: Likewise. * testsuite/ld-z80/relocs_b_z80.d: Likewise. * testsuite/ld-z80/relocs_f_z80.d: Likewise. * testsuite/ld-z80/z80.exp: Likewise. opcodes * z80-dis.c: Add support for eZ80 and Z80 instructions.
* [ARM][gas] fix build breakage with gcc-10 by using correct enum typeSzabolcs Nagy2020-01-022-1/+6
| | | | | | | | | | | | | | Fixes ../../gas/config/tc-arm.c: In function 'parse_reg_list': ../../gas/config/tc-arm.c:1946:35: error: implicit conversion from 'enum reg_list_els' to 'enum arm_reg_type' [-Werror=enum-conversion] 1946 | reg = arm_reg_parse (&str, REGLIST_RN); | ^~~~~~~~~~ gas/ChangeLog: * config/tc-arm.c (parse_reg_list): Use REG_TYPE_RN instead of REGLIST_RN.
* Re: Update year range in copyright notice of binutils filesAlan Modra2020-01-011-0/+4
| | | | Add the ChangeLog entry.
* Update year range in copyright notice of binutils filesAlan Modra2020-01-01567-570/+570
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* ChangeLog rotationAlan Modra2020-01-012-4872/+4886
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* x86: adjust ignored prefix warning for branchesJan Beulich2019-12-275-14/+27
| | | | | | There's no reason to not also issue them in Intel syntax mode, and it can be quite helpful to mention the actual insn (after all there can be multiple on a single line).
* x86-64: correct / adjust prefix emissionJan Beulich2019-12-2710-63/+72
| | | | | | | | | First and foremost REX must come last. Next JumpInterSegment branches can't possibly have a REX prefix, as they're consistently CpuNo64. And finally make BND prefix handling in output_branch() consistent with that of other prefixes in the same function, and make its placement among prefixes consistent with output_jump() (which, oddly enough, still isn't the supposedly canonical order specified by the *_PREFIX definitions).
* x86-64: fix Intel64 handling of branch with data16 prefixJan Beulich2019-12-276-24/+71
| | | | | | | | | | | | | | | | | | | | The expectation of x86-64-branch-3 for "call" / "jmp" with an obvious direct destination to translate to an indirect _far_ branch is plain wrong. The operand size prefix should have no effect at all on the interpretation of the operand. The main underlying issue here is that the Intel64 templates of the direct branches don't include Disp16, yet various assumptions exist that it would always be there when there's also Disp32/Disp32S, toggled by the operand size prefix (which is being ignored by direct branches in Intel64 mode). Along these lines it was also wrong to base the displacement width decision solely on the operand size prefix: REX.W cancels this effect and hence needs taking into consideration, too. A disassembler change is needed here as well: XBEGIN was wrongly treated the same as direct CALL/JMP, which isn't the case - the operand size prefix does affect displacement size there, it's merely ignored when it comes to updating [ER]IP.
* x86: consolidate Disp<NN> handling a littleJan Beulich2019-12-274-46/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In memory operand addressing, which forms of displacement are permitted besides Disp8 is pretty clearly limited - outside of 64-bit mode, Disp16 or Disp32 only, depending on address size (MPX being special in not allowing Disp16), - in 64-bit mode, Disp32s or Disp64 without address size override, and solely Disp32 with one. Adjust assembler and i386-gen to match this, observing that templates already get adjusted before trying to match them against input depending on the presence of an address size prefix. This adjustment logic gets extended to all cases, as certain DispNN values should also be dropped when there's no such prefix. In fact behavior of the assembler, perhaps besides the exact diagnostics wording, should not differ between there being templates applicable to 64-bit and non-64-bit at the same time, or there being fully separate sets of templates, with their DispNN settings already reduced accordingly. This adjustment logic further gets guarded such that there wouldn't be and Disp<N> conversion based on address size prefix when this prefix doesn't control the width of the displacement (on branches other than absolute ones). These adjustments then also allow folding two MOV templates, which had been split between 64-bit and non-64-bits variants so far. Once in this area also - drop the bogus DispNN from JumpByte templates, leaving just the correct Disp8 there (compensated by i386_finalize_displacement() now setting Disp8 on their operands), - add the missing Disp32S to XBEGIN. Note that the changes make it necessary to temporarily mark a test as XFAIL; this will get taken care of by a subsequent patch. The failing parts are entirely bogus and will get replaced.
* Remove tic80 supportAlan Modra2019-12-172-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is one way of fixing ubsan bug reports, just delete the code. The assembler support was removed back in 2005 along with other non-BFD assemblers, but somehow the remainder of the port stayed in. bfd/ * coff-tic80.c: Delete file. * cpu-tic80.c: Delete file. * archures.c: Remove tic80 support. * coffcode.h: Likewise. * coffswap.h: Likewise. * targets.c: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * Makefile.am: Likewise. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. binutils/ * testsuite/binutils-all/objcopy.exp: Remove tic80 support. * testsuite/binutils-all/objdump.exp: Likewise. gas/ * doc/as.texi: Remove mention of tic80. include/ * coff/tic80.h: Delete file. * opcode/tic80.h: Delete file. ld/ * emulparams/tic80coff.sh: Delete file. * scripttempl/tic80coff.sc: Delete file. * configure.tgt: Remove tic80 support. * Makefile.am: Likewise. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate. opcodes/ * tic80-dis.c: Delete file. * tic80-opc.c: Delete file. * disassemble.c: Remove tic80 support. * disassemble.h: Likewise. * Makefile.am: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
* i386: Also check R12-R15 registers when optimizing testq to testbH.J. Lu2019-12-125-3/+25
| | | | | | | | | | | | | | | | Similar to SP, BP, SI and DI registers, R12-R15 registers must use REX prefix for the low byte register when optimizing test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 PR gas/25274 * config/tc-i386.c (optimize_encoding): Also check R12-R15 registers for "test $imm7, %r64/%r32/%r16 -> test $imm7, %r8" optimization. * testsuite/gas/i386/x86-64-optimize-3.s: Add tests for test with r12. * testsuite/gas/i386/x86-64-optimize-3.d: Updated. * testsuite/gas/i386/x86-64-optimize-3b.d: Likewise.
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