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* bfd/Tristan Gingold2011-12-154-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | 2011-12-15 Iain Sandoe <iains@gcc.gnu.org> * mach-o-target.c (bfd_mach_o_bfd_set_private_flags): Use bfd_mach_o_bfd_set_private_flags. * mach-o.c (bfd_mach_o_bfd_set_private_flags): New. * mach-o.h (bfd_mach_o_bfd_set_private_flags): Declare. gas/ 2011-12-15 Iain Sandoe <iains@gcc.gnu.org> * config/obj-macho.c (obj_mach_o_subsections_by_symbols): New global. (obj_mach_o_file_properties): New enum. (obj_mach_o_subsections_via_symbols): Generalize name to... ... (obj_mach_o_fileprop) and use to set subsections_via_symbols. gas/testsuite/ 2011-12-15 Iain Sandoe <iains@gcc.gnu.org> * gas/mach-o/subsect-via-symbols-0.d: New. * gas/mach-o/subsect-via-symbols-1.d: New. * gas/mach-o/subsect-via-symbols.s: New.
* * frv.opc (parse_uhi16): Fix handling of %hi operator on 64-bitNick Clifton2011-12-154-0/+30
| | | | | | | | | | | | | hosts. * cgen-asm.c (cgen_parse_signed_integer): Add code to handle the sign extension of negative values on a 64-bit host. * frv-asm.c: Regenerate. * gas/frv/immediates.s: New test file - checks assembly of constant values. * gas/frv/immediates.d: Expected disassmbly. * gas/frv/allinsn.exp: Run the new test.
* gas/Jie Zhang2011-12-159-46/+57
| | | | | | | | | | | | | | | | | | | 2011-12-14 Stuart Henderson <shenders@gcc.gnu.org> * config/bfin-parse.y (asm_1): set SRCx fields to all 1s for dspalu32 instrs that don't use them. gas/testsuite/ 2011-12-14 Stuart Henderson <shenders@gcc.gnu.org> * gas/bfin/move.d: Update SRCx field expectations. * gas/bfin/move2.d: Likewise. * gas/bfin/parallel.d: Likewise. * gas/bfin/parallel2.d: Likewise. * gas/bfin/parallel3.d: Likewise. * gas/bfin/parallel4.d: Likewise. * gas/bfin/video.d: Likewise. * gas/bfin/video2.d: Likewise.
* 2011-12-14 Iain Sandoe <iains@gcc.gnu.org>Tristan Gingold2011-12-147-2/+510
| | | | | | | | | | * gas/mach-o/comm-1.d: New. * gas/mach-o/comm-1.s: New. * gas/mach-o/lcomm-1.s: New. * gas/mach-o/mach-o.exp: Update to use run_dump_tests[]. * gas/mach-o/sections-1.d: New. * gas/mach-o/sections-1.s: New. * gas/mach-o/warn-1.s: Add .comm alignment range warning.
* 2011-12-14 Iain Sandoe <iains@gcc.gnu.org>Tristan Gingold2011-12-146-0/+57
| | | | | | | | * gas/mach-o: New. * gas/mach-o/mach-o.exp: New. * gas/mach-o/warn-1.s: New. * gas/mach-o/lcomm-1.s: New. * gas/mach-o/lcomm-1.d: New.
* opcodes:Andrew Pinski2011-12-086-0/+15
| | | | | | | | | | | | | | 2011-12-08 Andrew Pinski <apinski@cavium.com> * mips-opc.c (mips_builtin_opcodes): Add "pause". gas/testsuite: 2011-12-08 Andrew Pinski <apinski@cavium.com> * gas/mips/mips32-mt.d: Add pause instruction encoding to the end. * gas/mips/micromips@mips32r2.d: Likewise. * gas/mips/mips32r2.d: Likewise. * gas/mips/mips32-mt.s: Add pause instruction to the end. * gas/mips/mips32r2.s: Likewise.
* bfd:Andrew Pinski2011-12-084-0/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2011-12-08 Andrew Pinski <apinski@cavium.com> Adam Nemet <anemet@caviumnetworks.com> * archures.c (bfd_mach_mips_octeon2): New macro * bfd-in2.h: Regenerate. * cpu-mips.c (I_mipsocteon2): New enum value. (arch_info_struct): Add bfd_mach_mips_octeon2. * elfxx-mips.c (_bfd_elf_mips_mach): Support E_MIPS_MACH_OCTEON2. (mips_set_isa_flags): Add bfd_mach_mips_octeon2. (mips_mach_extensions): Add bfd_mach_mips_octeon2. gas: 2011-12-08 Andrew Pinski <apinski@cavium.com> Adam Nemet <anemet@caviumnetworks.com> * tc-mips.c (CPU_IS_OCTEON): Add Octeon2. (mips_cpu_info_table): Add Octeon2. * doc/c-mips.texi: Document octeon2 as an acceptable value for -march=. gas/testsuite: 2011-12-08 Andrew Pinski <apinski@cavium.com> Adam Nemet <anemet@caviumnetworks.com> * gas/mips/mips.exp: Add Octeon2 for an architecture. Run octeon2 test. * gas/mips/octeon2.d: New file. * gas/mips/octeon2.s: New file. include/opcode: 2011-12-08 Andrew Pinski <apinski@cavium.com> Adam Nemet <anemet@caviumnetworks.com> * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2. (INSN_OCTEON2): New macro. (CPU_OCTEON2): New macro. (OPCODE_IS_MEMBER): Add Octeon2. opcodes: 2011-12-08 Andrew Pinski <apinski@cavium.com> Adam Nemet <anemet@caviumnetworks.com> * mips-dis.c (mips_arch_choices): Add Octeon2. For "octeon+", just include OcteonP for the insn. * mips-opc.c (IOCT): Include Octeon2. (IOCTP): Include Octeon2. (IOCT2): New macro. (mips_builtin_opcodes): Add "laa", "laad", "lac", "lacd", "lad", "ladd", "lai", "laid", "las", "lasd", "law", "lawd". Move "lbux", "ldx", "lhx", "lwx", and "lwux" up to where the standard loads are, and add IOCT2 to them. Add "lbx" and "lhux". Add "qmac.00", "qmac.01", "qmac.02", "qmac.03", "qmacs.00", "qmacs.01", "qmacs.01", "qmacs.02" and "qmacs.03". Add "zcb" and "zcbt".
* 2011-12-07 Sameera Deshpande <sameera.deshpande@arm.com>Matthew Gretton-Dann2011-12-076-204/+249
| | | | | | | | | | * gas/config/tc-arm.c (do_t_ldstd): Warn for unpredictable cases. * gas/testsuite/gas/arm/thumb2_ldstd_unpredictable.d: New testcase. * gas/testsuite/gas/arm/thumb2_ldstd_unpredictable.l: Likewise. * gas/testsuite/gas/arm/thumb2_ldstd_unpredictable.s: Likewise. * gas/testsuite/gas/testsuite/gas/arm/sp-pc-validations-bad-t.l: Update testcase. * gas/testsuite/gas/testsuite/gas/arm/sp-pc-validations-bad-t.s: Likewise.
* * gas/config/tc-arm.c (ARM_IT_MAX_OPERANDS): New define.Matthew Gretton-Dann2011-12-073-2/+10
| | | | | | | (arm_it): Use ARM_IT_MAX_OPERANDS. (neon_select_shape): Ensure we have matched all operands. * gas/testsuite/gas/arm/neon-suffix-bad.l: Add testcase. * gas/testsuite/gas/arm/neon-suffix-bad.s: Likewise.
* * tc-arm.c (aeabi_set_public_attributes): Correctly setRichard Earnshaw2011-12-055-0/+35
| | | | | | | | | Tag_ARM_ISA_use and Tag_Thumb_ISA_use. * gas/arm/attr-any-armv4t.d: New test. * gas/arm/attr-any-armv4t.s: New file. * gas/arm/attr-any-thumbv6.d: New test. * gas/arm/attr-any-thumbv6.s: New file.
* * gas/config/tc-arm.c (arm_cpu_option_table): Add name_len field.Matthew Gretton-Dann2011-12-053-0/+13
| | | | | | | | | | | | | | | | | (arm_arch_option_table): Likewise. (arm_option_extension_value_table): Likewise. (ARM_CPU_OPT): New define. (ARM_ARCH_OPT): Likewise. (ARM_EXT_OPT): Likewise. (arm_cpus): Use ARM_CPU_OPT to initialize. (arm_archs): Use ARM_ARCH_OPT to initialize. (arm_extensions): Use ARM_EXT_OPT to initialize. (arm_parse_extension): Ensure option string matching matches the whole string. (arm_parse_cpu): Likewise. (arm_parse_arch): Likewise. * gas/testsuite/gas/arm/cmdline-bad-arch.d: New test case. * gas/testsuite/gas/arm/cmdline-bad-cpu.d: Likewise.
* gas/testsuite/Richard Sandiford2011-12-032-25/+56
| | | | | | | | | * gas/mips/mips.exp (run_dump_test_arch): Add an opts parameter. (run_dump_test_arches): Allow additional options to be passed. (run_list_test_arch): Add opts to the name. (run_list_test_arches): Allow the options to be elided. (mips4-fp, mips5-fp): Run twice, one with -32 and once with -mabi=o64. (mips64r2-ill, octeon-ill): Remove empty options string.
* opcode/Andrew Pinski2011-11-296-3/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2011-11-29 Andrew Pinski <apinski@cavium.com> * mips-dis.c (mips_arch_choices): Add Octeon+. * mips-opc.c (IOCT): Include Octeon+. (IOCTP): New macro. (mips_builtin_opcodes): Add "saa" and "saad". bfd/ 2011-11-29 Andrew Pinski <apinski@cavium.com> * archures.c (bfd_mach_mips_octeonp): New macro. * bfd-in2.h: Regenerate. * bfd/cpu-mips.c (I_mipsocteonp): New enum value. (arch_info_struct): Add bfd_mach_mips_octeonp. * elfxx-mips.c (mips_set_isa_flags): Add bfd_mach_mips_octeonp. (mips_mach_extensions): Add bfd_mach_mips_octeonp. include/opcodes/ 2011-11-29 Andrew Pinski <apinski@cavium.com> * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP. (INSN_OCTEONP): New macro. (CPU_OCTEONP): New macro. (OPCODE_IS_MEMBER): Add Octeon+. (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values. gas/ 2011-11-29 Andrew Pinski <apinski@cavium.com> * config/tc-mips.c (CPU_IS_OCTEON): New macro function. (CPU_HAS_SEQ): Change to use CPU_IS_OCTEON. (NO_ISA_COP): Likewise. (macro) <ld_st>: Add support when off0 is true. Add support for M_SAA_AB, M_SAA_OB, M_SAAD_OB and M_SAAD_AB. (mips_cpu_info_table): Add octeon+. * doc/c-mips.texi: Document octeon+ as an acceptable value for -march=. gas/testsuite/ 2011-11-29 Andrew Pinski <apinski@cavium.com> * gas/mips/mips.exp: Add octeon+ for an architecture. Run octeon-saa-saad test. (run_dump_test_arch): For Octeon architectures, also try octeon@. * gas/mips/octeon-pref.d: Remove -march=octeon from command line. * gas/mips/octeon.d: Likewise. * gas/mips/octeon-saa-saad.d: New file. * gas/mips/octeon-saa-saad.s: New file
* * gas/config/tc-arm.c (do_t_mov_cmp): Allow MOV lowreg, lowreg when no CPUMatthew Gretton-Dann2011-11-255-0/+31
| | | | | | | | is specified. * gas/testsuite/gas/arm/mov-highregs-any.d: New testcase. * gas/testsuite/gas/arm/mov-highregs-any.s: Likewise. * gas/testsuite/gas/arm/mov-lowregs-any.d: Likewise. * gas/testsuite/gas/arm/mov-lowregs-any.s: Likewise.
* * gas/mips/micromips@24k-branch-delay-1.d: New test.Maciej W. Rozycki2011-11-2125-14/+580
| | | | | | | | | | | | | | | | | | | | | | | | | | | * gas/mips/micromips@24k-triple-stores-1.d: New test. * gas/mips/micromips@24k-triple-stores-2.d: New test. * gas/mips/micromips@24k-triple-stores-3.d: New test. * gas/mips/micromips@24k-triple-stores-4.d: New test. * gas/mips/micromips@24k-triple-stores-5.d: New test. * gas/mips/micromips@24k-triple-stores-6.d: New test. * gas/mips/micromips@24k-triple-stores-7.d: New test. * gas/mips/micromips@24k-triple-stores-8.d: New test. * gas/mips/micromips@24k-triple-stores-9.d: New test. * gas/mips/micromips@24k-triple-stores-10.d: New test. * gas/mips/micromips@24k-triple-stores-11.d: New test. * gas/mips/24k-triple-stores-1.s: Adjust for microMIPS disassembly. * gas/mips/24k-triple-stores-2.s: Likewise. * gas/mips/24k-triple-stores-3.s: Likewise. * gas/mips/24k-triple-stores-4.s: Likewise. * gas/mips/24k-triple-stores-5.s: Likewise. * gas/mips/24k-triple-stores-6.s: Likewise. * gas/mips/24k-triple-stores-7.s: Likewise. * gas/mips/24k-triple-stores-8.s: Likewise. * gas/mips/24k-triple-stores-9.s: Likewise. * gas/mips/24k-triple-stores-10.s: Likewise. * gas/mips/24k-triple-stores-11.s: Likewise. * gas/mips/mips.exp: Run the new tests.
* * gas/mips/micromips@loc-swap-2.d: Correct test case.Maciej W. Rozycki2011-11-212-7/+11
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* gas/Maciej W. Rozycki2011-11-1612-92/+107
| | | | | | | | | | | | | | | | | | | | * config/tc-mips.c (macro): Fix unsupported opcode message capitalization. (mips_ip, mips16_ip): Likewise. gas/testsuite/ * gas/mips/mips-double-float-flag.l: Adjust according to unsupported opcode message capitalization fix. * gas/mips/mips-hard-float-flag.l: Likewise. * gas/mips/mips-macro-ill-nofp.l: Likewise. * gas/mips/mips-macro-ill-sfp.l: Likewise. * gas/mips/mips1-fp.l: Likewise. * gas/mips/mips16e-64.l: Likewise. * gas/mips/mips32-sf32.l: Likewise. * gas/mips/mips32r2-fp32.l: Likewise. * gas/mips/mips4-branch-likely.l: Likewise. * gas/mips/mips4-fp.l: Likewise. * gas/mips/octeon-ill.l: Likewise.
* gas/Maciej W. Rozycki2011-11-146-0/+81
| | | | | | | | | | | | * config/tc-mips.c (can_swap_branch_p): Exclude microMIPS variant frags too. gas/testsuite/ * gas/mips/relax-swap3.d: New test. * gas/mips/mips16@relax-swap3.d: Likewise. * gas/mips/micromips@relax-swap3.d: Likewise. * gas/mips/relax-swap3.s: New test source. * gas/mips/mips.exp: Run the new tests.
* * config/tc-arm.c (md_begin): Remove ARM_PLT32 reloc associatedNick Clifton2011-11-022-1/+5
| | | | | | | | with the (PLT) instruction suffix when operating in eabi mode. * doc/c-arm.texi (ARM_Relocations): Extend description of (PLT) suffix. * gas/arm/pic.d: Update expected output.
* bfd:Nick Clifton2011-10-2515-0/+3943
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Makefile.am (ALL_MACHINES): Add cpu-epiphany.lo . (ALL_MACHINES_CFILES): Add cpu-epiphany.c . (BFD32_BACKENDS): Add elf32-epiphany.lo . (BFD32_BACKENDS_CFILES): Add elf32-epiphany.c . * Makefile.in, bfd-in2.h, configure, libbfd.h: Regenerate. * archures.c (bfd_arch_epiphany): Add. (bfd_mach_epiphany16, bfd_mach_epiphany32): Define. (bfd_epiphany_arch): Declare. (bfd_archures_list): Add &bfd_epiphany_arch. * config.bfd (epiphany-*-elf): New target case. * configure.in (bfd_elf32_epiphany_vec): New target vector case. * reloc.c (BFD_RELOC_EPIPHANY_SIMM8): New relocation. (BFD_RELOC_EPIPHANY_SIMM24, BFD_RELOC_EPIPHANY_HIGH): Likewise. (BFD_RELOC_EPIPHANY_LOW, BFD_RELOC_EPIPHANY_SIMM11): Likewise. (BFD_RELOC_EPIPHANY_IMM11, BFD_RELOC_EPIPHANY_IMM8): Likewise. * targets.c (bfd_elf32_epiphany_vec): Declare. (_bfd_target_vector): Add bfd_elf32_epiphany_vec. * po/SRC-POTFILES.in, po/bfd.pot: Regenerate. * cpu-epiphany.c, elf32-epiphany.c: New files. binutils: * readelf.c (include "elf/epiphany.h") (guess_is_rela, dump_relocation): Handle EM_ADAPTEVA_EPIPHANY. (get_machine_name, is_32bit_abs_reloc, is_32bit_pcrel_reloc): Likewise. (is_16bit_abs_reloc, is_none_reloc): Likewise. * po/binutils.pot: Regenerate. cpu: * cpu/epiphany.cpu, cpu/epiphany.opc: New files. gas: * NEWS: Mention addition of Adapteva Epiphany support. * config/tc-epiphany.c, config/tc-epiphany.h: New files. * Makefile.am (TARGET_CPU_CFILES): Add config/tc-epiphany.c . (TARGET_CPU_HFILES): Add config/tc-epiphany.h . * Makefile.in, configure, doc/Makefile.in, po/POTFILES.in: Regenerate. * configure.in: Also set using_cgen for epiphany. * configure.tgt: Handle epiphany. * doc/Makefile.am (CPU_DOCS): Add c-epiphany.texi . * doc/all.texi: Set EPIPHANY. * doc/as.texinfo: Add EPIPHANY-specific text. * doc/c-epiphany.texi: New file. * po/gas.pot: Regenerate. gas/testsuite: * gas/epiphany: New directory. include: * dis-asm.h (print_insn_epiphany): Declare. * elf/epiphany.h: New file. * elf/common.h (EM_ADAPTEVA_EPIPHANY): Define. ld: * NEWS: Mention addition of Adapteva Epiphany support. * Makefile.am (ALL_EMULATION_SOURCES): Add eelf32epiphany.c . (eelf32epiphany.c): New rule. * Makefile.in: Regenerate. * configure.tgt: Handle epiphany-*-elf. * po/ld.pot: Regenerate. * testsuite/ld-srec/srec.exp: xfail epiphany. * emulparams/elf32epiphany.sh: New file. opcodes: * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h . (TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c, epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c . (CLEANFILES): Add stamp-epiphany. (EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it. (stamp-epiphany): New rule. * Makefile.in, configure, po/POTFILES.in, po/opcodes.pot: Regenerate. * configure.in: Handle bfd_epiphany_arch. * disassemble.c (ARCH_epiphany): Define. (disassembler): Handle bfd_arch_epiphany. * epiphany-asm.c, epiphany-desc.c, epiphany-desc.h: New files. * epiphany-dis.c, epiphany-ibld.c, epiphany-opc.c: Likewise. * epiphany-opc.h: Likewise.
* opcodes/Julian Brown2011-10-244-0/+30
| | | | | | | | | * m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml. gas/testsuite/ * gas/m68k/all.exp (movem-offset): Add test. * gas/m68k/movem-offset.s: New test. * gas/m68k/movem-offset.d: New.
* 2011-10-21 Jan Glauber <jang@linux.vnet.ibm.com>Andreas Krebbel2011-10-213-1/+28
| | | | | | | | | * s390-opc.txt: Add CPUMF instructions. 2011-10-21 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/zarch-z10.d: Add CPUMF instructions. * gas/s390/zarch-z10.s: Likewise.
* Jie Zhang <jie@codesourcery.com>Julian Brown2011-10-184-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Julian Brown <julian@codesourcery.com> gas/ * config/tc-arm.c (parse_shifter_operand): Fix handling of explicit rotation. (encode_arm_shifter_operand): Likewise. gas/testsuite/ * gas/arm/adrl.d: Adjust. * gas/arm/immed2.d: New test. * gas/arm/immed2.s: New test. ld/testsuite/ * ld-arm/cortex-a8-fix-b-plt.d: Adjust. * ld-arm/cortex-a8-fix-bcc-plt.d: Adjust. * ld-arm/cortex-a8-fix-bl-plt.d: Adjust. * ld-arm/cortex-a8-fix-bl-rel-plt.d: Adjust. * ld-arm/cortex-a8-fix-blx-plt.d: Adjust. * ld-arm/ifunc-1.dd: Adjust. * ld-arm/ifunc-2.dd: Adjust. * ld-arm/ifunc-3.dd: Adjust. * ld-arm/ifunc-4.dd: Adjust. * ld-arm/ifunc-5.dd: Adjust. * ld-arm/ifunc-6.dd: Adjust. * ld-arm/ifunc-7.dd: Adjust. * ld-arm/ifunc-8.dd: Adjust. * ld-arm/ifunc-9.dd: Adjust. * ld-arm/ifunc-10.dd: Adjust. * ld-arm/ifunc-14.dd: Adjust. * ld-arm/ifunc-15.dd: Adjust. * ld-arm/ifunc-16.dd: Adjust. opcodes/ * arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.
* * config/tc-arm.c (check_ldr_r15_aligned): New.Nick Clifton2011-10-1313-58/+398
| | | | | | | | | | | | | | | | | | | (do_ldst): Warn in upredictable cases. (do_t_ldst): Likewise. (insns): Update accordingly. * gas/arm/ldr-bad.s: New testcase. * gas/arm/ldr-bad.l: Likewise. * gas/arm/ldr-bad.d: Likewise. * gas/arm/ldr.s: Likewise. * gas/arm/ldr.d: Likewise. * gas/arm/ldr-t-bad.s: Likewise. * gas/arm/ldr-t-bad.l: Likewise. * gas/arm/ldr-t-bad.d: Likewise. * gas/arm/ldr-t.s: Likewise. * gas/arm/ldr-t.d: Likewise. * gas/arm/sp-pc-usage-t.s: Correct. * gas/arm/sp-pc-usage-t.d: Update accordingly.
* gas/testsuite/Jan Beulich2011-10-067-6/+15
| | | | | | | | | | | | | | | | | | | | | | | 2011-09-28 Jan Beulich <jbeulich@suse.com> * gas/ppc/476.s: Fix lswi first operand. * gas/ppc/476.d: Adjust expected output. * gas/ppc/a2.s: Fix lswi first operand. * gas/ppc/a2.d: Adjust expected output. * gas/ppc/power6.s: Fix lfdpx first operand. * gas/ppc/power6.d: Adjust expected output. opcodes/ 2011-09-28 Jan Beulich <jbeulich@suse.com> * ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX, RBX): New. (insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset. (powerpc_opcodes): Use RAX for second and RBXC for third operand of lswx. Use NBI for third operand of lswi. Use FRTp for first operand of lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively on DFP quad instructions.
* Another typo ... :(Kai Tietz2011-09-281-2/+1
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* * gas/pe/section-exclude.d: Correct testcase.Kai Tietz2011-09-282-4/+6
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* 2011-09-27 Kai Tietz <ktietz@redhat.com>Kai Tietz2011-09-274-0/+29
| | | | | | | | | | | * config/obj-coff.c (obj_coff_section): Add 'e' as specifier for marking section SEC_EXCLUDE. 2011-09-27 Kai Tietz <ktietz@redhat.com> * gas/pe/pe.exp: Add new testcase. * gas/pe/section-exclude.d: New file. * gas/pe/section-exclude.s: New file.
* opcodes/David S. Miller2011-09-273-2/+7
| | | | | | | | | | * sparc-opc.c (sparc_opcodes): Fix random instruction to write to a float instead of an integer register. gas/testsuite/ * gas/sparc/hpcvis3.s: Update to use float reg for random insn. * gas/sparc/hpcvis3.d: Likewise.
* Add sparc integer multiply-add instructions.David S. Miller2011-09-264-0/+22
| | | | | | | | | | | | | opcodes/ * sparc-opc.c (sparc_opcodes): Add integer multiply-add instructions. gas/testsuite/ * gas/sparc/ima.d: New test. * gas/sparc/ima.s: New test source. * gas/sparc/sparc.exp: Run new test.
* Add new sparc options to control instruction availability.David S. Miller2011-09-222-1/+3
| | | | | | | | | | | | | | | gas/ * config/tc-sparc.c (hwcap_allowed): New. (struct sparc_arch): New field 'hwcap_allowed' containing a bitmask of F_FOO flags which are enabled by the particular arch setting. Add new options that provide explicit access to new instructions. (md_parse_option): Only bump max_architecture if the requested one is larger, or this is the first explicit request. (get_hwcap_name): New function. (sparc_ip): Validate that hwcaps used by an instruction have actually been enabled. * doc/c-sparc.texi: Document new sparc options.
* Fix sparc testcases when building with 64-bit default.David S. Miller2011-09-215-6/+11
| | | | | | | | | gas/testsuite/ * gas/sparc/imm-plus-rreg.d: Fix address regex for 64-bit. * gas/sparc/save-args.d: Likewise. * gas/sparc/ticc-imm-reg.d: Likewise, add -32 to options. * gas/sparc/v8-movwr-imm.d: Likewise.
* Annotate sparc objects with cpu hardware capabilities used.David S. Miller2011-09-213-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | bfd/ * elfxx-sparc.c (_bfd_sparc_elf_merge_private_bfd_data): New. * elfxx-sparc.h: Declare it. * elf32-sparc.c (elf32_sparc_merge_private_bfd_data): Call it. * elf64-sparc.c (elf64_sparc_merge_private_bfd_data): Likewise. binutils/ * readelf.c (display_sparc_hwcaps): New. (display_sparc_gnu_attribute): New. (process_sparc_specific): New. (process_arch_specific): When EM_SPARC, EM_SPARC32PLUS, or EM_SPARCV9 invoke process_sparc_specific. gas/ * config/tc-sparc.c (hwcap_seen): New bitmask, defined when not TE_SOLARIS. (sparc_ip): When not TE_SOLARIS, accumulate hwcap bits from sparc_opcode->flags of instruction into hwcap_seen. (sparc_md_end): Create Tag_GNU_Sparc_HWCAPS attribute if hwcap_seen is non-zero and not TE_SOLARIS. gas/testsuite/ * gas/sparc/hpcvis3.s: Update for fixed fchksum16 mnemonic. * gas/sparc/hpcvis3.d: Likewise. include/elf/ * sparc.h (Tag_GNU_Sparc_HWCAPS): New object attribute. (ELF_SPARC_HWCAP_*): New HWCAPS bitmask values. include/opcode/ * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int. (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2, F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS, F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits. opcodes/ * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag bits. Fix "fchksm16" mnemonic.
* Add PR markersAndreas Schwab2011-09-101-0/+1
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* opcodes/David S. Miller2011-09-084-0/+22
| | | | | | | | | | * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd' This has been reported as being accepted by the Sun assmebler. gas/testsuite/ * gas/sparc/save-args.[sd]: New test. * gas/sparc/sparc.exp: Run new test.
* opcodes/David S. Miller2011-09-086-0/+130
| | | | | | | | | | | | | | | | | | | | The changes below bring 'mov' and 'ticc' instructions into line with the V8 SPARC Architecture Manual. * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'. * sparc-opc.c (sparc_opcodes): Add alias entries for 'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs'; 'mov regrs2,%wim' and 'mov regrs2,%tbr'. * sparc-opc.c (sparc_opcodes): Move/Change entries for 'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim' and 'mov imm,%tbr'. * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above mov aliases. gas/testsuite/ * gas/sparc/ticc-imm-reg.[sd]: New test. * gas/sparc/v8-movwr-imm.[sd]: New test. * gas/sparc/sparc.exp: Run new tests.
* gas/David S. Miller2011-09-084-0/+26
| | | | | | | | | | * config/tc-sparc.c (sparc_ip): Handle 'i' + r<0..31> in addition to 'i' + [goli]<0..7>. gas/testsuite/ * gas/sparc/imm-plus-rreg.[sd]: New test. * gas/sparc/sparc.exp: Run new test.
* opcodes/David S. Miller2011-09-083-2/+7
| | | | | | | | | * sparc-opc.c (pdistn): Destination is integer not float register. gas/testsuite/ * gas/sparc/hpcvis3.s: Correct pdistn test. * gas/sparc/hpcvis3.d: Likewise.
* gas/Richard Sandiford2011-09-084-0/+61
| | | | | | | | | | PR gas/13167 * dwarf2dbg.c (dwarf2_flush_pending_lines): Use symbol_temp_new_now. gas/testsuite/ PR gas/13167 * gas/ia64/pr13167.d, gas/ia64/pr13167.s: New test. * gas/ia64/ia64.exp: Run it.
* * gas/testsuite/gas/m68k/all.exp: Run "mode5" test also with -mcpu=5200.Andreas Schwab2011-09-074-0/+11
| | | | | | | * gas/testsuite/gas/m68k/mode5.s: Add moveml testcases. * gas/testsuite/gas/m68k/mode5.d: Update. * opcodes/m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
* gas/Richard Sandiford2011-09-056-0/+176
| | | | | | | | | | | | | | | | | PR gas/13024 * dwarf2dbg.c (pending_lines, pending_lines_tail): New variables. (dwarf2_gen_line_info_1): Delete. (dwarf2_push_line, dwarf2_flush_pending_lines): New functions. (dwarf2_gen_line_info, dwarf2_emit_label): Use them. (dwarf2_consume_line_info): Call dwarf2_flush_pending_lines. (dwarf2_directive_loc): Push previous .locs instead of generating them immediately. gas/testsuite/ * gas/mips/loc-swap-2.s, gas/mips/loc-swap-2.d, gas/mips/micromips@loc-swap-2.d, gas/mips/mips16@loc-swap-2.d: New test. * gas/mips/mips.exp: Run it.
* Update AVX tests.H.J. Lu2011-08-1913-48/+353
| | | | | | | | | | | | | | | | | | | 2011-08-19 Sergey A. Guriev <sergeya.a.guriev@intel.com> * gas/i386/avx-gather-intel.d: Added missing vpgather tests. * gas/i386/avx-gather.d: Likewise. * gas/i386/x86-64-avx-gather-intel.d: Likewise. * gas/i386/x86-64-avx-gather.d: Likewise. * gas/i386/avx-intel.d: Added missing vpinsrd and removed duplicated vpinsrb instructions. * gas/i386/avx.d: Likewise. * gas/i386/avx.s: Likewise. * gas/i386/ilp32/x86-64-avx-intel.d: Likewise. * gas/i386/ilp32/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx.s: Likewise.
* * gas/mips/micromips@mips5.d: Rename to...Maciej W. Rozycki2011-08-106-4/+16
| | | | | | | | | | | * gas/mips/micromips@mips5-fp.d: ... this. * gas/mips/mips5.d: Rename to... * gas/mips/mips5-fp.d: ... this. * gas/mips/mips5.l: Rename to... * gas/mips/mips5-fp.l: ... this. * gas/mips/mips5.s: Rename to... * gas/mips/mips5-fp.s: ... this. * gas/mips/mips.exp: Update accordingly.
* * gas/mips/mips.exp: Define new "fpisa3", "fpisa4" and "fpisa5"Maciej W. Rozycki2011-08-102-12/+22
| | | | | | | architecture properties adding them to "mips3", "mips4", "mips5" and "mips32r2" architectures. Use the new properties for the "24k-triple-stores-1", "24k-triple-stores-3", "mips4-fp", "mips5" and "alnv_ps-swap" tests.
* gas/Maciej W. Rozycki2011-08-095-0/+325
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * config/tc-mips.c (mips_set_options): Add ase_mcu. (mips_opts): Initialise ase_mcu to -1. (ISA_SUPPORTS_MCU_ASE): New macro. (MIPS_CPU_ASE_MCU): Likewise. (is_opcode_valid): Handle MCU. (macro_build, macro): Likewise. (validate_mips_insn, validate_micromips_insn): Likewise. (mips_ip): Likewise. (options): Add OPTION_MCU and OPTION_NO_MCU. (md_longopts): Add mmcu and mno-mcu. (md_parse_option): Handle OPTION_MCU and OPTION_NO_MCU. (mips_after_parse_args): Handle MCU. (s_mipsset): Likewise. (md_show_usage): Handle MCU options. * doc/as.texinfo: Document -mmcu and -mno-mcu options. * doc/c-mips.texi: Likewise, and document ".set mcu" and ".set nomcu" directives. gas/testsuite/ * gas/mips/micromips@mcu.d: New test. * gas/mips/mcu.d: Likewise. * gas/mips/mcu.s: New test source. * gas/mips/mips.exp: Run the new tests. include/opcode/ * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros. (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine. (INSN_ASE_MASK): Add the MCU bit. (INSN_MCU): New macro. (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values. (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros. opcodes/ * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2" and "mips64r2". (print_insn_args, print_insn_micromips): Handle MCU. * micromips-opc.c (MC): New macro. (micromips_opcodes): Add "aclr", "aset" and "iret". * mips-opc.c (MC): New macro. (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
* include/opcode/Maciej W. Rozycki2011-08-096-33/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros. (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise. (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise. (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise. (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise. (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise. (INSN2_READ_GPR_MMN): Likewise. (INSN2_READ_FPR_D): Change the bit used. (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise. (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise. (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise. (INSN2_COND_BRANCH): Likewise. (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros. (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise. (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise. (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise. (INSN2_MOD_GPR_MN): Likewise. gas/ * config/tc-mips.c (gpr_mod_mask): Remove INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG, INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN, INSN2_MOD_GPR_MP and INSN2_MOD_GPR_MQ opcode register use checks. (gpr_read_mask): Add INSN2_READ_GPR_MC, INSN2_READ_GPR_ME INSN2_READ_GPR_MG, INSN2_READ_GPR_MJ, INSN2_READ_GPR_MMN, INSN2_READ_GPR_MP and INSN2_READ_GPR_MQ opcode register use checks. (gpr_write_mask): Replace INSN2_WRITE_GPR_S opcode register use flag with INSN_WRITE_GPR_S. Add INSN2_WRITE_GPR_MB, INSN2_WRITE_GPR_MHI, INSN2_WRITE_GPR_MJ and INSN2_WRITE_GPR_MP opcode register use checks. (can_swap_branch_p): Enable microMIPS branch swapping. (append_insn): Likewise. gas/testsuite/ * gas/mips/micromips.d: Update according to changes to enable microMIPS branch swapping. * gas/mips/micromips-trap.d: Likewise. * gas/mips/micromips@jal-svr4pic.d: Likewise. * gas/mips/micromips@loc-swap.d: Likewise. * gas/mips/micromips@loc-swap-dis.d: Likewise. opcodes/ * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros. (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise. (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise. (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros. (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise. (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise. (WR_s): Update macro. (micromips_opcodes): Update register use flags of: "addiu", "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu", "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j", "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li", "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not", "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw", "swm" and "xor" instructions.
* include/opcode/David S. Miller2011-08-054-0/+178
| | | | | | | | | | | | | | | | | | | * sparc.h: Document new format codes '4', '5', and '('. (OPF_LOW4, RS3): New macros. opcodes/ * sparc-dis.c (v9a_ast_reg_names): Add "cps". (X_RS3): New macro. (print_insn_sparc): Handle '4', '5', and '(' format codes. Accept %asr numbers below 28. * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3 instructions. gas/ * config/tc-sparc.c (v9a_asr_table): Add "cps". (sparc_ip): Handle '4', '5' and '(' format codes. gas/testsuite * gas/sparc/hpcvis3.d: New test. * gas/sparc/hpcvis3.s: New test source. * gas/sparc/sparc.exp: Run new test.
* Update gas/i386/x86-64-branch.d to support win64.H.J. Lu2011-08-052-5/+10
| | | | | | | 2011-08-05 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/x86-64-branch.d: Pass -dw to objdump and support win64.
* Add a testcase for group error.H.J. Lu2011-08-045-0/+24
| | | | | | | | | | 2011-08-04 H.J. Lu <hongjiu.lu@intel.com> * gas/elf/bad-group.d: New. * gas/elf/bad-group.err: Likewise. * gas/elf/bad-group.s: Likewise. * gas/elf/elf.exp: Run bad-group.
* * config/tc-arm.c (do_t_strexbh): New.Nick Clifton2011-08-036-1/+92
| | | | | | | | | | (insns): Update accordingly. * gas/arm/strex-bad-t.d: New testcase. * gas/arm/strex-bad-t.s: Likewise. * gas/arm/strex-bad-t.l: Likewise. * gas/arm/strex-t.s: Likewise. * gas/arm/strex-t.d: Likewise.
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