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* testsuite: Support filtering targets by TCL procedure in `run_dump_test'Maciej W. Rozycki2018-04-271-16/+20
* Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist2018-04-2711-136/+0
* Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist2018-04-2611-0/+136
* x86: also optimize zeroing-masking variants of insnsJan Beulich2018-04-266-72/+72
* x86: properly force / avoid forcing EVEX encodingJan Beulich2018-04-265-0/+60
* x86: CpuXSAVE is a prereq for various other featuresJan Beulich2018-04-263-0/+49
* x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMaskJan Beulich2018-04-265-0/+89
* x86: don't recognize bnd<N> as registers without CpuMPXJan Beulich2018-04-263-0/+19
* x86: x87-related adjustmentsJan Beulich2018-04-265-0/+42
* [ARM] Add FDPIC relocations definitionsChristophe Lyon2018-04-252-0/+29
* Fix the mask for the sqrdml(a|s)h instructions.Tamar Christina2018-04-253-125/+10058
* Remove arm-aout and arm-coff supportAlan Modra2018-04-25151-152/+148
* RISC-V: Add new option -mrelax/-mno-relax.Jim Wilson2018-04-204-0/+45
* Fix tests to avoid cldemote encoding.Igor Tsimbalist2018-04-175-4/+10
* Enable Intel CLDEMOTE instruction.Igor Tsimbalist2018-04-1712-10/+96
* Remove arm-epoc-pe supportAlan Modra2018-04-164-4/+3
* Remove sparc-aout and sparc-coff supportAlan Modra2018-04-163-47/+0
* Remove m68k-aout and m68k-coff supportAlan Modra2018-04-1618-310/+2
* Remove sh5 and sh64 supportAlan Modra2018-04-16144-6069/+7
* Remove sh-symbianelf supportAlan Modra2018-04-162-2/+0
* Remove i370 supportAlan Modra2018-04-163-13/+2
* Remove h8300-coff supportAlan Modra2018-04-167-380/+0
* x86: Allow 32-bit registers for tpause and umwaitH.J. Lu2018-04-153-8/+20
* Stop the assembler from overwriting its output file.John Darrington2018-04-121-0/+2
* Enable Intel WAITPKG instructions.Igor Tsimbalist2018-04-117-0/+93
* Remove i860, i960, bout and aout-adobe targetsAlan Modra2018-04-1185-5725/+3
* i386: Clear vex instead of vex.evexH.J. Lu2018-04-042-0/+7
* [1/2][GAS][AARCH64]Add BFD_RELOC_AARCH64_TLSLE_LDST8/16/32/64_TPREL_LO12 supp...Renlin Li2018-03-2824-0/+216
* x86: drop VecESizeJan Beulich2018-03-286-0/+18
* x86: convert broadcast insn attribute to booleanJan Beulich2018-03-282-0/+278
* x86: don't show suffixes for to-scalar-int conversion insnsJan Beulich2018-03-282-16/+16
* Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton2018-03-282-0/+38
* ix86: allow HLE store of accumulator to absolute addressJan Beulich2018-03-223-0/+9
* x86: fix swapped operand handling for BNDMOVJan Beulich2018-03-225-0/+24
* x86/Intel: fix fallout from earlier template foldingJan Beulich2018-03-223-0/+231
* x86: fold a few XOP templatesJan Beulich2018-03-223-0/+135
* RISC-V: Emit better warning for unknown CSR.Jim Wilson2018-03-163-0/+6
* Missing testcase files for last commit.Jim Wilson2018-03-142-0/+90
* x86: Encode EVEX instructions with VEX128 if possibleH.J. Lu2018-03-092-24/+24
* x86: Strip whitespace in check_VecOperationsH.J. Lu2018-03-092-2/+2
* x86: Optimize with EVEX128 encoding for AVX512VLH.J. Lu2018-03-0811-48/+428
* x86-64: Also optimize "clr reg64"H.J. Lu2018-03-082-0/+4
* x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu2018-03-087-33/+21
* x86: correct operand size match checks for BMI/BMI2 insnsJan Beulich2018-03-083-0/+47
* x86: add GFNI, VAES, and VPCLMUL checking to cpu_flags_match()Jan Beulich2018-03-0817-1/+144
* x86: extend SSE check to PCLMULQDQ, AES, and GFNI insnsJan Beulich2018-03-0814-125/+63
* x86/Intel: correct disassembly of fsub*/fdiv*Jan Beulich2018-03-082-0/+711
* x86: adjust 4-XMM-register-group related warningJan Beulich2018-03-082-18/+18
* x86: bogus VMOVD with 64-bit operands should only allow for registersJan Beulich2018-03-083-6/+0
* x86: Rewrite NOP generation for fill and alignmentH.J. Lu2018-03-0761-3206/+2144
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