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* RISC-V: Allocate "various" operand typeTsukasa OI2023-03-313-25/+71
* x86: convert testcases to use .insnJan Beulich2023-03-3139-523/+346
* x86: document .insnJan Beulich2023-03-312-0/+133
* x86: handle immediate operands for .insnJan Beulich2023-03-316-4/+182
* x86: allow for multiple immediates in output_disp()Jan Beulich2023-03-311-5/+5
* x86: handle EVEX Disp8 for .insnJan Beulich2023-03-315-1/+149
* x86: process instruction operands for .insnJan Beulich2023-03-316-21/+432
* x86: parse special opcode modifiers for .insnJan Beulich2023-03-311-1/+38
* x86: parse VEX and alike specifiers for .insnJan Beulich2023-03-316-6/+252
* x86: introduce .insn directiveJan Beulich2023-03-319-10/+218
* Arm64/ELF: accept relocations against STN_UNDEFJan Beulich2023-03-311-1/+5
* Automatic date update in version.inGDB Administrator2023-03-311-1/+1
* PR gdb/30219: Clear sync_quit_force_run in quit_forceKevin Buettner2023-03-302-0/+9
* aarch64: Remove stray reglist variableRichard Sandiford2023-03-301-1/+1
* aarch64: Add the RPRFM instructionRichard Sandiford2023-03-3014-886/+1113
* aarch64: Add the SVE FCLAMP instructionRichard Sandiford2023-03-3010-760/+873
* aarch64: Add new SVE shift instructionsRichard Sandiford2023-03-309-873/+1006
* aarch64: Add new SVE saturating conversion instructionsRichard Sandiford2023-03-309-752/+881
* aarch64: Add new SVE dot-product instructionsRichard Sandiford2023-03-3016-854/+1111
* aarch64: Add the SVE BFMLSL instructionsRichard Sandiford2023-03-309-742/+936
* aarch64: Add the SME2 UZP and ZIP instructionsRichard Sandiford2023-03-309-338/+790
* aarch64: Add the SME2 UNPK instructionsRichard Sandiford2023-03-309-709/+945
* aarch64: Add the SME2 shift instructionsRichard Sandiford2023-03-3025-508/+1066
* aarch64: Add the SME2 saturating conversion instructionsRichard Sandiford2023-03-3021-468/+921
* aarch64: Add the SME2 FP<->FP conversion instructionsRichard Sandiford2023-03-309-948/+1102
* aarch64: Add the SME2 FP<->int conversion instructionsRichard Sandiford2023-03-309-749/+1190
* aarch64: Add the SME2 CLAMP instructionsRichard Sandiford2023-03-309-820/+1299
* aarch64: Add the SME2 MOPA and MOPS instructionsRichard Sandiford2023-03-309-717/+966
* aarch64: Add the SME2 vertical dot-product instructionsRichard Sandiford2023-03-3030-669/+1345
* aarch64: Add the SME2 dot-product instructionsRichard Sandiford2023-03-3030-753/+3708
* aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford2023-03-3029-851/+3921
* aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford2023-03-3017-665/+3573
* aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford2023-03-3022-529/+1884
* aarch64: Add the SME2 maximum/minimum instructionsRichard Sandiford2023-03-3013-445/+3198
* aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford2023-03-3031-488/+2177
* aarch64: Add the SME2 ZT0 instructionsRichard Sandiford2023-03-3020-409/+1443
* aarch64: Add the SME2 predicate-related instructionsRichard Sandiford2023-03-3037-845/+3961
* aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford2023-03-3040-448/+8895
* aarch64: Add the SME2 MOVA instructionsRichard Sandiford2023-03-3021-314/+2282
* aarch64: Add support for predicate-as-counter registersRichard Sandiford2023-03-3022-1600/+1983
* aarch64; Add support for vector offset rangesRichard Sandiford2023-03-3013-13/+151
* aarch64: Add support for vgx2 and vgx4Richard Sandiford2023-03-3015-9/+173
* aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayRichard Sandiford2023-03-305-11/+11
* aarch64: Add a _10 suffix to FLD_imm3Richard Sandiford2023-03-306-8/+8
* aarch64: Add +sme2Richard Sandiford2023-03-304-0/+7
* aarch64: Prefer register ranges & support wrappingRichard Sandiford2023-03-3012-983/+1039
* aarch64: Add support for strided register listsRichard Sandiford2023-03-307-62/+135
* aarch64: Sort fields alphanumericallyRichard Sandiford2023-03-302-163/+164
* aarch64: Resync field namesRichard Sandiford2023-03-301-7/+7
* aarch64: Regularise FLD_* suffixesRichard Sandiford2023-03-306-55/+55
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