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* [AArch64] Add SVE condition codesusers/ARM/sveRichard Sandiford2016-08-2313-90/+274
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SVE defines new names for existing NZCV conditions, to reflect the result of instructions like PTEST. This patch adds support for these names. The patch also adds comments to the disassembly output to show the alternative names of a condition code. For example: cinv x0, x1, cc becomes: cinv x0, x1, cc // cc = lo, ul, last and: b.cc f0 <...> becomes: b.cc f0 <...> // b.lo, b.ul, b.last Doing this for the SVE names follows the practice recommended by the SVE specification and is definitely useful when reading SVE code. If the feeling is that it's too distracting elsewhere, we could add an option to turn it off. include/ * opcode/aarch64.h (aarch64_cond): Bump array size to 4. opcodes/ * aarch64-dis.c (remove_dot_suffix): New function, split out from... (print_mnemonic_name): ...here. (print_comment): New function. (print_aarch64_insn): Call it. * aarch64-opc.c (aarch64_conds): Add SVE names. (aarch64_print_operand): Print alternative condition names in a comment. gas/ * config/tc-aarch64.c (opcode_lookup): Search for the end of a condition name, rather than assuming that it will have exactly 2 characters. (parse_operands): Likewise. * testsuite/gas/aarch64/alias.d: Add new condition-code comments to the expected output. * testsuite/gas/aarch64/beq_1.d: Likewise. * testsuite/gas/aarch64/float-fp16.d: Likewise. * testsuite/gas/aarch64/int-insns.d: Likewise. * testsuite/gas/aarch64/no-aliases.d: Likewise. * testsuite/gas/aarch64/programmer-friendly.d: Likewise. * testsuite/gas/aarch64/reloc-insn.d: Likewise. * testsuite/gas/aarch64/b_c_1.d, testsuite/gas/aarch64/b_c_1.s: New test. Change-Id: I8b7feb02a08aa97706955cf11f59c41ab87d6b96
* [AArch64][SVE 32/32] Add SVE testsRichard Sandiford2016-08-2314-0/+79417
| | | | | | | | | | | | | | | | | | This patch adds new tests for SVE. It also extends diagnostic.[sl] with checks for some inappropriate uses of MUL and MUL VL in base AArch64 instructions. gas/testsuite/ * gas/aarch64/diagnostic.s, gas/aarch64/diagnostic.l: Add tests for invalid uses of MUL VL and MUL in base AArch64 instructions. * gas/aarch64/sve-add.s, gas/aarch64/sve-add.d, gas/aarch64/sve-dup.s, gas/aarch64/sve-dup.d, gas/aarch64/sve-invalid.s, gas/aarch64/sve-invalid.d, gas/aarch64/sve-invalid.l, gas/aarch64/sve-reg-diagnostic.s, gas/aarch64/sve-reg-diagnostic.d, gas/aarch64/sve-reg-diagnostic.l, gas/aarch64/sve.s, gas/aarch64/sve.d: New tests. Change-Id: I7bdebac0c91df6dfc4eb6ac270ecf0026602dba5
* [AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford2016-08-2310-117/+9451
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the SVE instruction definitions and associated OP_* enum values. include/opcode/ * aarch64.h (AARCH64_FEATURE_SVE): New macro. (OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi) (OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P) (OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops. opcodes/ * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB) (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ) (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD) (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU) (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB) (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR) (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS) (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB) (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD) (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD) (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD) (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD) (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD) (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD) (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS) (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD) (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD) (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD) (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD) (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD) (OP_SVE_XWU, OP_SVE_XXU): New macros. (aarch64_feature_sve): New variable. (SVE): New macro. (_SVE_INSN): Likewise. (aarch64_opcode_table): Add SVE instructions. * aarch64-opc.h (extract_fields): Declare. * aarch64-opc-2.c: Regenerate. * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops. * aarch64-asm-2.c: Regenerate. * aarch64-dis.c (extract_fields): Make global. (do_misc_decoding): Handle the new SVE aarch64_ops. * aarch64-dis-2.c: Regenerate. gas/ * doc/c-aarch64.texi: Document the "sve" feature. * config/tc-aarch64.c (REG_TYPE_R_Z_BHSDQ_VZP): New register type. (get_reg_expected_msg): Handle it. (aarch64_check_reg_type): Likewise. (parse_operands): When parsing operands of an SVE instruction, disallow immediates that match REG_TYPE_R_Z_BHSDQ_VZP. (aarch64_features): Add an entry for SVE. Change-Id: I66ee75b1b812bf3dac5d8ec5748bc53443b15d30
* [AArch64][SVE 30/32] Add SVE instruction classesRichard Sandiford2016-08-235-0/+217
| | | | | | | | | | | | | | | | | | | | | | | | | | The main purpose of the SVE aarch64_insn_classes is to describe how an index into an aarch64_opnd_qualifier_seq_t is represented in the instruction encoding. Other instructions usually use flags for this information, but (a) we're running out of those and (b) the iclass would otherwise be unused for SVE. include/opcode/ * aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc, sve_movprfx) (sve_pred_zm, sve_shift_pred, sve_shift_unpred, sve_size_bhs) (sve_size_bhsd, sve_size_hsd, sve_size_sd): New aarch64_insn_classes. opcodes/ * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16) (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New aarch64_field_kinds. * aarch64-opc.c (fields): Add corresponding entries. * aarch64-asm.c (aarch64_get_variant): New function. (aarch64_encode_variant_using_iclass): Likewise. (aarch64_opcode_encode): Call it. * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function. (aarch64_opcode_decode): Call it. Change-Id: Ia562434a84b519aecd21b4cd7d3f5e2dfb9af67d
* [AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford2016-08-238-20/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | SVE uses some new fields to store W, X and scalar FP registers. This patch adds corresponding operands. include/opcode/ * aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd. (AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd) (AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core and FP register operands. * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm) (FLD_SVE_Vn): New aarch64_field_kinds. * aarch64-opc.c (fields): Add corresponding entries. (aarch64_print_operand): Handle the new SVE core and FP register operands. * aarch64-opc-2.c: Regenerate. * aarch64-asm-2.c: Likewise. * aarch64-dis-2.c: Likewise. gas/ * config/tc-aarch64.c (parse_operands): Handle the new SVE core and FP register operands. Change-Id: Icb683553ba080e25c1de2449fa6e9030e48eba36
* [AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford2016-08-2312-53/+258
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the new SVE floating-point immediate operands. One operand uses the same 8-bit encoding as base AArch64, but in a different position. The others use a single bit to select between two values. One of the single-bit operands is a choice between 0 and 1, where 0 is not a valid 8-bit encoding. I think the cleanest way of handling these single-bit immediates is therefore to use the IEEE float encoding itself as the immediate value and select between the two possible values when encoding and decoding. As described in the covering note for the patch that added F_STRICT, we get better error messages by accepting unsuffixed vector registers and leaving the qualifier matching code to report an error. This means that we carry on parsing the other operands, and so can try to parse FP immediates for invalid instructions like: fcpy z0, #2.5 In this case there is no suffix to tell us whether the immediate should be treated as single or double precision. Again, we get better error messages by picking one (arbitrary) immediate size and reporting an error for the missing suffix later. include/opcode/ * aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd. (AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO) (AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP immediate operands. * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind. * aarch64-opc.c (fields): Add corresponding entry. (operand_general_constraint_met_p): Handle the new SVE FP immediate operands. (aarch64_print_operand): Likewise. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two) (ins_sve_float_zero_one): New inserters. * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function. (aarch64_ins_sve_float_half_two): Likewise. (aarch64_ins_sve_float_zero_one): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two) (ext_sve_float_zero_one): New extractors. * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function. (aarch64_ext_sve_float_half_two): Likewise. (aarch64_ext_sve_float_zero_one): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (double_precision_operand_p): New function. (parse_operands): Use it to calculate the dp_p input to parse_aarch64_imm_float. Handle the new SVE FP immediate operands. Change-Id: I8a8578992ede586391d4a0499000ea36e36c2b85
* [AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford2016-08-2312-100/+657
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the new SVE integer immediate operands. There are three kinds: - simple signed and unsigned ranges, but with new widths and positions. - 13-bit logical immediates. These have the same form as in base AArch64, but at a different bit position. In the case of the "MOV Zn.<T>, #<limm>" alias of DUPM, the logical immediate <limm> is not allowed to be a valid DUP immediate, since DUP is preferred over DUPM for constants that both instructions can handle. - a new 9-bit arithmetic immediate, of the form "<imm8>{, LSL #8}". In some contexts the operand is signed and in others it's unsigned. As an extension, we allow shifted immediates to be written as a single integer, e.g. "#256" is equivalent to "#1, LSL #8". We also use the shiftless form as the preferred disassembly, except for the special case of "#0, LSL #8" (a redundant encoding of 0). include/opcode/ * aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd. (AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM) (AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM) (AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED) (AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED) (AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5) (AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6) (AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3) (AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8) (AARCH64_OPND_SVE_UIMM8_53): Likewise. (aarch64_sve_dupm_mov_immediate_p): Declare. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE integer immediate operands. * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5) (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9) (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds. * aarch64-opc.c (fields): Add corresponding entries. (operand_general_constraint_met_p): Handle the new SVE integer immediate operands. (aarch64_print_operand): Likewise. (aarch64_sve_dupm_mov_immediate_p): New function. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm) (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters. * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from... (aarch64_ins_limm): ...here. (aarch64_ins_inv_limm): New function. (aarch64_ins_sve_aimm): Likewise. (aarch64_ins_sve_asimm): Likewise. (aarch64_ins_sve_limm_mov): Likewise. (aarch64_ins_sve_shlimm): Likewise. (aarch64_ins_sve_shrimm): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm) (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors. * aarch64-dis.c (decode_limm): New function, split out from... (aarch64_ext_limm): ...here. (aarch64_ext_inv_limm): New function. (decode_sve_aimm): Likewise. (aarch64_ext_sve_aimm): Likewise. (aarch64_ext_sve_asimm): Likewise. (aarch64_ext_sve_limm_mov): Likewise. (aarch64_top_bit): Likewise. (aarch64_ext_sve_shlimm): Likewise. (aarch64_ext_sve_shrimm): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (parse_operands): Handle the new SVE integer immediate operands. Change-Id: Idad4f72e1ec6c9d78e8d7b22898444b0c47fdbd4
* [AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford2016-08-2311-49/+317
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for addresses of the form: [<base>, #<offset>, MUL VL] This involves adding a new AARCH64_MOD_MUL_VL modifier, which is why I split it out from the other addressing modes. For LD2, LD3 and LD4, the offset must be a multiple of the structure size, so for LD3 the possible values are 0, 3, 6, .... The patch therefore extends value_aligned_p to handle non-power-of-2 alignments. include/opcode/ * aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd. (AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL) (AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL) (AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise. (AARCH64_MOD_MUL_VL): New aarch64_modifier_kind. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL operands. * aarch64-opc.c (aarch64_operand_modifiers): Initialize the AARCH64_MOD_MUL_VL entry. (value_aligned_p): Cope with non-power-of-two alignments. (operand_general_constraint_met_p): Handle the new MUL VL addresses. (print_immediate_offset_address): Likewise. (aarch64_print_operand): Likewise. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl) (ins_sve_addr_ri_s9xvl): New inserters. * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function. (aarch64_ins_sve_addr_ri_s6xvl): Likewise. (aarch64_ins_sve_addr_ri_s9xvl): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl) (ext_sve_addr_ri_s9xvl): New extractors. * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function. (aarch64_ext_sve_addr_ri_s4xvl): Likewise. (aarch64_ext_sve_addr_ri_s6xvl): Likewise. (aarch64_ext_sve_addr_ri_s9xvl): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (SHIFTED_MUL_VL): New parse_shift_mode. (parse_shift): Handle it. (parse_address_main): Handle the new MUL VL addresses. (parse_operands): Likewise. Change-Id: I2c76f713f90d7ae0c5365a516685b34d23356c60
* [AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford2016-08-2312-74/+972
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds most of the new SVE addressing modes and associated operands. A follow-on patch adds MUL VL, since handling it separately makes the changes easier to read. The patch also introduces a new "operand-dependent data" field to the operand flags, based closely on the existing one for opcode flags. For SVE this new field needs only 2 bits, but it could be widened in future if necessary. include/opcode/ * aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd. (AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4) (AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR) (AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2) (AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX) (AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2) (AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ) (AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2) (AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14) (AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14) (AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14) (AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14) (AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5) (AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4) (AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL) (AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW): Likewise. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE address operands. * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14) (FLD_SVE_xs_22): New aarch64_field_kinds. (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags. (get_operand_specific_data): New function. * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14 and FLD_SVE_xs_22. (operand_general_constraint_met_p): Handle the new SVE address operands. (sve_reg): New array. (get_addr_sve_reg_name): New function. (aarch64_print_operand): Handle the new SVE address operands. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl) (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl) (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters. * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function. (aarch64_ins_sve_addr_rr_lsl): Likewise. (aarch64_ins_sve_addr_rz_xtw): Likewise. (aarch64_ins_sve_addr_zi_u5): Likewise. (aarch64_ins_sve_addr_zz): Likewise. (aarch64_ins_sve_addr_zz_lsl): Likewise. (aarch64_ins_sve_addr_zz_sxtw): Likewise. (aarch64_ins_sve_addr_zz_uxtw): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl) (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl) (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors. * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function. (aarch64_ext_sve_addr_ri_u6): Likewise. (aarch64_ext_sve_addr_rr_lsl): Likewise. (aarch64_ext_sve_addr_rz_xtw): Likewise. (aarch64_ext_sve_addr_zi_u5): Likewise. (aarch64_ext_sve_addr_zz): Likewise. (aarch64_ext_sve_addr_zz_lsl): Likewise. (aarch64_ext_sve_addr_zz_sxtw): Likewise. (aarch64_ext_sve_addr_zz_uxtw): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (aarch64_addr_reg_parse): New function, split out from aarch64_reg_parse_32_64. Handle Z registers too. (aarch64_reg_parse_32_64): Call it. (parse_address_main): Add base_qualifier, offset_qualifier and accept_sve parameters. Handle SVE base and offset registers. (parse_address): Update call to parse_address_main. (parse_address_reloc): Likewise. (parse_sve_address): New function. (parse_operands): Parse the new SVE address operands. Change-Id: Ic68d4760e4f610e736aa3dc79d2eb7858b29db27
* [AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford2016-08-2312-19/+148
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SVE instructions count the number of elements in a given vector pattern and allow a scale factor of [1, 16] to be applied to the result. This scale factor is written ", MUL #n", where "MUL" is a new operator. E.g.: UQINCD X0, POW2, MUL #2 This patch adds support for this kind of operand. All existing operators were shifts of some kind, so there was a natural range of [0, 63] regardless of context. This was then narrowered further by later checks (e.g. to [0, 31] when used for 32-bit values). In contrast, MUL doesn't really have a natural context-independent range. Rather than pick one arbitrarily, it seemed better to make the "shift" amount a full 64-bit value and leave the range test to the usual operand-checking code. I've rearranged the fields of aarch64_opnd_info so that this doesn't increase the size of the structure (although I don't think its size is critical anyway). include/opcode/ * aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New aarch64_opnd. (AARCH64_MOD_MUL): New aarch64_modifier_kind. (aarch64_opnd_info): Make shifter.amount an int64_t and rearrange the fields. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for AARCH64_OPND_SVE_PATTERN_SCALED. * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind. * aarch64-opc.c (fields): Add a corresponding entry. (set_multiplier_out_of_range_error): New function. (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL. (operand_general_constraint_met_p): Handle AARCH64_OPND_SVE_PATTERN_SCALED. (print_register_offset_address): Use PRIi64 to print the shift amount. (aarch64_print_operand): Likewise. Handle AARCH64_OPND_SVE_PATTERN_SCALED. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_scale): New inserter. * aarch64-asm.c (aarch64_ins_sve_scale): New function. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_scale): New inserter. * aarch64-dis.c (aarch64_ext_sve_scale): New function. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode. (parse_shift): Handle it. Reject AARCH64_MOD_MUL for all other shift modes. Skip range tests for AARCH64_MOD_MUL. (process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED. (parse_operands): Likewise. Change-Id: Ib37bb0dc49d7284c9bb90eb34e6ee0852df5c8a4
* [AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford2016-08-238-11/+180
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SVE instructions have two enumerated operands: one to select a vector pattern and another to select a prefetch operation. The latter is a cut-down version of the base AArch64 prefetch operation. Both types of operand can also be specified as raw enum values such as #31. Reserved values can only be specified this way. If it hadn't been for the pattern operand, I would have been tempted to use the existing parsing for prefetch operations and add extra checks for SVE. However, since the patterns needed new enum parsing code anyway, it seeemed cleaner to reuse it for the prefetches too. Because of the small number of enum values, I don't think we'd gain anything by using hash tables. include/opcode/ * aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd. (AARCH64_OPND_SVE_PRFOP): Likewise. (aarch64_sve_pattern_array): Declare. (aarch64_sve_prfop_array): Likewise. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP. * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind. (FLD_SVE_prfop): Likewise. * aarch64-opc.c: Include libiberty.h. (aarch64_sve_pattern_array): New variable. (aarch64_sve_prfop_array): Likewise. (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop. (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. gas/ * config/tc-aarch64.c (parse_enum_string): New function. (po_enum_or_fail): New macro. (parse_operands): Handle AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP. Change-Id: I42001f5da32d151fae8dc73e9a631811ef2ad2c1
* [AArch64][SVE 22/32] Add qualifiers for merging and zeroing predicationRichard Sandiford2016-08-233-4/+62
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds qualifiers to represent /z and /m suffixes on predicate registers. include/opcode/ * aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier. (AARCH64_OPND_QLF_P_M): Likewise. opcodes/ * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for AARCH64_OPND_QLF_P_[ZM]. (aarch64_print_operand): Print /z and /m where appropriate. gas/ * config/tc-aarch64.c (vector_el_type): Add NT_zero and NT_merge. (parse_vector_type_for_operand): Assert that the skipped character is a '.'. (parse_predication_for_operand): New function. (parse_typed_reg): Parse /z and /m suffixes for predicate registers. (vectype_to_qualifier): Handle NT_zero and NT_merge. Change-Id: I0e1463f446feeb2051ee9e4c832bbb31318ff05d
* [AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford2016-08-2312-33/+424
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the Zn and Pn registers, and associated fields and operands. include/opcode/ * aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New aarch64_operand_class. (AARCH64_OPND_CLASS_PRED_REG): Likewise. (AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5) (AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16) (AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt) (AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd) (AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn) (AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN) (AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands. * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5) (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt) (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16) (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds. * aarch64-opc.c (fields): Add corresponding entries here. (operand_general_constraint_met_p): Check that SVE register lists have the correct length. Check the ranges of SVE index registers. Check for cases where p8-p15 are used in 3-bit predicate fields. (aarch64_print_operand): Handle the new SVE operands. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters. * aarch64-asm.c (aarch64_ins_sve_index): New function. (aarch64_ins_sve_reglist): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors. * aarch64-dis.c (aarch64_ext_sve_index): New function. (aarch64_ext_sve_reglist): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (NTA_HASVARWIDTH): New macro. (AARCH64_REG_TYPES): Add ZN and PN. (get_reg_expected_msg): Handle them. (aarch64_check_reg_type): Likewise. Update comment for REG_TYPE_R_Z_BHSDQ_V. (parse_vector_type_for_operand): Add a reg_type parameter. Skip the width for Zn and Pn registers. (parse_typed_reg): Extend vector handling to Zn and Pn. Update the call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn, expecting the width to be 0. (parse_vector_reg_list): Restrict error about [BHSD]nn operands to REG_TYPE_VN. (vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH. (parse_operands): Handle the new Zn and Pn operands. (REGSET16): New macro, split out from... (REGSET31): ...here. (reg_names): Add Zn and Pn entries. Change-Id: Ife7d6978fb56e2483b9030e1b6f326d18557756b
* [AArch64][SVE 20/32] Add support for tied operandsRichard Sandiford2016-08-234-16/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SVE has some instructions in which the same register appears twice in the assembly string, once as an input and once as an output. This patch adds a general mechanism for that. The patch needs to add new information to the instruction entries. One option would have been to extend the flags field of the opcode to 64 bits (since we already rely on 64-bit integers being available on the host). However, the *_INSN macros mean that it's easy to add new information as top-level fields without affecting the existing table entries too much. Going for that option seemed to give slightly neater code. include/opcode/ * aarch64.h (aarch64_opcode): Add a tied_operand field. (AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind. opcodes/ * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN) (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN) (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field. * aarch64-opc.c (aarch64_match_operands_constraint): Check for tied operands. gas/ * config/tc-aarch64.c (output_operand_error_record): Handle AARCH64_OPDE_UNTIED_OPERAND. Change-Id: Iad542d45bc8fc13eedeff75092b94c124615ca22
* [AArch64][SVE 19/32] Refactor address-printing codeRichard Sandiford2016-08-231-36/+56
| | | | | | | | | | | | | | | | | | | | SVE adds addresses in which the base or offset are vector registers. The addresses otherwise have the same kind of form as normal AArch64 addresses, including things like SXTW with or without a shift, UXTW with or without a shift, and LSL. This patch therefore refactors the address-printing code so that it can cope with both scalar and vector registers. opcodes/ * aarch64-opc.c (get_offset_int_reg_name): New function. (print_immediate_offset_address): Likewise. (print_register_offset_address): Take the base and offset registers as parameters. (aarch64_print_operand): Update caller accordingly. Use print_immediate_offset_address. Change-Id: Ib975218f68fd866a50184d82ed3ea9bc792bbf02
* [AArch64][SVE 18/32] Tidy definition of aarch64-opc.c:int_regRichard Sandiford2016-08-231-18/+11
| | | | | | | | | | | | | Use a macro to define 31 regular registers followed by a supplied value for 0b11111. The SVE code will also use this for vector base and offset registers. opcodes/ * aarch64-opc.c (BANK): New macro. (R32, R64): Take a register number as argument (int_reg): Use BANK. Change-Id: I0948da47ece3cd5d8d101b8002d8f828738d7b60
* [AArch64][SVE 17/32] Add a prefix parameter to print_register_listRichard Sandiford2016-08-231-13/+16
| | | | | | | | | | | | This patch generalises the interface to print_register_list so that it can print register lists involving SVE z registers as well as AdvSIMD v ones. opcodes/ * aarch64-opc.c (print_register_list): Add a prefix parameter. (aarch64_print_operand): Update accordingly. Change-Id: Iae90472b0e2ef7acfcf749bd1d4296ccf82378d6
* [AArch64][SVE 16/32] Use specific insert/extract methods for fpimmRichard Sandiford2016-08-237-6/+28
| | | | | | | | | | | | | | | | | | | | FPIMM used the normal "imm" insert/extract methods, with a specific test for FPIMM in the extract method. SVE needs to use the same extractors, so rather than add extra checks for specific operand types, it seemed cleaner to use a separate insert/extract method. opcodes/ * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm for FPIMM. * aarch64-asm.h (ins_fpimm): New inserter. * aarch64-asm.c (aarch64_ins_fpimm): New function. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_fpimm): New extractor. * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test. (aarch64_ext_fpimm): New function. * aarch64-dis-2.c: Regenerate. Change-Id: If0ebc825f03141677cd6ad41797ffc17d6de4d3d
* [AArch64][SVE 15/32] Add {insert,extract}_all_fields helpersRichard Sandiford2016-08-232-14/+42
| | | | | | | | | | | | | | | | Several of the SVE operands use the aarch64_operand fields array to store the fields that make up the operand, rather than hard-coding the names in the C code. This patch adds helpers for inserting and extracting those fields. opcodes/ * aarch64-asm.c: Include libiberty.h. (insert_fields): New function. (aarch64_ins_imm): Use it. * aarch64-dis.c (extract_fields): New function. (aarch64_ext_imm): Use it. Change-Id: I23658f0ea290c9a14380946c42e2d1d40997fd07
* [AArch64][SVE 14/32] Make aarch64_logical_immediate_p take an element sizeRichard Sandiford2016-08-232-29/+30
| | | | | | | | | | | | | | | | | | SVE supports logical immediate operations on 8-bit, 16-bit and 32-bit elements, treating them as aliases of operations on 64-bit elements in which the immediate is replicated. This patch therefore replaces the "32-bit/64-bit" input to aarch64_logical_immediate_p with a more general "number of bytes" input. opcodes/ * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32 with an esize parameter. (operand_general_constraint_met_p): Update accordingly. Fix misindented code. * aarch64-asm.c (aarch64_ins_limm): Update call to aarch64_logical_immediate_p. Change-Id: If8679882141d79580aa38603bc3aab90880539db
* [AArch64][SVE 13/32] Add an F_STRICT flagRichard Sandiford2016-08-233-6/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SVE predicate operands can appear in three forms: 1. unsuffixed: "Pn" 2. with a predication type: "Pn/[ZM]" 3. with a size suffix: "Pn.[BHSD]" No variation is allowed: unsuffixed operands cannot have a (redundant) suffix, and the suffixes can never be dropped. Unsuffixed Pn are used in LDR and STR, but they are also used for Pg operands in cases where the result is scalar and where there is therefore no choice to be made between "merging" and "zeroing". This means that some Pg operands have suffixes and others don't. It would be possible to use context-sensitive parsing to handle this difference. The tc-aarch64.c code would then raise an error if the wrong kind of suffix is used for a particular instruction. However, we get much more user-friendly error messages if we parse all three forms for all SVE instructions and record the suffix as a qualifier. The normal qualifier matching code can then report cases where the wrong kind of suffix is used. This is a slight extension of existing usage, which really only checks for the wrong choice of suffix within a particular kind of suffix. The only catch is a that a "NIL" entry in the qualifier list specifically means "no suffix should be present" (case 1 above). NIL isn't a wildcard here. It also means that an instruction that requires all-NIL qualifiers can fail to match (because a suffix was supplied when it shouldn't have been); this requires a slight change to find_best_match. This patch adds an F_STRICT flag to select this behaviour. The flag will be set for all SVE instructions. The behaviour for other instructions doesn't change. include/opcode/ * aarch64.h (F_STRICT): New flag. opcodes/ * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT. gas/ * config/tc-aarch64.c (find_best_match): Simplify, allowing an instruction with all-NIL qualifiers to fail to match. Change-Id: I4af1ba954da0478de1a124bce66d034eb949412f
* [AArch64][SVE 12/32] Make more use of bfd_booleanRichard Sandiford2016-08-231-12/+24
| | | | | | | | | | | | | | | | | | | | | Following on from the previous patch, which converted the aarch64_reg_parse_32_64 parameters to bfd_booleans, this one does the same for parse_address_main and parse_address. It also documents the parameters. This isn't an attempt to convert the whole file to use bfd_booleans more often. It's simply trying to avoid inconsistencies with new SVE parameters. gas/ * config/tc-aarch64.c (parse_address_main): Turn reloc and accept_reg_post_index into bfd_booleans. Add commentary. (parse_address_reloc): Update accordingly. Add commentary. (parse_address): Likewise. Also change accept_reg_post_index into a bfd_boolean here. (parse_operands): Update calls accordingly. Change-Id: Ia8f585035886401fe282377bb32c4192329896e4
* [AArch64][SVE 11/32] Tweak aarch64_reg_parse_32_64 interfaceRichard Sandiford2016-08-231-36/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | aarch64_reg_parse_32_64 is currently used to parse address registers, among other things. It returns two bits of information about the register: whether it's W rather than X, and whether it's a zero register. SVE adds addressing modes in which the base or offset can be a vector register instead of a scalar, so a choice between W and X is no longer enough. It's more convenient to pass the type of register around as a qualifier instead. As it happens, two callers of aarch64_reg_parse_32_64 already wanted the information in the form of a qualifier, so the change feels pretty natural even without SVE. Also, the function took two parameters to control whether {W}SP and (W|X)ZR should be accepted. These parameters were negative "reject" parameters, but the closely-related parse_address_main had a positive "accept" parameter (for post-indexed addressing). One of the SVE patches adds a parameter to parse_address_main that needs to be passed down alongside the aarch64_reg_parse_32_64 parameters, which as things stood led to an awkward mix of positive and negative bools. The patch therefore changes the aarch64_reg_parse_32_64 parameters to "accept_sp" and "accept_rz" instead. Finally, the two input parameters and isregzero return value were all ints but logically bools. The patch changes the types to bfd_boolean. gas/ * config/tc-aarch64.c (aarch64_reg_parse_32_64): Return the register type as a qualifier rather than an "isreg32" boolean. Turn the SP/ZR control parameters from negative "reject" to positive "accept". Make them and *ISREGZERO bfd_booleans rather than ints. (parse_shifter_operand): Update accordingly. (parse_address_main): Likewise. (po_int_reg_or_fail): Likewise. Make the same reject->accept change to the macro parameters. (parse_operands): Update after the above changes, replacing the "isreg32" local variable with one called "qualifier". Change-Id: Ifa366ca8105100004ca86a04fa28457c85810d84
* [AArch64][SVE 10/32] Move range check out of parse_aarch64_imm_floatRichard Sandiford2016-08-231-8/+6
| | | | | | | | | | | | Since some SVE constants are no longer explicitly tied to the 8-bit FP immediate format, it seems better to move the range checks out of parse_aarch64_imm_float and into the callers. gas/ * config/tc-aarch64.c (parse_aarch64_imm_float): Remove range check. (parse_operands): Check the range of 8-bit FP immediates here instead. Change-Id: I5cbffb01f84e23f85b2899f2fde7e9b341bcbbf9
* [AArch64][SVE 09/32] Improve error messages for invalid floatsRichard Sandiford2016-08-233-6/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously: fmov d0, #2 would give an error: Operand 2 should be an integer register whereas the user probably just forgot to add the ".0" to make: fmov d0, #2.0 This patch reports an invalid floating point constant unless the operand is obviously a register. The FPIMM8 handling is only relevant for SVE. Without it: fmov z0, z1 would try to parse z1 as an integer immediate zero (the res2 path), whereas it's more likely that the user forgot the predicate. This is tested by the final patch. gas/ * config/tc-aarch64.c (parse_aarch64_imm_float): Report a specific low-severity error for registers. (parse_operands): Report an invalid floating point constant for if parsing an FPIMM8 fails, and if no better error has been recorded. * testsuite/gas/aarch64/diagnostic.s, testsuite/gas/aarch64/diagnostic.l: Add tests for integer operands to FMOV. Change-Id: Iac44324b848a7a12d35c4fa4ec26931951b05e66
* [AArch64][SVE 08/32] Generalise aarch64_double_precision_fmovableRichard Sandiford2016-08-231-33/+29
| | | | | | | | | | | | | | | | | | | | | | | SVE has single-bit floating-point constants that don't really have any relation to the AArch64 8-bit floating-point encoding. (E.g. one of the constants selects between 0 and 1.) The easiest way of representing them in the aarch64_opnd_info seemed to be to use the IEEE float representation directly, rather than invent some new scheme. This patch paves the way for that by making the code that converts IEEE doubles to IEEE floats accept any value in the range of an IEEE float, not just zero and 8-bit floats. It leaves the range checking to the caller (which already handles it). gas/ * config/tc-aarch64.c (aarch64_double_precision_fmovable): Rename to... (can_convert_double_to_float): ...this. Accept any double-precision value that converts to single precision without loss of precision. (parse_aarch64_imm_float): Update accordingly. Change-Id: Id70057a30406b41613ede70acdb8b3366a109d0b
* [AArch64][SVE 07/32] Replace hard-coded uses of REG_TYPE_R_Z_BHSDQ_VRichard Sandiford2016-08-231-22/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To remove parsing ambiguities and to avoid register names being accidentally added to the symbol table, the immediate parsing routines reject things like: .equ x0, 0 add v0.4s, v0.4s, x0 An explicit '#' must be used instead: .equ x0, 0 add v0.4s, v0.4s, #x0 Of course, it wasn't possible to predict what other register names might be added in future, so this behaviour was restricted to the register names that were defined at the time. For backwards compatibility, we should continue to allow things like: .equ p0, 0 add v0.4s, v0.4s, p0 even though p0 is now an SVE register. However, it seems reasonable to extend the x0 behaviour above to SVE registers when parsing SVE instructions, especially since none of the SVE immediate formats are relocatable. Doing so removes the same parsing ambiguity for SVE instructions as the x0 behaviour removes for base AArch64 instructions. As a prerequisite, we then need to be able to tell the parsing routines which registers to reject. This patch changes the interface to make that possible, although the set of rejected registers doesn't change at this stage. gas/ * config/tc-aarch64.c (parse_immediate_expression): Add a reg_type parameter. (parse_constant_immediate): Likewise, and update calls. (parse_aarch64_imm_float): Likewise. (parse_big_immediate): Likewise. (po_imm_nc_or_fail): Update accordingly, passing down a new imm_reg_type variable. (po_imm_of_fail): Likewise. (parse_operands): Likewise. Change-Id: I315ee16d17c768d25bb9e0848bb14c4609435ecb
* [AArch64][SVE 06/32] Generalise parse_neon_reg_listRichard Sandiford2016-08-231-5/+8
| | | | | | | | | | | | | | Rename parse_neon_reg_list to parse_vector_reg_list and take in the required register type as an argument. Later patches will reuse the function for SVE registers. gas/ * config/tc-aarch64.c (parse_neon_reg_list): Rename to... (parse_vector_reg_list): ...this and take a register type as input. (parse_operands): Update accordingly. Change-Id: I0b9d19ca75f1feadae35091cc22f6992c729c63b
* [AArch64][SVE 05/32] Rename parse_neon_type_for_operandRichard Sandiford2016-08-231-2/+2
| | | | | | | | | | | | Generalise the name of parse_neon_type_for_operand to parse_vector_type_for_operand. Later patches will add SVEisms to it. gas/ * config/tc-aarch64.c (parse_neon_type_for_operand): Rename to... (parse_vector_type_for_operand): ...this. (parse_typed_reg): Update accordingly. Change-Id: I44a9128c2f912a95dec764b37f55a2c44808364e
* [AArch64][SVE 04/32] Rename neon_type_el to vector_type_elRichard Sandiford2016-08-231-16/+16
| | | | | | | | | | | | | | | | | | | Similar to the previous patch, but this time for the neon_type_el structure. gas/ * config/tc-aarch64.c (neon_type_el): Rename to... (vector_type_el): ...this. (parse_neon_type_for_operand): Update accordingly. (parse_typed_reg): Likewise. (aarch64_reg_parse): Likewise. (vectype_to_qualifier): Likewise. (parse_operands): Likewise. (eq_neon_type_el): Likewise. Rename to... (eq_vector_type_el): ...this. (parse_neon_reg_list): Update accordingly. Change-Id: Ib5c23f4f18a4c14025dd6aca732473291fdf1d9b
* [AArch64][SVE 03/32] Rename neon_el_type to vector_el_typeRichard Sandiford2016-08-231-4/+4
| | | | | | | | | | | | | | Later patches will add SVEisms to neon_el_type, so this patch renames it to something more generic. gas/ * config/tc-aarch64.c (neon_el_type: Rename to... (vector_el_type): ...this. (neon_type_el): Update accordingly. (parse_neon_type_for_operand): Likewise. (vectype_to_qualifier): Likewise. Change-Id: I4b9a803cb6ccd27edb3d794653a3cef95a9268f6
* [AArch64][SVE 02/32] Avoid hard-coded limit in indented_printRichard Sandiford2016-08-231-5/+1
| | | | | | | | | | | | The maximum indentation needed by aarch64-gen.c grows as more instructions are added to aarch64-tbl.h. Rather than having to increase the indentation limit to a higher value, it seemed better to replace it with "%*s". opcodes/ * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit. Change-Id: Id740909ecb53ee2d6ff4e08e525bcb5d96e9af99
* [AArch64][SVE 01/32] Remove parse_neon_operand_typeRichard Sandiford2016-08-231-27/+4
| | | | | | | | | | | | | | | | | | | | | | A false return from parse_neon_operand_type had an overloaded meaning: either the parsing failed, or there was nothing to parse (which isn't necessarily an error). The only caller, parse_typed_reg, would therefore not consume the suffix if it was invalid but instead (successfully) parse the register without a suffix. It would still leave inst.parsing_error with an error about the invalid suffix. It seems wrong for a successful parse to leave an error message, so this patch makes parse_typed_reg return PARSE_FAIL instead. The patch doesn't seem to make much difference in practice. Most possible follow-on errors use set_first_error and so the error about the suffix tended to win despite the successful parse. gas/ * config/tc-aarch64.c (parse_neon_operand_type): Delete. (parse_typed_reg): Call parse_neon_type_for_operand directly. Change-Id: I0b9c9048672c19390007452ae7fab5603fa03e4e
* [AArch64] Add V8_2_INSN macroRichard Sandiford2016-08-232-2/+9
| | | | | | | | | | | | | | | For consistency with the previous two patches, this one adds a macro for the two ARMv8.2 table entries. Both table entries need a non-null aarch64_op field. I haven't added macros for the RAS and STAT_PROFILE entries since there's only one of each. The series isn't getting rid of braced entries altogether, so I've only looked at replacing things that occur more than once. opcodes/ * aarch64-tbl.h (V8_2_INSN): New macro. (aarch64_opcode_table): Use it.
* [AArch64] Make more use of CORE/FP/SIMD_INSNRichard Sandiford2016-08-232-67/+72
| | | | | | | | | | After the previous patch, this one makes all CORE, FP and SIMD table entries with null "verify" fields use the associated macros. opcodes/ * aarch64-tbl.h (aarch64_opcode_table): Make more use of CORE_INSN, __FP_INSN and SIMD_INSN.
* [AArch64] Add OP parameter to aarch64-tbl.h macrosRichard Sandiford2016-08-232-722/+727
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nick recently wrapped most of aarch64-tbl.h entries in macros like CORE_INSN. These new macros assumed that the aarch64_op "op" field of aarch64_opcode is 0 and that the new "verifier" field is NULL. However, there are a lot of CORE, SIMD and FP insns whose table entries need a nonzero aarch64_op field, so these entries continued to use a braced list instead of a macro. This makes the table entries less consistent and means that there are still quite a few braced entries that need to be updated when making further changes to the aarch64_opcode structure. I think the number of entries that need a nonzero aarch64_op field is high enough to justify having an explicit aarch64_op entry for all CORE, SIMD and FP entries. This patch adds one and updates all existing uses of the macros. A following patch makes more use of the macros. I've followed existing practice by using 0 instead of OP_NIL for empty aarch64_op fields. Empty fields are still the norm and you need to know what the fields are when reading the table anyway, so it was hard to justify an additional patch to replace all 0 op fields with OP_NIL. opcodes/ * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter. (aarch64_opcode_table): Update uses accordingly.
* Fix duplicate FAILs from ld testsuiteAlan Modra2016-08-232-10/+9
| | | | | * testsuite/lib/ld-lib.exp (run_cc_link_tests): Don't fail tests twice.
* R_OR1K_GOTOFF_* relocationsAlan Modra2016-08-232-1/+10
| | | | | | PR 20475 * elf32-or1k.c (or1k_elf_relocate_section): Offset from _GLOBAL_OFFSET_TABLE_, not start of .got section.
* Automatic date update in version.inGDB Administrator2016-08-231-1/+1
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* Fix PR gdb/20505 - Make vDSO detection work with core filesPedro Alves2016-08-224-29/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loading a core dump that was either generated on a system running pristine glibc master, or on a Fedora/RHEL system with LD_DEBUG=unused set in the environment, solib-svr4.c:svr4_current_sos fails to filter out the vDSO, resulting in: (gdb) core-file corefile.core^M [New LWP 2362]^M warning: Could not load shared library symbols for linux-vdso.so.1.^M Do you need "set solib-search-path" or "set sysroot"?^M Core was generated by `build-gdb/gdb/testsuite/outputs/gdb.base/corefile/'.^M ... The problem is that gdbarch_vsyscall_range does not support core inferiors at all. When live debugging, we're finding the vDSO's start address with auxv/AT_SYSINFO_EHDR, and then we find the vDSO's size by look for the corresponding mapping, by parsing /proc/PID/maps. When debugging a core dump, we can also determine the starting address from auxv/AT_SYSINFO_EHDR. However, we obviously can't read the core mappings out of the host's /proc. But we can instead look for a corresponding load segment in the core's bfd. gdb/ChangeLog: 2016-08-22 Pedro Alves <palves@redhat.com> PR gdb/20505 * linux-tdep.c (linux_vsyscall_range_raw): For core inferiors, find the vDSO's start address with AT_SYSINFO_EHDR too, and determine the vDSO's size by finding the PT_LOAD segment that matches AT_SYSINFO_EHDR. gdb/testsuite/ChangeLog: 2016-08-22 Pedro Alves <palves@redhat.com> PR gdb/20505 * gdb.base/vdso-warning.exp: Test core dumps too. Use with_test_prefix. Factor out bits to ... (test_no_vdso): ... this new procedure.
* Free the string buffer used by the chew program to hold each file it parses.Nick Clifton2016-08-222-0/+6
| | | | | * doc/chew.c (main): Free the string buffer used to files as they are parsed.
* Prevent a seg-fault in gprof when parsing a corrupt core file.Nick Clifton2016-08-222-0/+13
| | | | | | PR gprof/20499 * corefile.c (core_create_syms_from): Avoid walking off the end of the symbol table.
* Error on unsupported PowerPC ifuncsAlan Modra2016-08-222-10/+45
| | | | | | | | | | | | | | | The pr19784 tests fail on ppc32 due to a gcc bug. The failure should be noticed when building both libpr19784a.so and libpr19784b.so, rather than ld building a buggy libpr19784a.so that fails at run time. This patch fixes that by moving the @local ifunc check out of check_relocs, where a call destination may not yet be known to be ifunc. The patch also adds a related error for -mbss-plt code. * elf32-ppc.c (ppc_elf_check_relocs): Move error for @local ifunc.. (ppc_elf_relocate_section): ..to here. Comment. Error on detecting -mbss-plt -fPIC local ifuncs too. (ppc_elf_size_dynamic_sections): Comment on unnecessary glink branch table entries.
* Automatic date update in version.inGDB Administrator2016-08-221-1/+1
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* Automatic date update in version.inGDB Administrator2016-08-211-1/+1
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* Automatic date update in version.inGDB Administrator2016-08-201-1/+1
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* Fix missing files for ld when test suite not compiled in the source directoryCarl E. Love2016-08-197-22/+23
| | | | | | | | | | | | | | | | | | | | | | | | This patch fixes an issues with six test suite expect files that do not run correctly when the test suite is not built in the source directory. The issue is these tests are not using the current "standard_testfile" call but rather using the older set command to initialize the "testfile", "srcfile" and "binprefix" variables or are missing the set for the "binprefix" variable. ----------------------------------------------- gdb/testsuite/ChangeLog 2016-08-19 Carl Love <cel@us.ibm.com> * gdb.arch/altivec-regs.exp: Use standard_testfile instead of maintaining separate logic for constructing the output path. * gdb.arch/powerpc-d128-regs.exp: Likewise. * gdb.arch/ppc-dfp.exp: Likewise. * gdb.arch/ppc-fp.exp: Likewise. * gdb.arch/vsx-regs.exp: Likewise. * gdb.arch/altivec-abi.exp: Likewise, plus added local variable binprefix for generating the additional binary files.
* [AArch64] Match instruction "STP with base register" in prologueYao Qi2016-08-192-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Nowadays, we only match pre-indexed STP in prologue. Due to the change in gcc, https://gcc.gnu.org/ml/gcc-patches/2016-07/msg01933.html, it may generate "STP with base register" in prologue, which GDB doesn't handle. That is to say, previously GCC generates prologue like this, sub sp, sp, #490 stp x29, x30, [sp, #-96]! mov x29, sp with the gcc patch above, GCC generates prologue like like this, sub sp, sp, #4f0 stp x29, x30, [sp] mov x29, sp This patch is to teach GDB to recognize this instruction in prologue analysis. gdb: 2016-08-19 Yao Qi <yao.qi@linaro.org> * aarch64-tdep.c (aarch64_analyze_prologue): Handle register based STP instruction.
* null-terminate string in linespec_location_completerYao Qi2016-08-192-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If I build gdb with -fsanitize=address and run tests, I get error, malformed linespec error: unexpected colon^M (gdb) PASS: gdb.linespec/ls-errs.exp: lang=C: break : break :=================================================================^M ==3266==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x602000051451 at pc 0x2b5797a972a8 bp 0x7fffd8e0f3c0 sp 0x7fffd8e0f398^M READ of size 2 at 0x602000051451 thread T0 #0 0x2b5797a972a7 in __interceptor_strlen (/usr/lib/x86_64-linux-gnu/libasan.so.1+0x322a7)^M #1 0x7bd004 in compare_filenames_for_search(char const*, char const*) /home/yao/SourceCode/gnu/gdb/git/gdb/symtab.c:316^M #2 0x7bd310 in iterate_over_some_symtabs(char const*, char const*, int (*)(symtab*, void*), void*, compunit_symtab*, compunit_symtab*) /home/yao/SourceCode/gnu/gdb/git/gdb/symtab.c:411^M #3 0x7bd775 in iterate_over_symtabs(char const*, int (*)(symtab*, void*), void*) /home/yao/SourceCode/gnu/gdb/git/gdb/symtab.c:481^M #4 0x7bda15 in lookup_symtab(char const*) /home/yao/SourceCode/gnu/gdb/git/gdb/symtab.c:527^M #5 0x7d5e2a in make_file_symbol_completion_list_1 /home/yao/SourceCode/gnu/gdb/git/gdb/symtab.c:5635^M #6 0x7d61e1 in make_file_symbol_completion_list(char const*, char const*, char const*) /home/yao/SourceCode/gnu/gdb/git/gdb/symtab.c:5684^M #7 0x88dc06 in linespec_location_completer /home/yao/SourceCode/gnu/gdb/git/gdb/completer.c:288 .... 0x602000051451 is located 0 bytes to the right of 1-byte region [0x602000051450,0x602000051451)^M mallocated by thread T0 here: #0 0x2b5797ab97ef in __interceptor_malloc (/usr/lib/x86_64-linux-gnu/libasan.so.1+0x547ef)^M #1 0xbbfb8d in xmalloc /home/yao/SourceCode/gnu/gdb/git/gdb/common/common-utils.c:43^M #2 0x88dabd in linespec_location_completer /home/yao/SourceCode/gnu/gdb/git/gdb/completer.c:273^M #3 0x88e5ef in location_completer(cmd_list_element*, char const*, char const*) /home/yao/SourceCode/gnu/gdb/git/gdb/completer.c:531^M #4 0x8902e7 in complete_line_internal /home/yao/SourceCode/gnu/gdb/git/gdb/completer.c:964^ The code in question is here file_to_match = (char *) xmalloc (colon - text + 1); strncpy (file_to_match, text, colon - text + 1); it is likely that file_to_match is not null-terminated. The patch is to strncpy 'colon - text' bytes and explicitly set '\0'. gdb: 2016-08-19 Yao Qi <yao.qi@linaro.org> * completer.c (linespec_location_completer): Make file_to_match null-terminated.
* ARM: Issue a warning when the MRRC and MRRC2 instructions are used with the ↵Tamar Christina2016-08-195-0/+51
| | | | | | | | | same destination registers. * config/tc-arm.c (do_co_reg2c): Added constraint. * testsuite/gas/arm/dest-unpredictable.s: New. * testsuite/gas/arm/dest-unpredictable.l: New. * testsuite/gas/arm/dest-unpredictable.d: New.