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PR gas/23940
* macro.c (getstring): Check array bound before accessing.
(cherry picked from commit 10c172ba93dde7cb7c46982ca217e646565bf938)
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Fixes the linker testcase "Secure gateway veneers:cmse functions debug
information missing" which was failing due to output regular expression
mismatch on arm-none-linux-gnueabihf targets.
* ld/testsuite/ld-arm/cmse_main_sec_debug.d: Modify regexps to
allow for output from a arm-none-linux-gnueabihf target.
(cherry picked from commit 0c628bba5afd16e0ab3d78ca81ab3f2d5342c50c)
Committed on behalf of Srinath Parvathaneni.
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We're missing support for the GMID_EL1 system register from the Memory Tagging Extension in binutils.
This is specified at:
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/gmid_el1
This simple patch adds the support for this read-only register.
Tested make check on gas.
Backport from mainline
2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
(aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
Backport from mainline
2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test gmid_el1 read.
* testsuite/gas/aarch64/sysreg-4.d: Update expected output.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
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backport commit 13acf03468d1e218c0a980ff6e6adaaac4bb5d1e
failed to copy the changes in get_dynamic_type.
this could cause build failure
binutils/readelf.c:1800:1: warning: 'get_aarch64_dynamic_type' defined but not used [-Wunused-function]
binutils/ChangeLog:
2019-07-08 Szabolcs Nagy <szabolcs.nagy@arm.com>
* readelf.c (get_dynamic_type): Handle EM_AARCH64.
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PR 24785
* elf32-ppc.c (_bfd_elf_ppc_set_arch): Sanity check .PPC.EMB.apuinfo
size before reading first word.
(cherry picked from commit 62a47958bd6e3cbd909c2f19cd4669a9670ce4f1)
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Backport commit 823710d5856996d1f54f04ecb2f7647aeae99b5b
Backport commit 65f381e729bedb933f3e1376e7f53f0ff63ac9a8
Propagate STO_AARCH64_VARIANT_PCS st_other attribute to the output and
add DT_AARCH64_VARIANT_PCS dynamic tag if necessary.
Mismatching attributes are not diagnosed.
bfd/ChangeLog:
* elfnn-aarch64.c (elfNN_aarch64_merge_symbol_attribute): New function.
(struct elf_aarch64_link_hash_table): Add variant_pcs member.
(elfNN_aarch64_allocate_dynrelocs): Update variant_pcs.
(elfNN_aarch64_size_dynamic_sections): Add DT_AARCH64_VARIANT_PCS.
(elf_backend_merge_symbol_attribute): Define.
ld/ChangeLog:
* testsuite/ld-aarch64/aarch64-elf.exp: Add new tests.
* testsuite/ld-aarch64/variant_pcs-1.s: New asm for tests.
* testsuite/ld-aarch64/variant_pcs-2.s: New asm for tests.
* testsuite/ld-aarch64/variant_pcs-now.d: New test.
* testsuite/ld-aarch64/variant_pcs-r.d: New test.
* testsuite/ld-aarch64/variant_pcs-shared.d: New test.
* testsuite/ld-aarch64/variant_pcs.ld: New linker script for tests.
ld/ChangeLog:
* testsuite/ld-aarch64/variant_pcs-now.d: Use --hash-style=sysv.
* testsuite/ld-aarch64/variant_pcs-shared.d: Likewise.
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Backport commit 0b4eac57c44ec4c9e13f5201b40936c3b3e6c639
Allow st_other values such as STO_AARCH64_VARIANT_PCS to be set for alias
symbols independently. This is needed for ifunc symbols which are
aliased to the resolver using .set and don't expect resolver attributes
to override the ifunc symbol attributes. This means .variant_pcs must be
added explicitly to aliases.
gas/ChangeLog:
* config/tc-aarch64.c (aarch64_elf_copy_symbol_attributes): Define.
* config/tc-aarch64.h (aarch64_elf_copy_symbol_attributes): Declare.
(OBJ_COPY_SYMBOL_ATTRIBUTES): Define.
* testsuite/gas/aarch64/symbol-variant_pcs-3.d: New test.
* testsuite/gas/aarch64/symbol-variant_pcs-3.s: New test.
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Backport commit f166ae0188dcb89c5ae925034260a708a254ab2f
In ELF objects the specified symbol is marked with STO_AARCH64_VARIANT_PCS.
gas/ChangeLog:
* config/tc-aarch64.c (s_variant_pcs): New function.
* doc/c-aarch64.texi: Document .variant_pcs.
* testsuite/gas/aarch64/symbol-variant_pcs-1.d: New test.
* testsuite/gas/aarch64/symbol-variant_pcs-1.s: New test.
* testsuite/gas/aarch64/symbol-variant_pcs-2.d: New test.
* testsuite/gas/aarch64/symbol-variant_pcs-2.s: New test.
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Backport commit 2301ed1c9af1316b4bad3747d2b03f7d44940f87
The bottom 2 bits of st_other are used for visibility, the top 6 bits are
de facto reserved for processor specific use. This patch defines a
bits to mark function symbols that follow a variant procedure call standard
with different register usage convention.
A dynamic tag is also defined that marks modules with R_<CLS>_JUMP_SLOT
relocations referencing symbols marked with STO_AARCH64_VARIANT_PCS.
This can be used by dynamic linkers that support lazy binding to decide
what registers need to be preserved during symbol resolution.
binutils/ChangeLog:
* readelf.c (get_aarch64_dynamic_type): Handle DT_AARCH64_VARIANT_PCS.
(get_aarch64_symbol_other): New, handles STO_AARCH64_VARIANT_PCS.
(get_symbol_other): Call get_aarch64_symbol_other.
include/ChangeLog:
* elf/aarch64.h (DT_AARCH64_VARIANT_PCS): Define.
(STO_AARCH64_VARIANT_PCS): Define.
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the linker when performing garbage collection.
onsider a file containing only Armv8-M secure entry functions.
This file is compiled and linked with "-march=armv8-m.main -mfloat-abi=hard
-mfpu=fpv5-sp-d16 -mcmse -static --specs=rdimon.specs
-Wl,--section-start,.gnu.sgstubs=0x190000 -ffunction-sections
-fdata-sections
-Wl,--gc-sections -g" options to generate an executable.
The executable generated does not contain any debug information of these
secure entry
functions even though it contains secure entry functions in the .text
section.
Example:
$ cat main.c
int main (void)
{
return 0;
}
$ cat sec.c
void __attribute__((cmse_nonsecure_entry))
SecureLED_On ()
{
}
Generate the object files "main.o" and "sec.o" for above test, using
below command.
1. $ arm-none-eabi-gcc -march=armv8-m.main -mfloat-abi=hard
-mfpu=fpv5-sp-d16 -mcmse
-static --specs=rdimon.specs -ffunction-sections -fdata-sections main.c
sec.c -g -c
Using linker, generate the executable for above generated object files.
2.$ arm-none-eabi-ld --section-start .gnu.sgstubs=0x190000 --gc-sections
main.o sec.o -e0 -o main_sec.out
Check for "SecureLED_On" in dwarf information generated for executable
"main_sec.out".
3. $ arm-none-eabi-objdump --dwarf=info main_sec.out |grep "SecureLED_On"
There is no match for the function "SecureLED_On" in .dwarf_info.
After applying this patch and performing above steps 2 and 3, the output is:
<8f> DW_AT_name : (indirect string, offset: 0x9d):
SecureLED_On
This patch fixes the linker by marking all the debug sections (setting
gc_mark to 1)
when .text section containing secure entry functions is marked.
bfd * elf32-arm.c (elf32_arm_gc_mark_extra_sections): Mark debug
sections when .text section contain secure entry functions
is marked.
ld * testsuite/ld-arm/arm-elf.exp: Add tests.
* testsuite/ld-arm/cmse_main.s: New test.
* testsuite/ld-arm/cmse_main_sec_debug.d: Likewise.
* testsuite/ld-arm/cmse_sec_debug.s: Likewise.
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The entry for the FMOV alias of FCPY was missing C_SCAN_MOVPRFX.
(The entry for FCPY itself was OK.)
This was the only /m-predicated instruction I could see that was
missing the flag.
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
opcodes/
* aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
SVE FMOV alias of FCPY.
gas/
* testsuite/gas/aarch64/sve-movprfx_27.s,
* testsuite/gas/aarch64/sve-movprfx_27.d: New test.
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SVE FCVTZS, FCVTZU, SCVTF and UCVTF need the same treatment as FCVT:
the register size used in a predicated MOVPRFX must be the wider of
the destination and source sizes.
Since I was adding a (supposedly) complete set of tests for converts,
it seemed more consistent to add a complete set of tests for shifts
as well, even though there's no bug to fix there.
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
opcodes/
* aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
gas/
* testsuite/gas/aarch64/sve-movprfx_26.s: Also test FCVTZS, FCVTZU,
SCVTF, UCVTF, LSR and ASR.
* testsuite/gas/aarch64/sve-movprfx_26.d: Update accordingly.
* testsuite/gas/aarch64/sve-movprfx_26.l: Likewise.
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One of the MOVPRFX tests has:
output register of preceding `movprfx' used as input at operand 3 -- `cpy z1.d,p1/m,x1'
But X1 and Z1 are not the same register, so the instruction is
actually OK.
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
opcodes/
* aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
registers in an instruction prefixed by MOVPRFX.
gas/
* testsuite/gas/aarch64/sve-movprfx_25.s: Allow CPY Z1.D.P1/M,X1
to be prefixed by MOVPRFX.
* testsuite/gas/aarch64/sve-movprfx_25.d: Update accordingly.
* testsuite/gas/aarch64/sve-movprfx_25.l: Likewise.
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