diff options
Diffstat (limited to 'sim/mips/mips.igen')
| -rw-r--r-- | sim/mips/mips.igen | 57 |
1 files changed, 34 insertions, 23 deletions
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index fece487e10d..81fb2001b27 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -4271,6 +4271,22 @@ } +010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1 +"luxc1 f<FD>, r<INDEX>(r<BASE>)" +*mipsV: +*mips64: +{ + address_word base = GPR[BASE]; + address_word index = GPR[INDEX]; + address_word vaddr = base + index; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + /* Arrange for the bottom 3 bits of (base + index) to be 0. */ + if ((vaddr & 0x7) != 0) + index -= (vaddr & 0x7); + COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index)); +} + 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1 "lwc1 f<FT>, <OFFSET>(r<BASE>)" @@ -4743,6 +4759,24 @@ } +010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1 +"suxc1 f<FS>, r<INDEX>(r<BASE>)" +*mipsV: +*mips64: +{ + unsigned64 v; + address_word base = GPR[BASE]; + address_word index = GPR[INDEX]; + address_word vaddr = base + index; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + /* Arrange for the bottom 3 bits of (base + index) to be 0. */ + if ((vaddr & 0x7) != 0) + index -= (vaddr & 0x7); + do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS)); +} + + 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt "sqrt.%s<FMT> f<FD>, f<FS>" *mipsII: @@ -4994,17 +5028,6 @@ } -010000,1,0000000000000000000,111001:COP0:32::DI -"di" -*mipsI: -*mipsII: -*mipsIII: -*mipsIV: -*mipsV: -*vr4100: -*vr5000: - - 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0 "dmfc0 r<RT>, r<RD>" *mipsIII: @@ -5029,18 +5052,6 @@ } -010000,1,0000000000000000000,111000:COP0:32::EI -"ei" -*mipsI: -*mipsII: -*mipsIII: -*mipsIV: -*mipsV: -*mips64: -*vr4100: -*vr5000: - - 010000,1,0000000000000000000,011000:COP0:32::ERET "eret" *mipsIII: |