diff options
Diffstat (limited to 'ld')
| -rw-r--r-- | ld/ChangeLog | 7 | ||||
| -rw-r--r-- | ld/emulparams/elf32_spu.sh | 3 | ||||
| -rw-r--r-- | ld/emulparams/elf32ppc.sh | 8 | ||||
| -rw-r--r-- | ld/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | ld/testsuite/ld-spu/ear.s | 3 | ||||
| -rw-r--r-- | ld/testsuite/ld-spu/embed.rd | 24 |
6 files changed, 37 insertions, 13 deletions
diff --git a/ld/ChangeLog b/ld/ChangeLog index 08739611387..87679e9e62f 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,5 +1,12 @@ 2008-05-08 Alan Modra <amodra@bigpond.net.au> + * elf32_spu.sh (OTHER_SECTIONS): Add "._ea". + * elf32ppc.sh: If building with spu support, put ".data.spehandle" + sections at the start of ".data" and provide a symbol to locate + the directory of embedded spe programs. + +2008-05-08 Alan Modra <amodra@bigpond.net.au> + * ldexp.c (exp_print_token): Add ABSOLUTE, MIN_K, ASSERT_K. Correct MAX_K. (fold_binary <SEGMENT_START>): Set expld.result.section to diff --git a/ld/emulparams/elf32_spu.sh b/ld/emulparams/elf32_spu.sh index 4af608cb2e1..52a3e7be69b 100644 --- a/ld/emulparams/elf32_spu.sh +++ b/ld/emulparams/elf32_spu.sh @@ -17,4 +17,5 @@ EMBEDDED=true MAXPAGESIZE=0x80 DATA_ADDR="ALIGN(${MAXPAGESIZE})" OTHER_BSS_SECTIONS=".toe ALIGN(128) : { *(.toe) } = 0" -OTHER_SECTIONS=".note.spu_name 0 : { KEEP(*(.note.spu_name)) }" +OTHER_SECTIONS=".note.spu_name 0 : { KEEP(*(.note.spu_name)) } + ._ea 0 : { KEEP(*(._ea)) }" diff --git a/ld/emulparams/elf32ppc.sh b/ld/emulparams/elf32ppc.sh index 68962d7325d..7349993f6c5 100644 --- a/ld/emulparams/elf32ppc.sh +++ b/ld/emulparams/elf32ppc.sh @@ -14,3 +14,11 @@ PLT=".plt ${RELOCATING-0} : SPECIAL { *(.plt) }" GOTPLT="${PLT}" OTHER_TEXT_SECTIONS="*(.glink)" EXTRA_EM_FILE=ppc32elf +if grep -q 'ld_elf32_spu_emulation' ldemul-list.h; then +# crt1.o defines data_start and __data_start. Keep them first. +# Next put all the .data.spehandle sections, with a trailing zero word. + DATA_START_SYMBOLS="${RELOCATING+*crt1.o(.data .data.* .gnu.linkonce.d.*) + PROVIDE (__spe_handle = .); + *(.data.spehandle) + . += 4 * (DEFINED (__spe_handle) || . != 0);}" +fi diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog index ddbd75dadc9..5383fbd108b 100644 --- a/ld/testsuite/ChangeLog +++ b/ld/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2008-05-08 Alan Modra <amodra@bigpond.net.au> + + * ld-spu/ear.s: Align various sections. + * ld-spu/embed.rd: Update. + 2008-05-05 Alan Modra <amodra@bigpond.net.au> PR 6473 diff --git a/ld/testsuite/ld-spu/ear.s b/ld/testsuite/ld-spu/ear.s index ba0be05c650..724a52583a9 100644 --- a/ld/testsuite/ld-spu/ear.s +++ b/ld/testsuite/ld-spu/ear.s @@ -5,6 +5,7 @@ _start: #test old-style toe _EAR_ syms .section .toe,"a",@nobits + .p2align 4 _EAR_: .space 16 _EAR_bar: @@ -12,6 +13,7 @@ _EAR_bar: #test new-style _EAR_ syms .data + .p2align 4 _EAR_main: .space 16 @@ -21,5 +23,6 @@ _EAR_foo: .space 16 .section .data.blah,"aw",@progbits + .p2align 4 _EAR_blah: .space 16 diff --git a/ld/testsuite/ld-spu/embed.rd b/ld/testsuite/ld-spu/embed.rd index 0ac34da8ce0..4fcfe2ae125 100644 --- a/ld/testsuite/ld-spu/embed.rd +++ b/ld/testsuite/ld-spu/embed.rd @@ -1,16 +1,16 @@ Relocation section '\.rela\.rodata\.speelf' at .* contains 3 entries: - Offset Info Type Sym\. Value Symbol's Name \+ Addend -00000184 00000601 R_PPC_ADDR32 00000000 main \+ 0 -000001a4 00000901 R_PPC_ADDR32 00000000 foo \+ 0 -000001b4 00000701 R_PPC_ADDR32 00000000 blah \+ 0 - -Relocation section '\.rela\.data' at .* contains 2 entries: - Offset Info Type Sym\. Value Symbol's Name \+ Addend -00000004 00000201 R_PPC_ADDR32 00000000 \.rodata\.speelf \+ 0 -00000008 00000401 R_PPC_ADDR32 00000000 \.data\.spetoe \+ 0 + Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend +0+184 .* R_PPC_ADDR32 +0+0 +main \+ 0 +0+1a4 .* R_PPC_ADDR32 +0+0 +foo \+ 0 +0+1b4 .* R_PPC_ADDR32 +0+0 +blah \+ 0 Relocation section '\.rela\.data\.spetoe' at .* contains 2 entries: - Offset Info Type Sym\. Value Symbol's Name \+ Addend -00000004 00000201 R_PPC_ADDR32 00000000 \.rodata\.speelf \+ 0 -00000014 00000a01 R_PPC_ADDR32 00000000 bar \+ 0 + Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend +0+004 .* R_PPC_ADDR32 +0+0 +\.rodata\.speelf \+ 0 +0+014 .* R_PPC_ADDR32 +0+0 +bar \+ 0 + +Relocation section '\.rela\.data\.spehandle' at .* contains 2 entries: + Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend +0+004 .* R_PPC_ADDR32 +0+0 +\.rodata\.speelf \+ 0 +0+008 .* R_PPC_ADDR32 +0+0 +\.data\.spetoe \+ 0 |