diff options
Diffstat (limited to 'include/opcode/mips.h')
| -rw-r--r-- | include/opcode/mips.h | 28 |
1 files changed, 24 insertions, 4 deletions
diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 65434a77853..9dab6206097 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -236,11 +236,24 @@ struct mips_opcode "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT). Enforces: 0 <= pos < 32. "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB). - Requires that "+A" occur first to set position. + Requires that "+A" or "+E" occur first to set position. Enforces: 0 < (pos+size) <= 32. "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD). - Requires that "+A" occur first to set position. + Requires that "+A" or "+E" occur first to set position. Enforces: 0 < (pos+size) <= 32. + (Also used by "dext" w/ different limits, but limits for + that are checked by the M_DEXT macro.) + "+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT). + Enforces: 32 <= pos < 64. + "+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB). + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. + "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. + "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. Floating point instructions: "D" 5 bit destination register (OP_*_FD) @@ -265,7 +278,8 @@ struct mips_opcode Macro instructions: "A" General 32 bit expression - "I" 32 bit immediate + "I" 32 bit immediate (value placed in imm_expr). + "+I" 32 bit immediate (value placed in imm2_expr). "F" 64 bit floating point constant in .rdata "L" 64 bit floating point constant in .lit8 "f" 32 bit floating point constant @@ -292,7 +306,7 @@ struct mips_opcode Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: - "ABCD" + "ABCDEFGHI" */ /* These are the bits which may be set in the pinfo field of an @@ -385,6 +399,7 @@ struct mips_opcode #define INSN_ISA32 0x00000020 #define INSN_ISA64 0x00000040 #define INSN_ISA32R2 0x00000080 +#define INSN_ISA64R2 0x00000100 /* Masks used for MIPS-defined ASEs. */ #define INSN_ASE_MASK 0x0000f000 @@ -432,6 +447,8 @@ struct mips_opcode #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) #define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) +#define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) + /* CPU defines, use instead of hardcoding processor number. Keep this in sync with bfd/archures.c in order for machine selection to work. */ @@ -460,6 +477,7 @@ struct mips_opcode #define CPU_MIPS32R2 33 #define CPU_MIPS5 5 #define CPU_MIPS64 64 +#define CPU_MIPS64R2 65 #define CPU_SB1 12310201 /* octal 'SB', 01. */ /* Test for membership in an ISA including chip specific ISAs. INSN @@ -542,6 +560,8 @@ enum M_DDIV_3I, M_DDIVU_3, M_DDIVU_3I, + M_DEXT, + M_DINS, M_DIV_3, M_DIV_3I, M_DIVU_3, |