diff options
Diffstat (limited to 'gas/testsuite/gas/d30v')
32 files changed, 2047 insertions, 0 deletions
diff --git a/gas/testsuite/gas/d30v/align.d b/gas/testsuite/gas/d30v/align.d new file mode 100644 index 00000000000..466768f5dc1 --- /dev/null +++ b/gas/testsuite/gas/d30v/align.d @@ -0,0 +1,17 @@ +#objdump: -dr +#name: D30V alignment test +#as: + +.*: +file format elf32-d30v + +Disassembly of section .text: + +0+0000 <start>: + 0: 08815a80 00f00000 abs r21, r42 || nop + 8: 08815a80 00f00000 abs r21, r42 || nop + 10: 08815a80 00f00000 abs r21, r42 || nop + 18: 00f00000 00f00000 abs r21, r42 || nop + 20: 08815a80 00f00000 abs r21, r42 || nop + 28: 08815a80 00f00000 abs r21, r42 || nop + 30: 08815a80 00f00000 abs r21, r42 || nop + ... diff --git a/gas/testsuite/gas/d30v/align.s b/gas/testsuite/gas/d30v/align.s new file mode 100644 index 00000000000..ef0039c6940 --- /dev/null +++ b/gas/testsuite/gas/d30v/align.s @@ -0,0 +1,28 @@ +# tests proper handling of aligns on D30V + + .text + .align 3 +start: + abs r21,r42 + .align 3 + abs r21,r42 + .align 4 + abs r21,r42 + .align 4 + abs r21,r42 + + .data + .long 0xdeadbeef + + .text + abs r21,r42 + + .data + .align 4 + .long 0xdeadbeef + + .text + .align 3 + abs r21,r42 + .end + diff --git a/gas/testsuite/gas/d30v/array.d b/gas/testsuite/gas/d30v/array.d new file mode 100644 index 00000000000..e81bc3394ea --- /dev/null +++ b/gas/testsuite/gas/d30v/array.d @@ -0,0 +1,31 @@ +#objdump: -dr +#name: D30V array test +#as: + +.*: +file format elf32-d30v + +Disassembly of section .text: + +0+0000 <__foo-0x48>: + 0: 880820c0 80000048 add.l r2, r3, 0x48 + 0: R_D30V_32 .text + 8: 880820c0 80000049 add.l r2, r3, 0x49 + 8: R_D30V_32 .text + 10: 880820c0 8000004a add.l r2, r3, 0x4a + 10: R_D30V_32 .text + 18: 880820c0 8000004b add.l r2, r3, 0x4b + 18: R_D30V_32 .text + 20: 880820c0 8000004c add.l r2, r3, 0x4c + 20: R_D30V_32 .text + 28: 880820c0 8000004d add.l r2, r3, 0x4d + 28: R_D30V_32 .text + 30: 880820c0 8000004e add.l r2, r3, 0x4e + 30: R_D30V_32 .text + 38: 880820c0 8000004f add.l r2, r3, 0x4f + 38: R_D30V_32 .text + 40: 880820c0 80000050 add.l r2, r3, 0x50 + 40: R_D30V_32 .text + +0+0048 <__foo>: + 48: 12345678 12345678 .long 0x12345678 || .long 0x12345678 + 50: 12345678 00000000 .long 0x12345678 || bra.s r0 diff --git a/gas/testsuite/gas/d30v/array.s b/gas/testsuite/gas/d30v/array.s new file mode 100644 index 00000000000..3a187dd5afa --- /dev/null +++ b/gas/testsuite/gas/d30v/array.s @@ -0,0 +1,15 @@ +# D30V array test + .text + add r2, r3 , __foo + add r2, r3 , __foo+1 + add r2, r3 , __foo+2 + add r2, r3 , __foo+3 + add r2, r3 , __foo+4 + add r2, r3 , __foo+5 + add r2, r3 , __foo+6 + add r2, r3 , __foo+7 + add r2, r3 , __foo+8 +__foo: + .int 0x12345678 + .int 0x12345678 + .int 0x12345678 diff --git a/gas/testsuite/gas/d30v/bittest.d b/gas/testsuite/gas/d30v/bittest.d new file mode 100644 index 00000000000..b96ab46cb84 --- /dev/null +++ b/gas/testsuite/gas/d30v/bittest.d @@ -0,0 +1,20 @@ +#objdump: -dr +#name: D30V bittest opt +#as: -WO + +.*: +file format elf32-d30v + +Disassembly of section .text: + +00000000 <.text>: + 0: 00f00000 84401083 nop -> ldw.s r1, @\(r2, r3\) + 8: 04406144 00f00000 ldw.s r6, @\(r5, r4\) || nop + 10: 00f00000 82201083 nop -> bset r1, r2, r3 + 18: 80f00000 02001083 nop <- btst f1, r2, r3 + 20: 00f00000 02301083 nop || bclr r1, r2, r3 + 28: 00f00000 82101083 nop -> bnot r1, r2, r3 + 30: 02101083 80f00000 bnot r1, r2, r3 -> nop + 38: 047c0105 02201083 moddec r4, 0x5 || bset r1, r2, r3 + 40: 02201083 847c0105 bset r1, r2, r3 -> moddec r4, 0x5 + 48: 02201083 08c04146 bset r1, r2, r3 || joinll.s r4, r5, r6 + 50: 02201083 08c04146 bset r1, r2, r3 || joinll.s r4, r5, r6
\ No newline at end of file diff --git a/gas/testsuite/gas/d30v/bittest.l b/gas/testsuite/gas/d30v/bittest.l new file mode 100644 index 00000000000..75d1b7ed544 --- /dev/null +++ b/gas/testsuite/gas/d30v/bittest.l @@ -0,0 +1,56 @@ +.*: Assembler messages: +.*: Warning: Swapping instruction order +.*: Warning: Executing bset in IU may not work +.*: Warning: Executing btst in IU may not work +.*: Warning: Executing bclr in IU may not work +.*: Warning: Executing bnot in IU may not work +.*: Warning: Executing bset in IU may not work +.*: Warning: Swapping instruction order +GAS LISTING .* + + + 1 # bittest.s + 2 # + 3 # Bit operation instructions \(BCLR, BNOT, BSET, BTST\) should not be placed in IU. + 4 # If the user specifically indicates they should be in the IU, GAS will + 5 # generate warnings. The reason why this is not an error is that those instructions + 6 # will fail in IU only occasionally. Thus GAS should pack them in MU for + 7 # safety, and it just needs to draw attention when a violation is given. + 8 + 9 + 10 0000 00F00000 nop -> ldw R1, @\(R2,R3\) + 10 84401083 + 11 0008 04406144 nop || ldw R6, @\(R5,R4\) +.* Warning:Swapping instruction order + 11 00F00000 + 12 + 13 0010 00F00000 nop -> BSET R1, R2, R3 +.* Warning:Executing bset in IU may not work + 13 82201083 + 14 0018 80F00000 nop <- BTST F1, R2, R3 +.* Warning:Executing btst in IU may not work + 14 02001083 + 15 0020 00F00000 nop || BCLR R1, R2, R3 +.* Warning:Executing bclr in IU may not work + 15 02301083 + 16 0028 00F00000 nop -> BNOT R1, R2, R3 +.* Warning:Executing bnot in IU may not work + 16 82101083 + 17 0030 02101083 BNOT r1, r2, r3 -> nop + 17 80F00000 + 18 + 19 0038 047C0105 bset r1, r2, r3 || moddec r4, 5 +.* Warning:Swapping instruction order + 19 02201083 + 20 + 21 bset r1, r2, r3 + 22 0040 02201083 moddec r4, 5 + 22 847C0105 + 23 + 24 bset r1, r2, r3 + 25 0048 02201083 joinll r4, r5, r6 + 25 88C04146 + 26 + 27 joinll r4, r5, r6 + 28 0050 82201083 bset r1, r2, r3 + 28 08C04146 diff --git a/gas/testsuite/gas/d30v/bittest.s b/gas/testsuite/gas/d30v/bittest.s new file mode 100644 index 00000000000..b79a56c95cd --- /dev/null +++ b/gas/testsuite/gas/d30v/bittest.s @@ -0,0 +1,28 @@ +# bittest.s +# +# Bit operation instructions (BCLR, BNOT, BSET, BTST) should not be placed in IU. +# If the user specifically indicates they should be in the IU, GAS will +# generate warnings. The reason why this is not an error is that those instructions +# will fail in IU only occasionally. Thus GAS should pack them in MU for +# safety, and it just needs to draw attention when a violation is given. + + + nop -> ldw R1, @(R2,R3) + nop || ldw R6, @(R5,R4) + + nop -> BSET R1, R2, R3 + nop <- BTST F1, R2, R3 + nop || BCLR R1, R2, R3 + nop -> BNOT R1, R2, R3 + BNOT r1, r2, r3 -> nop + + bset r1, r2, r3 || moddec r4, 5 + + bset r1, r2, r3 + moddec r4, 5 + + bset r1, r2, r3 + joinll r4, r5, r6 + + joinll r4, r5, r6 + bset r1, r2, r3 diff --git a/gas/testsuite/gas/d30v/d30.exp b/gas/testsuite/gas/d30v/d30.exp new file mode 100644 index 00000000000..275b0e06df1 --- /dev/null +++ b/gas/testsuite/gas/d30v/d30.exp @@ -0,0 +1,35 @@ +# +# D30V assembler tests +# + +proc run_list_test { name opts } { + global srcdir subdir + set testname "D30V $name" + set file $srcdir/$subdir/$name + gas_run ${name}.s $opts ">&dump.out" + if {[regexp_diff "dump.out" "${file}.l"] } { + fail $testname + verbose "output is [file_contents "dump.out"]" 2 + return + } + pass $testname +} + +if {[istarget d30v-*-*]} { + run_dump_test "inst" + run_dump_test "align" + run_dump_test "guard" + run_dump_test "guard-debug" + run_dump_test "reloc" + run_dump_test "opt" + run_dump_test "array" + run_dump_test "label" + run_list_test "warn_oddreg" "-al" + run_list_test "bittest" "-al" + run_dump_test "bittest" + run_list_test "serial" "-al" + run_list_test "serial2" "-al" + run_list_test "serial2O" "-al -O" + run_dump_test "mul" +} + diff --git a/gas/testsuite/gas/d30v/guard-debug.d b/gas/testsuite/gas/d30v/guard-debug.d new file mode 100644 index 00000000000..e9a154c851c --- /dev/null +++ b/gas/testsuite/gas/d30v/guard-debug.d @@ -0,0 +1,25 @@ +#objdump: -ldr +#name: D30V debug (-g) test +#as: -g + +.*: +file format elf32-d30v + +Disassembly of section .text: + +00000000 <.text>: +.*:[0-9]+ + 0: 08001083 00f00000 add.s r1, r2, r3 || nop +.*:[0-9]+ + 8: 08001083 00f00000 add.s r1, r2, r3 || nop +.*:[0-9]+ + 10: 18001083 00f00000 add.s/tx r1, r2, r3 || nop +.*:[0-9]+ + 18: 28001083 00f00000 add.s/fx r1, r2, r3 || nop +.*:[0-9]+ + 20: 38001083 00f00000 add.s/xt r1, r2, r3 || nop +.*:[0-9]+ + 28: 48001083 00f00000 add.s/xf r1, r2, r3 || nop +.*:[0-9]+ + 30: 58001083 00f00000 add.s/tt r1, r2, r3 || nop +.*:[0-9]+ + 38: 68001083 00f00000 add.s/tf r1, r2, r3 || nop diff --git a/gas/testsuite/gas/d30v/guard-debug.s b/gas/testsuite/gas/d30v/guard-debug.s new file mode 100644 index 00000000000..3f20f7b187d --- /dev/null +++ b/gas/testsuite/gas/d30v/guard-debug.s @@ -0,0 +1,17 @@ +# Same as guard.s but here we are testing debug (-g) assembly +# On the D30V, assembling with -g should disable the VLIW packing +# and put only one instruction per line. + + .text + + add r1,r2,r3 + add/al r1,r2,r3 + add/tx r1,r2,r3 + add/fx r1,r2,r3 + add/xt r1,r2,r3 + add/xf r1,r2,r3 + add/tt r1,r2,r3 + add/tf r1,r2,r3 + + + diff --git a/gas/testsuite/gas/d30v/guard.d b/gas/testsuite/gas/d30v/guard.d new file mode 100644 index 00000000000..0cfa2da7ae7 --- /dev/null +++ b/gas/testsuite/gas/d30v/guard.d @@ -0,0 +1,17 @@ +#objdump: -dr +#name: D30V guarded execution test +#as: + +.*: +file format elf32-d30v + +Disassembly of section .text: + +0+0000 <.text>: + 0: 08001083 88001083 add.s r1, r2, r3 -> add.s r1, r2, r3 + 8: 18001083 a8001083 add.s/tx r1, r2, r3 -> add.s/fx r1, r2, r3 + 10: 38001083 c8001083 add.s/xt r1, r2, r3 -> add.s/xf r1, r2, r3 + 18: 58001083 e8001083 add.s/tt r1, r2, r3 -> add.s/tf r1, r2, r3 + 20: 08001083 88001083 add.s r1, r2, r3 -> add.s r1, r2, r3 + 28: 18001083 a8001083 add.s/tx r1, r2, r3 -> add.s/fx r1, r2, r3 + 30: 38001083 c8001083 add.s/xt r1, r2, r3 -> add.s/xf r1, r2, r3 + 38: 58001083 e8001083 add.s/tt r1, r2, r3 -> add.s/tf r1, r2, r3 diff --git a/gas/testsuite/gas/d30v/guard.s b/gas/testsuite/gas/d30v/guard.s new file mode 100644 index 00000000000..ed9cd30bb4c --- /dev/null +++ b/gas/testsuite/gas/d30v/guard.s @@ -0,0 +1,24 @@ +# D30V guarded execution assembly test + + .text + + add r1,r2,r3 + add/al r1,r2,r3 + add/tx r1,r2,r3 + add/fx r1,r2,r3 + add/xt r1,r2,r3 + add/xf r1,r2,r3 + add/tt r1,r2,r3 + add/tf r1,r2,r3 + +# check case sensitivity too + ADD r1,r2,r3 + ADD/AL r1,r2,r3 + ADD/tx r1,r2,r3 + add/FX r1,r2,r3 + ADD/XT r1,r2,r3 + ADD/XF r1,r2,r3 + add/TT r1,r2,r3 + ADD/tf r1,r2,r3 + + diff --git a/gas/testsuite/gas/d30v/inst.d b/gas/testsuite/gas/d30v/inst.d new file mode 100644 index 00000000000..9861cbf6cf2 --- /dev/null +++ b/gas/testsuite/gas/d30v/inst.d @@ -0,0 +1,256 @@ +#objdump: -dr +#name: D30V basic instruction test +#as: + +.*: +file format elf32-d30v + +Disassembly of section .text: + +00000000 <start>: + 0: 08815a80 88001083 abs r21, r42 -> add.s r1, r2, r3 + 8: 080b2cda 00f00000 add.s r50, r51, 0x1a || nop + 10: 880b2cf7 8ab1beef add.l r50, r51, 0xdeadbeef + 18: 08101083 881b2cda add2h.s r1, r2, r3 -> add2h.s r50, r51, 0x1a + 20: 881b2cf7 8ab1beef add2h.l r50, r51, 0xdeadbeef + 28: 08401083 884b2cda addc.s r1, r2, r3 -> addc.s r50, r51, 0x1a + 30: 884b2cf7 8ab1beef addc.l r50, r51, 0xdeadbeef + 38: 09001083 890b2cda addhlll.s r1, r2, r3 -> addhlll.s r50, r51, 0x1a + 40: 890b2cf7 8ab1beef addhlll.l r50, r51, 0xdeadbeef + 48: 09101083 891b2cda addhllh.s r1, r2, r3 -> addhllh.s r50, r51, 0x1a + 50: 891b2cf7 8ab1beef addhllh.l r50, r51, 0xdeadbeef + 58: 09201083 892b2cda addhlhl.s r1, r2, r3 -> addhlhl.s r50, r51, 0x1a + 60: 892b2cf7 8ab1beef addhlhl.l r50, r51, 0xdeadbeef + 68: 09301083 893b2cda addhlhh.s r1, r2, r3 -> addhlhh.s r50, r51, 0x1a + 70: 893b2cf7 8ab1beef addhlhh.l r50, r51, 0xdeadbeef + 78: 09401083 894b2cda addhhll.s r1, r2, r3 -> addhhll.s r50, r51, 0x1a + 80: 894b2cf7 8ab1beef addhhll.l r50, r51, 0xdeadbeef + 88: 09501083 895b2cda addhhlh.s r1, r2, r3 -> addhhlh.s r50, r51, 0x1a + 90: 895b2cf7 8ab1beef addhhlh.l r50, r51, 0xdeadbeef + 98: 09601083 896b2cda addhhhl.s r1, r2, r3 -> addhhhl.s r50, r51, 0x1a + a0: 896b2cf7 8ab1beef addhhhl.l r50, r51, 0xdeadbeef + a8: 09701083 897b2cda addhhhh.s r1, r2, r3 -> addhhhh.s r50, r51, 0x1a + b0: 897b2cf7 8ab1beef addhhhh.l r50, r51, 0xdeadbeef + b8: 08601083 886b2cda adds.s r1, r2, r3 -> adds.s r50, r51, 0x1a + c0: 886b2cf7 8ab1beef adds.l r50, r51, 0xdeadbeef + c8: 08701083 887b2cda adds2h.s r1, r2, r3 -> adds2h.s r50, r51, 0x1a + d0: 887b2cf7 8ab1beef adds2h.l r50, r51, 0xdeadbeef + d8: 03801083 838b2cda and.s r1, r2, r3 -> and.s r50, r51, 0x1a + e0: 838b2cf7 8ab1beef and.l r50, r51, 0xdeadbeef + e8: 02800042 82883105 andfg f0, f1, f2 -> andfg f3, s, 0x5 + f0: 08a01083 88a84146 avg.s r1, r2, r3 -> avg.s r4, r5, 0x6 + f8: 88ab2cf7 8ab1beef avg.l r50, r51, 0xdeadbeef + 100: 08b01083 88b84146 avg2h.s r1, r2, r3 -> avg2h.s r4, r5, 0x6 + 108: 88bb2cf7 8ab1beef avg2h.l r50, r51, 0xdeadbeef + 110: 02301083 82384146 bclr r1, r2, r3 -> bclr r4, r5, 0x6 + 118: 02101083 82185cc6 bnot r1, r2, r3 -> bnot r5, r51, 0x6 + 120: 00000029 00f00000 bra.s r41 || nop + 128: 00080008 00f00000 bra.s 40 \(168 <start\+0x168>\) || nop + 130: 00081e01 00f00000 bra.s f008 \(f138 <start\+0xf138>\) || nop + 138: 0046902a 00f00000 bratnz.s r41, r42 || nop + 140: 804c1000 8000f00d bratnz.l r1, f00d \(f14d <start\+0xf14d>\) + 148: 804c1037 8ab1f00d bratnz.l r1, -21520ff3 \(deadf155 <start\+0xdeadf155>\) + 150: 0042902a 00f00000 bratzr.s r41, r42 || nop + 158: 80481000 8000f00d bratzr.l r1, f00d \(f165 <start\+0xf165>\) + 160: 80481037 8ab1f00d bratzr.l r1, -21520ff3 \(deadf16d <start\+0xdeadf16d>\) + 168: 02201083 82285cc6 bset r1, r2, r3 -> bset r5, r51, 0x6 + 170: 00200029 00f00000 bsr.s r41 || nop + 178: 00281e01 00f00000 bsr.s f008 \(f180 <start\+0xf180>\) || nop + 180: 80280037 8ab1f00d bsr.l -21520ff3 \(deadf18d <start\+0xdeadf18d>\) + 188: 0066902a 00f00000 bsrtnz.s r41, r42 || nop + 190: 806c1000 8000f00d bsrtnz.l r1, f00d \(f19d <start\+0xf19d>\) + 198: 806c1037 8ab1f00d bsrtnz.l r1, -21520ff3 \(deadf1a5 <start\+0xdeadf1a5>\) + 1a0: 0062902a 00f00000 bsrtzr.s r41, r42 || nop + 1a8: 80681000 8000f00d bsrtzr.l r1, f00d \(f1b5 <start\+0xf1b5>\) + 1b0: 80681037 8ab1f00d bsrtzr.l r1, -21520ff3 \(deadf1bd <start\+0xdeadf1bd>\) + 1b8: 02001083 82085cc6 btst f1, r2, r3 -> btst v, r51, 0x6 + 1c0: 02c000c1 82c09515 cmpeq.s f0, r3, r1 -> cmpne.s f1, r20, r21 + 1c8: 02c127e0 82c1b0c4 cmpgt.s f2, r31, r32 -> cmpge.s f3, r3, r4 + 1d0: 02c240c4 82c2d0c4 cmplt.s s, r3, r4 -> cmple.s v, r3, r4 + 1d8: 02c360c4 82c3f0c4 cmpps.s va, r3, r4 -> cmpng.s c, r3, r4 + 1e0: 02d127e0 82d1b0c4 cmpugt.s f2, r31, r32 -> cmpuge.s f3, r3, r4 + 1e8: 02d240c4 82d2d0c4 cmpult.s s, r3, r4 -> cmpule.s v, r3, r4 + 1f0: 01001008 81081020 dbra.s r1, r8 -> dbra.s r1, 100 \(2f0 <start\+0x2f0>\) + 1f8: 81081037 8ab1f00d dbra.l r1, -21520ff3 \(deadf205 <start\+0xdeadf205>\) + 200: 0140201f 81482020 dbrai.s 10, r31 -> dbrai.s 10, 100 \(300 <start\+0x300>\) + 208: 81482037 8ab1f00d dbrai.l 10, -21520ff3 \(deadf215 <start\+0xdeadf215>\) + 210: 01201008 00f00000 dbsr.s r1, r8 || nop + 218: 01281020 00f00000 dbsr.s r1, 100 \(318 <start\+0x318>\) || nop + 220: 81281037 8ab1f00d dbsr.l r1, -21520ff3 \(deadf22d <start\+0xdeadf22d>\) + 228: 0160401f 00f00000 dbsri.s 20, r31 || nop + 230: 01684020 00f00000 dbsri.s 20, 100 \(330 <start\+0x330>\) || nop + 238: 81684037 8ab1f00d dbsri.l 20, -21520ff3 \(deadf245 <start\+0xdeadf245>\) + 240: 01101020 00f00000 djmp.s r1, r32 || nop + 248: 81181000 8000f00d djmp.l r1, f00d <start\+0xf00d> + 250: 81181037 8ab1f00d djmp.l r1, deadf00d <start\+0xdeadf00d> + 258: 01506020 00f00000 djmpi.s 30, r32 || nop + 260: 81586000 8000f00d djmpi.l 30, f00d <start\+0xf00d> + 268: 81586037 8ab1f00d djmpi.l 30, deadf00d <start\+0xdeadf00d> + 270: 01301020 00f00000 djsr.s r1, r32 || nop + 278: 81381000 8000f00d djsr.l r1, f00d <start\+0xf00d> + 280: 81381037 8ab1f00d djsr.l r1, deadf00d <start\+0xdeadf00d> + 288: 01702020 00f00000 djsri.s 10, r32 || nop + 290: 81784000 8000f00d djsri.l 20, f00d <start\+0xf00d> + 298: 81788037 8ab1f00d djsri.l 40, deadf00d <start\+0xdeadf00d> + 2a0: 00100029 00f00000 jmp.s r41 || nop + 2a8: 00181e01 00f00000 jmp.s f008 <start\+0xf008> || nop + 2b0: 80180037 8ab1f00d jmp.l deadf00d <start\+0xdeadf00d> + 2b8: 0056902a 00f00000 jmptnz.s r41, r42 || nop + 2c0: 805c1000 8000f00d jmptnz.l r1, f00d <start\+0xf00d> + 2c8: 805c1037 8ab1f00d jmptnz.l r1, deadf00d <start\+0xdeadf00d> + 2d0: 0052902a 00f00000 jmptzr.s r41, r42 || nop + 2d8: 80581000 8000f00d jmptzr.l r1, f00d <start\+0xf00d> + 2e0: 80581037 8ab1f00d jmptzr.l r1, deadf00d <start\+0xdeadf00d> + 2e8: 08c01084 88c8108f joinll.s r1, r2, r4 -> joinll.s r1, r2, 0xf + 2f0: 88c810b7 8ab1f00d joinll.l r1, r2, 0xdeadf00d + 2f8: 08d01084 88d8108f joinlh.s r1, r2, r4 -> joinlh.s r1, r2, 0xf + 300: 88d810b7 8ab1f00d joinlh.l r1, r2, 0xdeadf00d + 308: 08e01084 88e8108f joinhl.s r1, r2, r4 -> joinhl.s r1, r2, 0xf + 310: 88e810b7 8ab1f00d joinhl.l r1, r2, 0xdeadf00d + 318: 08f01084 88f8108f joinhh.s r1, r2, r4 -> joinhh.s r1, r2, 0xf + 320: 88f810b7 8ab1f00d joinhh.l r1, r2, 0xdeadf00d + 328: 00300029 00f00000 jsr.s r41 || nop + 330: 00381e01 00f00000 jsr.s f008 <start\+0xf008> || nop + 338: 80380037 8ab1f00d jsr.l deadf00d <start\+0xdeadf00d> + 340: 0076902a 00f00000 jsrtnz.s r41, r42 || nop + 348: 807c1000 8000f00d jsrtnz.l r1, f00d <start\+0xf00d> + 350: 807c1037 8ab1f00d jsrtnz.l r1, deadf00d <start\+0xdeadf00d> + 358: 0072902a 00f00000 jsrtzr.s r41, r42 || nop + 360: 80781000 8000f00d jsrtzr.l r1, f00d <start\+0xf00d> + 368: 80781037 8ab1f00d jsrtzr.l r1, deadf00d <start\+0xdeadf00d> + 370: 043061c8 843461c8 ld2h.s r6, @\(r7, r8\) -> ld2h.s r6, @\(r7\+, r8\) + 378: 043c61c8 843861da ld2h.s r6, @\(r7-, r8\) -> ld2h.s r6, @\(r7, 0x1a\) + 380: 843861c0 80001234 ld2h.l r6, @\(r7, 0x1234\) + 388: 046061c8 846461c8 ld2w.s r6, @\(r7, r8\) -> ld2w.s r6, @\(r7\+, r8\) + 390: 046c61c8 846861da ld2w.s r6, @\(r7-, r8\) -> ld2w.s r6, @\(r7, 0x1a\) + 398: 846861c0 80001234 ld2w.l r6, @\(r7, 0x1234\) + 3a0: 045061c8 845461c8 ld4bh.s r6, @\(r7, r8\) -> ld4bh.s r6, @\(r7\+, r8\) + 3a8: 045c61c8 845861da ld4bh.s r6, @\(r7-, r8\) -> ld4bh.s r6, @\(r7, 0x1a\) + 3b0: 845861c0 80001234 ld4bh.l r6, @\(r7, 0x1234\) + 3b8: 04d061c8 84d461c8 ld4bhu.s r6, @\(r7, r8\) -> ld4bhu.s r6, @\(r7\+, r8\) + 3c0: 04dc61c8 84d861da ld4bhu.s r6, @\(r7-, r8\) -> ld4bhu.s r6, @\(r7, 0x1a\) + 3c8: 84d861c0 80001234 ld4bhu.l r6, @\(r7, 0x1234\) + 3d0: 040061c8 840461c8 ldb.s r6, @\(r7, r8\) -> ldb.s r6, @\(r7\+, r8\) + 3d8: 040c61c8 840861da ldb.s r6, @\(r7-, r8\) -> ldb.s r6, @\(r7, 0x1a\) + 3e0: 840861c0 80001234 ldb.l r6, @\(r7, 0x1234\) + 3e8: 049061c8 849461c8 ldbu.s r6, @\(r7, r8\) -> ldbu.s r6, @\(r7\+, r8\) + 3f0: 049c61c8 849861da ldbu.s r6, @\(r7-, r8\) -> ldbu.s r6, @\(r7, 0x1a\) + 3f8: 849861c0 80001234 ldbu.l r6, @\(r7, 0x1234\) + 400: 042061c8 842461c8 ldh.s r6, @\(r7, r8\) -> ldh.s r6, @\(r7\+, r8\) + 408: 042c61c8 842861da ldh.s r6, @\(r7-, r8\) -> ldh.s r6, @\(r7, 0x1a\) + 410: 842861c0 80001234 ldh.l r6, @\(r7, 0x1234\) + 418: 041061c8 841461c8 ldhh.s r6, @\(r7, r8\) -> ldhh.s r6, @\(r7\+, r8\) + 420: 041c61c8 841861da ldhh.s r6, @\(r7-, r8\) -> ldhh.s r6, @\(r7, 0x1a\) + 428: 841861c0 80001234 ldhh.l r6, @\(r7, 0x1234\) + 430: 04a061c8 84a461c8 ldhu.s r6, @\(r7, r8\) -> ldhu.s r6, @\(r7\+, r8\) + 438: 04ac61c8 84a861da ldhu.s r6, @\(r7-, r8\) -> ldhu.s r6, @\(r7, 0x1a\) + 440: 84a861c0 80001234 ldhu.l r6, @\(r7, 0x1234\) + 448: 044061c8 844461c8 ldw.s r6, @\(r7, r8\) -> ldw.s r6, @\(r7\+, r8\) + 450: 044c61c8 844861da ldw.s r6, @\(r7-, r8\) -> ldw.s r6, @\(r7, 0x1a\) + 458: 844861c0 80001234 ldw.l r6, @\(r7, 0x1234\) + 460: 8b48109f 0b401084 mac0 r1, r2, 0x1f <- mac0 r1, r2, r4 + 468: 8b4c109f 0b441084 mac1 r1, r2, 0x1f <- mac1 r1, r2, r4 + 470: 8b58109f 0b501084 macs0 r1, r2, 0x1f <- macs0 r1, r2, r4 + 478: 8b5c109f 0b541084 macs1 r1, r2, 0x1f <- macs1 r1, r2, r4 + 480: 047c004a 8474004a moddec r1, 0xa -> modinc r1, 0xa + 488: 8b68109f 0b601084 msub0 r1, r2, 0x1f <- msub0 r1, r2, r4 + 490: 8b6c109f 0b641084 msub1 r1, r2, 0x1f <- msub1 r1, r2, r4 + 498: 8b08108a 0b001084 mul r1, r2, 0xa <- mul r1, r2, r4 + 4a0: 8b78109f 0b701084 msubs0 r1, r2, 0x1f <- msubs0 r1, r2, r4 + 4a8: 8b7c109f 0b741084 msubs1 r1, r2, 0x1f <- msubs1 r1, r2, r4 + 4b0: 00f00000 00f00000 nop || nop + 4b8: 8a08108a 0a001084 mul2h r1, r2, 0xa <- mul2h r1, r2, r4 + 4c0: 8a48108a 0a401084 mulhxll r1, r2, 0xa <- mulhxll r1, r2, r4 + 4c8: 8a58108a 0a501084 mulhxlh r1, r2, 0xa <- mulhxlh r1, r2, r4 + 4d0: 8a68108a 0a601084 mulhxhl r1, r2, 0xa <- mulhxhl r1, r2, r4 + 4d8: 8a78108a 0a701084 mulhxhh r1, r2, 0xa <- mulhxhh r1, r2, r4 + 4e0: 8b900044 0a108084 mulxs a0, r1, r4 <- mulx2h r8, r2, r4 + 4e8: 8b88108a 0b800044 mulx a1, r2, 0xa <- mulx a0, r1, r4 + 4f0: 8bf8204a 0bf01004 mvfacc r2, a1, 0xa <- mvfacc r1, a0, r4 + 4f8: 8b98108a 0a18808a mulxs a1, r2, 0xa <- mulx2h r8, r2, 0xa + 500: 01e0a080 81e0a1c0 mvfsys r10, pc -> mvfsys r10, rpt_c + 508: 01e0a000 81e0a002 mvfsys r10, psw -> mvfsys r10, pswh + 510: 01e0a001 81e0a003 mvfsys r10, pswl -> mvfsys r10, f0 + 518: 01e0a103 8af01084 mvfsys r10, s -> mvtacc a1, r2, r4 + 520: 00e07280 80e00280 mvtsys rpt_c, r10 -> mvtsys psw, r10 + 528: 00e00282 80e00281 mvtsys pswh, r10 -> mvtsys pswl, r10 + 530: 00e00283 80e03283 mvtsys f0, r10 -> mvtsys f3, r10 + 538: 00e04283 80e05283 mvtsys s, r10 -> mvtsys v, r10 + 540: 00e06283 80e07283 mvtsys va, r10 -> mvtsys c, r10 + 548: 00f00000 83901080 nop -> not r1, r2 + 550: 02901080 83a01084 notfg f1, f2 -> or.s r1, r2, r4 + 558: 03a8109a 00f00000 or.s r1, r2, 0x1a || nop + 560: 83a810b7 8ab1f00d or.l r1, r2, 0xdeadf00d + 568: 02a01084 82a84081 orfg f1, f2, s -> orfg s, f2, 0x1 + 570: 00800000 00f00000 reit || nop + 578: 01801002 00f00000 repeat.s r1, r2 || nop + 580: 81884000 8000dead repeat.l r4, dead \(e42d <start\+0xe42d>\) + 588: 81884037 8ab1f00d repeat.l r4, -21520ff3 \(deadf595 <start\+0xdeadf595>\) + 590: 01a0a001 81a8a200 repeati.s a \(59a <start\+0x59a>\), r1 -> repeati.s a \(59a <start\+0x59a>\), 1000 \(1590 <start\+0x1590>\) + 598: 00f00000 00f00000 nop || nop + 5a0: 03401084 8348108a rot r1, r2, r4 -> rot r1, r2, 0xa + 5a8: 03501084 8358108a rot2h r1, r2, r4 -> rot2h r1, r2, 0xa + 5b0: 8a88108a 0a801084 sat r1, r2, 0xa <- sat r1, r2, r4 + 5b8: 8a98108a 0a901084 sat2h r1, r2, 0xa <- sat2h r1, r2, r4 + 5c0: 8bc8108a 0bc01084 sathl r1, r2, 0xa <- sathl r1, r2, r4 + 5c8: 8bd8108a 0bd01084 sathh r1, r2, 0xa <- sathh r1, r2, r4 + 5d0: 8aa8108a 0aa01084 satz r1, r2, 0xa <- satz r1, r2, r4 + 5d8: 8ab8108a 0ab01084 satz2h r1, r2, 0xa <- satz2h r1, r2, r4 + 5e0: 03001084 8308108a sra r1, r2, r4 -> sra r1, r2, 0xa + 5e8: 03101084 8318108a sra2h r1, r2, r4 -> sra2h r1, r2, 0xa + 5f0: 03601084 8368108a src r1, r2, r4 -> src r1, r2, 0xa + 5f8: 03201084 8328108a srl r1, r2, r4 -> srl r1, r2, 0xa + 600: 03301084 8338108a srl2h r1, r2, r4 -> srl2h r1, r2, 0xa + 608: 053061c8 853461c8 st2h.s r6, @\(r7, r8\) -> st2h.s r6, @\(r7\+, r8\) + 610: 053c61c8 853861da st2h.s r6, @\(r7-, r8\) -> st2h.s r6, @\(r7, 0x1a\) + 618: 853861c0 80001234 st2h.l r6, @\(r7, 0x1234\) + 620: 056061c8 856461c8 st2w.s r6, @\(r7, r8\) -> st2w.s r6, @\(r7\+, r8\) + 628: 056c61c8 856861da st2w.s r6, @\(r7-, r8\) -> st2w.s r6, @\(r7, 0x1a\) + 630: 856861c0 80001234 st2w.l r6, @\(r7, 0x1234\) + 638: 055061c8 855461c8 st4hb.s r6, @\(r7, r8\) -> st4hb.s r6, @\(r7\+, r8\) + 640: 055c61c8 855861da st4hb.s r6, @\(r7-, r8\) -> st4hb.s r6, @\(r7, 0x1a\) + 648: 855861c0 80001234 st4hb.l r6, @\(r7, 0x1234\) + 650: 050061c8 850461c8 stb.s r6, @\(r7, r8\) -> stb.s r6, @\(r7\+, r8\) + 658: 050c61c8 850861da stb.s r6, @\(r7-, r8\) -> stb.s r6, @\(r7, 0x1a\) + 660: 850861c0 80001234 stb.l r6, @\(r7, 0x1234\) + 668: 052061c8 852461c8 sth.s r6, @\(r7, r8\) -> sth.s r6, @\(r7\+, r8\) + 670: 052c61c8 852861da sth.s r6, @\(r7-, r8\) -> sth.s r6, @\(r7, 0x1a\) + 678: 852861c0 80001234 sth.l r6, @\(r7, 0x1234\) + 680: 051061c8 851461c8 sthh.s r6, @\(r7, r8\) -> sthh.s r6, @\(r7\+, r8\) + 688: 051c61c8 851861da sthh.s r6, @\(r7-, r8\) -> sthh.s r6, @\(r7, 0x1a\) + 690: 851861c0 80001234 sthh.l r6, @\(r7, 0x1234\) + 698: 054061c8 854461c8 stw.s r6, @\(r7, r8\) -> stw.s r6, @\(r7\+, r8\) + 6a0: 054c61c8 854861da stw.s r6, @\(r7-, r8\) -> stw.s r6, @\(r7, 0x1a\) + 6a8: 854861c0 80001234 stw.l r6, @\(r7, 0x1234\) + 6b0: 08201083 882b2cda sub.s r1, r2, r3 -> sub.s r50, r51, 0x1a + 6b8: 882b2cf7 8ab1beef sub.l r50, r51, 0xdeadbeef + 6c0: 08301083 883b2cda sub2h.s r1, r2, r3 -> sub2h.s r50, r51, 0x1a + 6c8: 883b2cf7 8ab1beef sub2h.l r50, r51, 0xdeadbeef + 6d0: 08501083 885b2cda subb.s r1, r2, r3 -> subb.s r50, r51, 0x1a + 6d8: 885b2cf7 8ab1beef subb.l r50, r51, 0xdeadbeef + 6e0: 09801083 898b2cda subhlll.s r1, r2, r3 -> subhlll.s r50, r51, 0x1a + 6e8: 898b2cf7 8ab1beef subhlll.l r50, r51, 0xdeadbeef + 6f0: 09901083 899b2cda subhllh.s r1, r2, r3 -> subhllh.s r50, r51, 0x1a + 6f8: 899b2cf7 8ab1beef subhllh.l r50, r51, 0xdeadbeef + 700: 09a01083 89ab2cda subhlhl.s r1, r2, r3 -> subhlhl.s r50, r51, 0x1a + 708: 89ab2cf7 8ab1beef subhlhl.l r50, r51, 0xdeadbeef + 710: 09b01083 89bb2cda subhlhh.s r1, r2, r3 -> subhlhh.s r50, r51, 0x1a + 718: 89bb2cf7 8ab1beef subhlhh.l r50, r51, 0xdeadbeef + 720: 09c01083 89cb2cda subhhll.s r1, r2, r3 -> subhhll.s r50, r51, 0x1a + 728: 89cb2cf7 8ab1beef subhhll.l r50, r51, 0xdeadbeef + 730: 09d01083 89db2cda subhhlh.s r1, r2, r3 -> subhhlh.s r50, r51, 0x1a + 738: 89db2cf7 8ab1beef subhhlh.l r50, r51, 0xdeadbeef + 740: 09e01083 89eb2cda subhhhl.s r1, r2, r3 -> subhhhl.s r50, r51, 0x1a + 748: 89eb2cf7 8ab1beef subhhhl.l r50, r51, 0xdeadbeef + 750: 09f01083 89fb2cda subhhhh.s r1, r2, r3 -> subhhhh.s r50, r51, 0x1a + 758: 89fb2cf7 8ab1beef subhhhh.l r50, r51, 0xdeadbeef + 760: 00900001 00f00000 trap.s r1 || nop + 768: 0098000a 00f00000 trap.s 0xa || nop + 770: 03b01084 83b8108a xor.s r1, r2, r4 -> xor.s r1, r2, 0xa + 778: 83b810b7 8ab1f00d xor.l r1, r2, 0xdeadf00d + 780: 02b01084 82b8110a xorfg f1, f2, s -> xorfg f1, s, 0xa + 788: 00f00000 80f00000 nop -> nop + 790: 00f00000 80f00000 nop -> nop + 798: 00f00000 00f00000 nop || nop + 7a0: 80f00000 00f00000 nop <- nop + 7a8: 03901080 00f00000 not r1, r2 || nop + 7b0: 039020c0 80f00000 not r2, r3 -> nop diff --git a/gas/testsuite/gas/d30v/inst.s b/gas/testsuite/gas/d30v/inst.s new file mode 100644 index 00000000000..ee6611eb117 --- /dev/null +++ b/gas/testsuite/gas/d30v/inst.s @@ -0,0 +1,504 @@ +# test all instructions + +start: + abs r21,r42 + + add r1,r2,r3 + add r50,r51,0x1a + add r50,r51,0xdeadbeef + + add2h r1,r2,r3 + add2h r50,r51,0x1a + add2h r50,r51,0xdeadbeef + + addc r1,r2,r3 + addc r50,r51,0x1a + addc r50,r51,0xdeadbeef + + addhlll r1,r2,r3 + addhlll r50,r51,0x1a + addhlll r50,r51,0xdeadbeef + + addhllh r1,r2,r3 + addhllh r50,r51,0x1a + addhllh r50,r51,0xdeadbeef + + addhlhl r1,r2,r3 + addhlhl r50,r51,0x1a + addhlhl r50,r51,0xdeadbeef + + addhlhh r1,r2,r3 + addhlhh r50,r51,0x1a + addhlhh r50,r51,0xdeadbeef + + addhhll r1,r2,r3 + addhhll r50,r51,0x1a + addhhll r50,r51,0xdeadbeef + + addhhlh r1,r2,r3 + addhhlh r50,r51,0x1a + addhhlh r50,r51,0xdeadbeef + + addhhhl r1,r2,r3 + addhhhl r50,r51,0x1a + addhhhl r50,r51,0xdeadbeef + + addhhhh r1,r2,r3 + addhhhh r50,r51,0x1a + addhhhh r50,r51,0xdeadbeef + + adds r1,r2,r3 + adds r50,r51,0x1a + adds r50,r51,0xdeadbeef + + adds2h r1,r2,r3 + adds2h r50,r51,0x1a + adds2h r50,r51,0xdeadbeef + + and r1,r2,r3 + and r50,r51,0x1a + and r50,r51,0xdeadbeef + + andfg f0,f1,f2 + andfg f3,f4,5 + + avg r1,r2,r3 + avg r4,r5,6 + avg r50,r51,0xdeadbeef + + avg2h r1,r2,r3 + avg2h r4,r5,6 + avg2h r50,r51,0xdeadbeef + + bclr r1,r2,r3 + bclr r4,r5,6 + + bnot r1,r2,r3 + bnot r5,r51,6 + + bra r41 + bra 0x40 + bra 0xf00d + + bratnz r41,r42 + bratnz r1,0xf00d + bratnz r1,0xdeadf00d + + bratzr r41,r42 + bratzr r1,0xf00d + bratzr r1,0xdeadf00d + + bset r1,r2,r3 + bset r5,r51,6 + + bsr r41 + bsr 0xf00d + bsr 0xdeadf00d + + bsrtnz r41,r42 + bsrtnz r1,0xf00d + bsrtnz r1,0xdeadf00d + + bsrtzr r41,r42 + bsrtzr r1,0xf00d + bsrtzr r1,0xdeadf00d + + btst f1,r2,r3 + btst f5,r51,6 + + cmpeq f0,r3,r1 + cmpne f1,r20,r21 + cmpgt f2,r31,r32 + cmpge f3,r3,r4 + cmplt f4,r3,r4 + cmple f5,r3,r4 + cmpps f6,r3,r4 + cmpng f7,r3,r4 + + cmpugt f2,r31,r32 + cmpuge f3,r3,r4 + cmpult f4,r3,r4 + cmpule f5,r3,r4 + + dbra r1,r8 + dbra r1,0x100 + dbra r1,0xdeadf00d + + dbrai 0x10,r31 + dbrai 0x10,0x100 + dbrai 0x10,0xdeadf00d + + dbsr r1,r8 || nop + dbsr r1,0x100 || nop + dbsr r1,0xdeadf00d + + dbsri 0x20,r31 || nop + dbsri 0x20,0x100 || nop + dbsri 0x20,0xdeadf00d + + djmp r1,r32 + djmp r1,0xf00d + djmp r1,0xdeadf00d + + djmpi 0x30,r32 + djmpi 0x30,0xf00d + djmpi 0x30,0xdeadf00d + + djsr r1,r32 + djsr r1,0xf00d + djsr r1,0xdeadf00d + + djsri 0x10,r32 + djsri 0x20,0xf00d + djsri 0x40,0xdeadf00d + + jmp r41 + jmp 0xf00d + jmp 0xdeadf00d + + jmptnz r41,r42 + jmptnz r1,0xf00d + jmptnz r1,0xdeadf00d + + jmptzr r41,r42 + jmptzr r1,0xf00d + jmptzr r1,0xdeadf00d + + joinll r1,r2,r4 + joinll r1,r2,0xf + joinll r1,r2,0xdeadf00d + + joinlh r1,r2,r4 + joinlh r1,r2,0xf + joinlh r1,r2,0xdeadf00d + + joinhl r1,r2,r4 + joinhl r1,r2,0xf + joinhl r1,r2,0xdeadf00d + + joinhh r1,r2,r4 + joinhh r1,r2,0xf + joinhh r1,r2,0xdeadf00d + + jsr r41 + jsr 0xf00d + jsr 0xdeadf00d + + jsrtnz r41,r42 + jsrtnz r1,0xf00d + jsrtnz r1,0xdeadf00d + + jsrtzr r41,r42 + jsrtzr r1,0xf00d + jsrtzr r1,0xdeadf00d + + ld2h r6,@(r7,r8) + ld2h r6,@(r7+,r8) + ld2h r6,@(r7-,r8) + ld2h r6,@(r7,0x1a) + ld2h r6,@(r7,0x1234) + + ld2w r6,@(r7,r8) + ld2w r6,@(r7+,r8) + ld2w r6,@(r7-,r8) + ld2w r6,@(r7,0x1a) + ld2w r6,@(r7,0x1234) + + ld4bh r6,@(r7,r8) + ld4bh r6,@(r7+,r8) + ld4bh r6,@(r7-,r8) + ld4bh r6,@(r7,0x1a) + ld4bh r6,@(r7,0x1234) + + ld4bhu r6,@(r7,r8) + ld4bhu r6,@(r7+,r8) + ld4bhu r6,@(r7-,r8) + ld4bhu r6,@(r7,0x1a) + ld4bhu r6,@(r7,0x1234) + + ldb r6,@(r7,r8) + ldb r6,@(r7+,r8) + ldb r6,@(r7-,r8) + ldb r6,@(r7,0x1a) + ldb r6,@(r7,0x1234) + + ldbu r6,@(r7,r8) + ldbu r6,@(r7+,r8) + ldbu r6,@(r7-,r8) + ldbu r6,@(r7,0x1a) + ldbu r6,@(r7,0x1234) + + ldh r6,@(r7,r8) + ldh r6,@(r7+,r8) + ldh r6,@(r7-,r8) + ldh r6,@(r7,0x1a) + ldh r6,@(r7,0x1234) + + ldhh r6,@(r7,r8) + ldhh r6,@(r7+,r8) + ldhh r6,@(r7-,r8) + ldhh r6,@(r7,0x1a) + ldhh r6,@(r7,0x1234) + + ldhu r6,@(r7,r8) + ldhu r6,@(r7+,r8) + ldhu r6,@(r7-,r8) + ldhu r6,@(r7,0x1a) + ldhu r6,@(r7,0x1234) + + ldw r6,@(r7,r8) + ldw r6,@(r7+,r8) + ldw r6,@(r7-,r8) + ldw r6,@(r7,0x1a) + ldw r6,@(r7,0x1234) + + mac0 r1,r2,r4 + mac0 r1,r2,0x1f + mac1 r1,r2,r4 + mac1 r1,r2,0x1f + + macs0 r1,r2,r4 + macs0 r1,r2,0x1f + macs1 r1,r2,r4 + macs1 r1,r2,0x1f + + moddec r1,0xa + + modinc r1,0xa + + msub0 r1,r2,r4 + msub0 r1,r2,0x1f + msub1 r1,r2,r4 + msub1 r1,r2,0x1f + + mul r1,r2,r4 + mul r1,r2,0xa + + msubs0 r1,r2,r4 + msubs0 r1,r2,0x1f + msubs1 r1,r2,r4 + msubs1 r1,r2,0x1f + + mul2h r1,r2,r4 + mul2h r1,r2,0xa + + mulhxll r1,r2,r4 + mulhxll r1,r2,0xa + + mulhxlh r1,r2,r4 + mulhxlh r1,r2,0xa + + mulhxhl r1,r2,r4 + mulhxhl r1,r2,0xa + + mulhxhh r1,r2,r4 + mulhxhh r1,r2,0xa + + mulx2h r8,r2,r4 + mulxs a0,r1,r4 + + mulx a0,r1,r4 + mulx a1,r2,0xa + + mvfacc r1,a0,r4 + mvfacc r2,a1,0xa + + mulx2h r8,r2,0xa + mulxs a1,r2,0xa + + mvfsys r10,pc + mvfsys r10,rpt_c + mvfsys r10,psw + mvfsys r10,pswh + mvfsys r10,pswl + mvfsys r10,f0 + mvfsys r10,S + + mvtacc a1,r2,r4 + + mvtsys rpt_c, r10 + mvtsys psw, r10 + mvtsys pswh, r10 + mvtsys pswl, r10 + mvtsys f0, r10 + mvtsys f3, r10 + mvtsys S, r10 + mvtsys V, r10 + mvtsys VA, r10 + mvtsys C, r10 + + nop + + not r1,r2 + + notfg f1,f2 + + or r1,r2,r4 + or r1,r2,0x1a + or r1,r2,0xdeadf00d + + orfg f1,f2,f4 + orfg f4,f2,0x1 + + reit + + repeat r1,r2 + repeat r4,0xdead + repeat r4,0xdeadf00d + + repeati 0xa,r1 + repeati 0xa,0x1001 + + nop || nop + + rot r1,r2,r4 + rot r1,r2,0xa + + rot2h r1,r2,r4 + rot2h r1,r2,0xa + + sat r1,r2,r4 + sat r1,r2,0xa + + sat2h r1,r2,r4 + sat2h r1,r2,0xa + + sathl r1,r2,r4 + sathl r1,r2,0xa + + sathh r1,r2,r4 + sathh r1,r2,0xa + + satz r1,r2,r4 + satz r1,r2,0xa + + satz2h r1,r2,r4 + satz2h r1,r2,0xa + + sra r1,r2,r4 + sra r1,r2,0xa + + sra2h r1,r2,r4 + sra2h r1,r2,0xa + + src r1,r2,r4 + src r1,r2,0xa + + srl r1,r2,r4 + srl r1,r2,0xa + + srl2h r1,r2,r4 + srl2h r1,r2,0xa + + + st2h r6,@(r7,r8) + st2h r6,@(r7+,r8) + st2h r6,@(r7-,r8) + st2h r6,@(r7,0x1a) + st2h r6,@(r7,0x1234) + + st2w r6,@(r7,r8) + st2w r6,@(r7+,r8) + st2w r6,@(r7-,r8) + st2w r6,@(r7,0x1a) + st2w r6,@(r7,0x1234) + + st4hb r6,@(r7,r8) + st4hb r6,@(r7+,r8) + st4hb r6,@(r7-,r8) + st4hb r6,@(r7,0x1a) + st4hb r6,@(r7,0x1234) + + stb r6,@(r7,r8) + stb r6,@(r7+,r8) + stb r6,@(r7-,r8) + stb r6,@(r7,0x1a) + stb r6,@(r7,0x1234) + + sth r6,@(r7,r8) + sth r6,@(r7+,r8) + sth r6,@(r7-,r8) + sth r6,@(r7,0x1a) + sth r6,@(r7,0x1234) + + sthh r6,@(r7,r8) + sthh r6,@(r7+,r8) + sthh r6,@(r7-,r8) + sthh r6,@(r7,0x1a) + sthh r6,@(r7,0x1234) + + stw r6,@(r7,r8) + stw r6,@(r7+,r8) + stw r6,@(r7-,r8) + stw r6,@(r7,0x1a) + stw r6,@(r7,0x1234) + + sub r1,r2,r3 + sub r50,r51,0x1a + sub r50,r51,0xdeadbeef + + sub2h r1,r2,r3 + sub2h r50,r51,0x1a + sub2h r50,r51,0xdeadbeef + + subb r1,r2,r3 + subb r50,r51,0x1a + subb r50,r51,0xdeadbeef + + subhlll r1,r2,r3 + subhlll r50,r51,0x1a + subhlll r50,r51,0xdeadbeef + + subhllh r1,r2,r3 + subhllh r50,r51,0x1a + subhllh r50,r51,0xdeadbeef + + subhlhl r1,r2,r3 + subhlhl r50,r51,0x1a + subhlhl r50,r51,0xdeadbeef + + subhlhh r1,r2,r3 + subhlhh r50,r51,0x1a + subhlhh r50,r51,0xdeadbeef + + subhhll r1,r2,r3 + subhhll r50,r51,0x1a + subhhll r50,r51,0xdeadbeef + + subhhlh r1,r2,r3 + subhhlh r50,r51,0x1a + subhhlh r50,r51,0xdeadbeef + + subhhhl r1,r2,r3 + subhhhl r50,r51,0x1a + subhhhl r50,r51,0xdeadbeef + + subhhhh r1,r2,r3 + subhhhh r50,r51,0x1a + subhhhh r50,r51,0xdeadbeef + + trap r1 + trap 0xa + + xor r1,r2,r4 + xor r1,r2,0xa + xor r1,r2,0xdeadf00d + + xorfg f1,f2,f4 + xorfg f1,f4,0xa + +# VLIW syntax test + nop + nop + nop -> nop + nop || nop + nop <- nop + +# try changing sections + not r1,r2 + .section .foo + add r10,r12,6 + .text + not r2,r3 + nop +
\ No newline at end of file diff --git a/gas/testsuite/gas/d30v/label-debug.d b/gas/testsuite/gas/d30v/label-debug.d new file mode 100644 index 00000000000..e429f81e0f4 --- /dev/null +++ b/gas/testsuite/gas/d30v/label-debug.d @@ -0,0 +1,24 @@ +#objdump: -ldr +#name: D30V debug (-g) test +#as: -g + +.*: +file format elf32-d30v + +Disassembly of section .text: + +00000000 <_abc-0x18>: +.*label-debug.s:4 + 0: 10080003 00f00000 bra.s\/tx 18 \(18 <_abc>\) \|\| nop +.*label-debug.s:5 + 8: 00f00000 00f00000 nop || nop + 10: 0e000004 00f00000 .long 0xe000004 || nop + +00000018 <_abc>: +.*label-debug.s:8 + 18: 00f00000 00f00000 nop || nop +.*label-debug.s:9 + 20: 00f00000 00f00000 nop || nop +.*label-debug.s:10 + 28: 00f00000 00f00000 nop || nop +.*label-debug.s:11 + 30: 00f00000 00f00000 nop || nop diff --git a/gas/testsuite/gas/d30v/label-debug.s b/gas/testsuite/gas/d30v/label-debug.s new file mode 100644 index 00000000000..9640aa49bd7 --- /dev/null +++ b/gas/testsuite/gas/d30v/label-debug.s @@ -0,0 +1,11 @@ +# labels should be aligned on 8-byte boundries + + .text + bra.s/tx _abc || nop + nop || nop + .word 0x0e000004 +_abc: + nop + nop + nop + nop diff --git a/gas/testsuite/gas/d30v/label.d b/gas/testsuite/gas/d30v/label.d new file mode 100644 index 00000000000..66cfcdab740 --- /dev/null +++ b/gas/testsuite/gas/d30v/label.d @@ -0,0 +1,16 @@ +#objdump: -dr +#name: D30V label alignment test +#as: + +.*: +file format elf32-d30v + +Disassembly of section .text: + +00000000 <_abc-0x18>: + 0: 10080003 00f00000 bra.s/tx 18 (18 <_abc>) || nop + 8: 00f00000 00f00000 nop || nop + 10: 0e000004 00f00000 .long 0xe000004 || nop + +00000018 <_abc>: + 18: 00f00000 80f00000 nop -> nop + 20: 00f00000 80f00000 nop -> nop diff --git a/gas/testsuite/gas/d30v/label.s b/gas/testsuite/gas/d30v/label.s new file mode 100644 index 00000000000..9640aa49bd7 --- /dev/null +++ b/gas/testsuite/gas/d30v/label.s @@ -0,0 +1,11 @@ +# labels should be aligned on 8-byte boundries + + .text + bra.s/tx _abc || nop + nop || nop + .word 0x0e000004 +_abc: + nop + nop + nop + nop diff --git a/gas/testsuite/gas/d30v/mul.d b/gas/testsuite/gas/d30v/mul.d new file mode 100644 index 00000000000..04e0a550b15 --- /dev/null +++ b/gas/testsuite/gas/d30v/mul.d @@ -0,0 +1,20 @@ +#objdump: -dr +#name: D30V alignment test +#as: -WO + +.*: +file format elf32-d30v + +Disassembly of section .text: + +00000000 <.text>: + 0: 8a105187 0a1020c4 mulx2h r5, r6, r7 <- mulx2h r2, r3, r4 + 8: 00f00000 0a10824a nop || mulx2h r8, r9, r10 + 10: 00f00000 0a10b30d nop || mulx2h r11, r12, r13 + 18: 8a111493 0a10e3d0 mulx2h r17, r18, r19 <- mulx2h r14, r15, r16 + 20: 8a117619 0a114556 mulx2h r23, r24, r25 <- mulx2h r20, r21, r22 + 28: 8b01d79f 0a11a6dc mul r29, r30, r31 <- mulx2h r26, r27, r28 + 30: 8b005187 0b0020c4 mul r5, r6, r7 <- mul r2, r3, r4 + 38: 8a10b30d 0a10824a mulx2h r11, r12, r13 <- mulx2h r8, r9, r10 + 40: 80f00000 0b00e3d0 nop <- mul r14, r15, r16 + 48: 00f00000 0a111493 nop || mulx2h r17, r18, r19 + 50: 8b017619 0a114556 mul r23, r24, r25 <- mulx2h r20, r21, r22 diff --git a/gas/testsuite/gas/d30v/mul.s b/gas/testsuite/gas/d30v/mul.s new file mode 100644 index 00000000000..fe678595067 --- /dev/null +++ b/gas/testsuite/gas/d30v/mul.s @@ -0,0 +1,19 @@ +# One of the rule on restricted sequence is consecutive IU instruction +# IU: MUL, MAC, MACS, MSUB, MSUBS (a) +# IU: MULHXpp, MULX2H, MUL2H (b) +# This means that instructions in group (a) and in (b) should not be executed +# in IU in consecutive cycles in the order (a)->(b). It does neither prohibit +# executions in the reverse order (b)-> (a) nor consecutive execution of +# group (a)->(a) or (b)->(b) + + mulx2h r5,r6,r7 <- mulx2h r2,r3,r4 + nop || mulx2h r8,r9,r10 + nop || mulx2h r11,r12,r13 + mulx2h r14,r15,r16 + mulx2h r17,r18,r19 + mulx2h r23,r24,r25 <- mulx2h r20,r21,r22 + mul r29,r30,r31 <- mulx2h r26,r27,r28 + mul r5, r6, r7 <- mul r2, r3, r4 + mulx2h r11, r12, r13 <- mulx2h r8, r9, r10 + mulx2h r17, r18, r19 <- mul r14, r15, r16 + mul r23, r24, r25 <- mulx2h r20, r21, r22 diff --git a/gas/testsuite/gas/d30v/opt.d b/gas/testsuite/gas/d30v/opt.d new file mode 100644 index 00000000000..b4bfa9c12fd --- /dev/null +++ b/gas/testsuite/gas/d30v/opt.d @@ -0,0 +1,89 @@ +#objdump: -dr +#name: D30V optimization test +#as: -O + +.*: +file format elf32-d30v + +Disassembly of section .text: + +00000000 <start>: + 0: 08801080 08803100 abs r1, r2 || abs r3, r4 + 8: 02900100 02901080 notfg f0, s || notfg f1, f2 + 10: 08801080 02901080 abs r1, r2 || notfg f1, f2 + 18: 08001083 82907000 add.s r1, r2, r3 -> notfg c, f0 + 20: 08001083 829001c0 add.s r1, r2, r3 -> notfg f0, c + 28: 00080000 00f00000 bra.s 0 \(28 <start\+0x28>\) || nop + 30: 08801080 88801080 abs r1, r2 -> abs r1, r2 + 38: 00080000 00f00000 bra.s 0 \(38 <start\+0x38>\) || nop + 40: 002bffff 00f00000 bsr.s -8 \(38 <start\+0x38>\) || nop + 48: 08801080 88801080 abs r1, r2 -> abs r1, r2 + 50: 00280000 08801080 bsr.s 0 \(50 <start\+0x50>\) || abs r1, r2 + 58: 04001083 85007209 ldb.s r1, @\(r2, r3\) -> stb.s r7, @\(r8, r9\) + 60: 05007209 84001083 stb.s r7, @\(r8, r9\) -> ldb.s r1, @\(r2, r3\) + 68: 04007209 84001083 ldb.s r7, @\(r8, r9\) -> ldb.s r1, @\(r2, r3\) + 70: 05007209 85001083 stb.s r7, @\(r8, r9\) -> stb.s r1, @\(r2, r3\) + 78: 080030c6 854820c0 add.s r3, r3, r6 -> stw.s r2, @\(r3, 0x0\) + 80: 02c28105 90180000 cmple.s f0, r4, r5 -> jmp.s/tx 0 <start> + 88: 02c28105 a0180000 cmple.s f0, r4, r5 -> jmp.s/fx 0 <start> + 90: 30180000 02c28105 jmp.s/xt 0 <start> || cmple.s f0, r4, r5 + 98: 40180000 02c28105 jmp.s/xf 0 <start> || cmple.s f0, r4, r5 + a0: 02c28105 d0180000 cmple.s f0, r4, r5 -> jmp.s/tt 0 <start> + a8: 02c28105 e0180000 cmple.s f0, r4, r5 -> jmp.s/tf 0 <start> + b0: 10180000 02c29105 jmp.s/tx 0 <start> || cmple.s f1, r4, r5 + b8: 02c29105 b0180000 cmple.s f1, r4, r5 -> jmp.s/xt 0 <start> + c0: 08084001 82c28105 add.s r4, r0, 0x1 -> cmple.s f0, r4, r5 + c8: 08084001 02c280c5 add.s r4, r0, 0x1 || cmple.s f0, r3, r5 + d0: 04604006 886054d4 ld2w.s r4, @\(r0, r6\) -> adds.s r5, r19, r20 + d8: 04604006 88603154 ld2w.s r4, @\(r0, r6\) -> adds.s r3, r5, r20 + e0: 04604006 086064d4 ld2w.s r4, @\(r0, r6\) || adds.s r6, r19, r20 + e8: 04604006 086074d4 ld2w.s r4, @\(r0, r6\) || adds.s r7, r19, r20 + f0: 04604006 08607014 ld2w.s r4, @\(r0, r6\) || adds.s r7, r0, r20 + f8: 05604006 086054d4 st2w.s r4, @\(r0, r6\) || adds.s r5, r19, r20 + 100: 05604006 08603154 st2w.s r4, @\(r0, r6\) || adds.s r3, r5, r20 + 108: 05604006 086064d4 st2w.s r4, @\(r0, r6\) || adds.s r6, r19, r20 + 110: 05604006 086074d4 st2w.s r4, @\(r0, r6\) || adds.s r7, r19, r20 + 118: 05604006 08607014 st2w.s r4, @\(r0, r6\) || adds.s r7, r0, r20 + 120: 0560a0c4 85628aec st2w.s r10, @\(r3, r4\) -> st2w.s r40, @\(r43, r44\) + 128: 05401083 84429aab stw.s r1, @\(r2, r3\) -> ldw.s r41, @\(r42, r43\) + 130: 04401083 84029aab ldw.s r1, @\(r2, r3\) -> ldb.s r41, @\(r42, r43\) + 138: 0444418b 88689182 ldw.s r4, @\(r6\+, r11\) -> adds.s r9, r6, 0x2 + 140: 044c418b 08689182 ldw.s r4, @\(r6-, r11\) || adds.s r9, r6, 0x2 + 148: 054c418b 88689182 stw.s r4, @\(r6-, r11\) -> adds.s r9, r6, 0x2 + 150: 0440418b 08689182 ldw.s r4, @\(r6, r11\) || adds.s r9, r6, 0x2 + 158: 0440418b 08689182 ldw.s r4, @\(r6, r11\) || adds.s r9, r6, 0x2 + 160: 00180000 00f00000 jmp.s 0 <start> || nop + 168: 00380000 08801080 jsr.s 0 <start> || abs r1, r2 + 170: 08801080 00f00000 abs r1, r2 || nop + 178: 00080000 00f00000 bra.s 0 \(178 <start\+0x178>\) || nop + 180: 00280000 08801080 bsr.s 0 \(180 <start\+0x180>\) || abs r1, r2 + 188: 08801080 00f00000 abs r1, r2 || nop + +00000190 <label1>: + 190: 05602083 89004146 st2w.s r2, @\(r2, r3\) -> addhlll.s r4, r5, r6 + +00000198 <label2>: + 198: 05508209 8990a2cc st4hb.s r8, @\(r8, r9\) -> subhllh.s r10, r11, r12 + +000001a0 <label3>: + 1a0: 0460e38f 8a610452 ld2w.s r14, @\(r14, r15\) -> mulhxhl r16, r17, r18 + +000001a8 <label4>: + 1a8: 04413515 8a1165d8 ldw.s r19, @\(r20, r21\) -> mulx2h r22, r23, r24 + +000001b0 <label5>: + 1b0: 0421969b 8a01c75e ldh.s r25, @\(r26, r27\) -> mul2h r28, r29, r30 + +000001b8 <label6>: + 1b8: 80f00000 0b001083 nop <- mul r1, r2, r3 + 1c0: 08007209 0a404146 add.s r7, r8, r9 || mulhxll r4, r5, r6 + +000001c8 <label7>: + 1c8: 04405180 0b0020c4 ldw.s r5, @\(r6, r0\) || mul r2, r3, r4 + 1d0: 80f00000 0b007209 nop <- mul r7, r8, r9 + 1d8: 0440a2c0 00f00000 ldw.s r10, @\(r11, r0\) || nop + 1e0: 80f00000 0b00c34e nop <- mul r12, r13, r14 + 1e8: 0440f400 0b4420c4 ldw.s r15, @\(r16, r0\) || mac1 r2, r3, r4 + 1f0: 00f00000 00f00000 nop || nop + 1f8: 04405180 00f00000 ldw.s r5, @\(r6, r0\) || nop + 200: 80f00000 0b407209 nop <- mac0 r7, r8, r9 + 208: 0440a2c0 8440a2c0 ldw.s r10, @\(r11, r0\) -> ldw.s r10, @\(r11, r0\) diff --git a/gas/testsuite/gas/d30v/opt.s b/gas/testsuite/gas/d30v/opt.s new file mode 100644 index 00000000000..573330027ec --- /dev/null +++ b/gas/testsuite/gas/d30v/opt.s @@ -0,0 +1,216 @@ +# D30V parallel optimization test +# assemble with "-O" + + .text +start: + abs r1,r2 + abs r3,r4 + + notfg f0,f4 + notfg f1,f2 + + abs r1,r2 + notfg f1,f2 + +# both change C flag + add r1,r2,r3 + notfg C,f0 + +# one uses and one changes C flag + add r1,r2,r3 + notfg f0,C + + bra . + abs r1,r2 + + abs r1,r2 + bra . + + bsr . + abs r1,r2 + + abs r1,r2 + abs r1,r2 + bsr . + + ldb r1,@(r2,r3) + stb r7,@(r8,r9) + + stb r7,@(r8,r9) + ldb r1,@(r2,r3) + + ldb r7,@(r8,r9) + ldb r1,@(r2,r3) + + stb r7,@(r8,r9) + stb r1,@(r2,r3) + + add r3, r3, r6 + stw r2, @(r3, 0) + +# should be serial because of conditional execution + cmple f0,r4,r5 + jmp/tx 0x0 + + cmple f0,r4,r5 + jmp/fx 0x0 + + cmple f0,r4,r5 + jmp/xt 0x0 + + cmple f0,r4,r5 + jmp/xf 0x0 + + cmple f0,r4,r5 + jmp/tt 0x0 + + cmple f0,r4,r5 + jmp/tf 0x0 + + cmple f1,r4,r5 + jmp/tx 0x0 + + cmple f1,r4,r5 + jmp/xt 0x0 + + # serial because of the r4 dependency + add r4, r0, 1 + cmple f0, r4, r5 + + # parallel + add r4, r0, 1 + cmple f0, r3, r5 + + # serial because ld2w loads r5 + ld2w r4,@(r0,r6) + adds r5,r19,r20 + + # serial because ld2w loads r5 + ld2w r4,@(r0,r6) + adds r3,r5,r20 + + # parallel even though ld2w uses r6 and adds changes it + ld2w r4,@(r0,r6) + adds r6,r19,r20 + + # parallel + ld2w r4,@(r0,r6) + adds r7,r19,r20 + + # parallel + ld2w r4,@(r0,r6) + adds r7,r0,r20 + + # parallel even though st2w uses r5 and adds modifies it + st2w r4,@(r0,r6) + adds r5,r19,r20 + + # parallel, both use but don't modify r5 + st2w r4,@(r0,r6) + adds r3,r5,r20 + + # parallel even though st2w uses r6 and adds changes it + st2w r4,@(r0,r6) + adds r6,r19,r20 + + # parallel + st2w r4,@(r0,r6) + adds r7,r19,r20 + + # parallel + st2w r4,@(r0,r6) + adds r7,r0,r20 + +# test memory dependencies + + # always serial because one could overwrite the other + st2w r10,@(r3,r4) + st2w r40,@(r43,r44) + + # always serial + stw r1,@(r2,r3) + ldw r41,@(r42,r43) + + # reads can happen in parallel but the current architecture + # doesn't support it + ldw r1,@(r2,r3) + ldb r41,@(r42,r43) + +# test post increment and decrement dependencies + + # serial + ldw r4,@(r6+,r11) + adds r9,r6,2 + + # parallel, modification to r6 happens last + adds r9,r6,2 + ldw r4,@(r6-,r11) + + # serial + stw r4,@(r6-,r11) + adds r9,r6,2 + + # parallel + ldw r4,@(r6,r11) + adds r9,r6,2 + + # parallel + adds r9,r6,2 + ldw r4,@(r6,r11) + +# if the first instruction is a jmp, don't parallelize + jmp 0 + abs r1,r2 + + jsr 0 + abs r1,r2 + + .align 3 + + bra 0 + abs r1,r2 + + bsr 0 + abs r1,r2 + +# Explicitly prohibited from parallel execution. +# The labels are here to prevent instruction pairs +# from being merged with following pairs. + +label1: + st2w r2, @(r2, r3) + addhlll r4, r5, r6 +label2: + st4hb r8, @(r8, r9) + subhllh r10, r11, r12 +label3: + ld2w r14, @(r14, r15) + mulhxhl r16, r17, r18 +label4: + ldw r19, @(r20, r21) + mulx2h r22, r23, r24 +label5: + ldh r25, @(r26, r27) + mul2h r28, r29, r30 + +# Insertion of NOPs required to prevent pipeline clashes. + +label6: + mul r1,r2,r3 + mulhxll r4,r5,r6 + add r7, r8, r9 +label7: + + mul r2,r3,r4 + ldw r5, @(r6,r0) + + ldw r10, @(r11, r0) <- mul r7,r8,r9 + + mul r12,r13,r14 -> ldw r15, @(r16, r0) + + mac1 r2,r3,r4 + ldw r5, @(r6,r0) + + ldw r10, @(r11, r0) <- mac0 r7,r8,r9 + ldw r10, @(r11, r0) + diff --git a/gas/testsuite/gas/d30v/reloc.d b/gas/testsuite/gas/d30v/reloc.d new file mode 100644 index 00000000000..1de2780b483 --- /dev/null +++ b/gas/testsuite/gas/d30v/reloc.d @@ -0,0 +1,93 @@ +#objdump: -dr +#name: D30V relocation test +#as: + +.*: +file format elf32-d30v + +Disassembly of section .text: + +00000000 <start>: + 0: 88082000 80000028 add.l r2, r0, 0x28 + 0: R_D30V_32 .text + 8: 88084000 80000000 add.l r4, r0, 0x0 + 8: R_D30V_32 .data + 10: 88084000 80000006 add.l r4, r0, 0x6 + 10: R_D30V_32 .data + 18: 88084000 80000000 add.l r4, r0, 0x0 + 18: R_D30V_32 unk + 20: 80080000 80000018 bra.l 18 \(38 <cont>\) + +00000028 <hello>: + 28: 48656c6c 6f20576f .long 0x48656c6c || .long 0x6f20576f + 30: 726c640a 00f00000 .long 0x726c640a || nop + +00000038 <cont>: + 38: 80180000 80000048 jmp.l 48 <cont2> + 38: R_D30V_32 .text + 40: 088020c0 00f00000 abs r2, r3 || nop + +00000048 <cont2>: + 48: 000bfff7 00f00000 bra.s -48 \(0 <start>\) || nop + 50: 00080205 00f00000 bra.s 1028 \(1078 <exit>\) || nop + 58: 00180000 00f00000 jmp.s 0 <start> || nop + 60: 006c1ffb 00f00000 bsrtnz.s r1, -28 \(38 <cont>\) || nop + 68: 006c1ffa 00f00000 bsrtnz.s r1, -30 \(38 <cont>\) || nop + 70: 004c1ff9 00f00000 bratnz.s r1, -38 \(38 <cont>\) || nop + 78: 004c1ff8 00f00000 bratnz.s r1, -40 \(38 <cont>\) || nop + 80: 005c1007 00f00000 jmptnz.s r1, 38 <cont> || nop + 80: R_D30V_15 .text + 88: 006c11f1 00f00000 bsrtnz.s r1, f88 \(1010 <foo>\) || nop + 90: 005c1000 00f00000 jmptnz.s r1, 0 <start> || nop + 90: R_D30V_15 unk + 98: 006c1000 00f00000 bsrtnz.s r1, 0 \(98 <cont2\+0x50>\) || nop + 98: R_D30V_15_PCREL unk + a0: 805c1000 80000000 jmptnz.l r1, 0 <start> + a0: R_D30V_32 unk + a8: 806c1000 80000000 bsrtnz.l r1, 0 \(a8 <cont2\+0x60>\) + a8: R_D30V_32_PCREL unk + b0: 000801ec 00f00000 bra.s f60 \(1010 <foo>\) || nop + b8: 80080000 80000f58 bra.l f58 \(1010 <foo>\) + c0: 000bffe8 00f00000 bra.s -c0 \(0 <start>\) || nop + c8: 80180000 80000000 jmp.l 0 <start> + c8: R_D30V_32 .text + d0: 80180000 80000000 jmp.l 0 <start> + d0: R_D30V_32 .text + d8: 00180000 00f00000 jmp.s 0 <start> || nop + d8: R_D30V_21 .text + e0: 00180202 00f00000 jmp.s 1010 <foo> || nop + e0: R_D30V_21 .text + e8: 000bffe3 00f00000 bra.s -e8 \(0 <start>\) || nop + f0: 80080000 80000000 bra.l 0 \(f0 <cont2\+0xa8>\) + f0: R_D30V_32_PCREL unknown + f8: 80180000 80000000 jmp.l 0 <start> + f8: R_D30V_32 unknown + 100: 00180000 00f00000 jmp.s 0 <start> || nop + 100: R_D30V_21 unknown + 108: 00080000 00f00000 bra.s 0 \(108 <cont2\+0xc0>\) || nop + 108: R_D30V_21_PCREL unknown + ... + +00001010 <foo>: + 1010: 08001000 00f00000 add.s r1, r0, r0 || nop + 1018: 846bc000 80001070 ld2w.l r60, @\(r0, 0x1070\) + 1018: R_D30V_32 .text + 1020: 0803e000 8028000b add.s r62, r0, r0 -> bsr.s 58 \(1078 <exit>\) + 1028: 002bfffd 00f00000 bsr.s -18 \(1010 <foo>\) || nop + 1030: 000bfe03 00f00000 bra.s -fe8 \(48 <cont2>\) || nop + 1038: 000bfe02 00f00000 bra.s -ff0 \(48 <cont2>\) || nop + 1040: 00280007 00f00000 bsr.s 38 \(1078 <exit>\) || nop + 1048: 0018020f 00f00000 jmp.s 1078 <exit> || nop + 1048: R_D30V_21 .text + 1050: 0018020f 00f00000 jmp.s 1078 <exit> || nop + 1050: R_D30V_21 .text + 1058: 0018020f 00f00000 jmp.s 1078 <exit> || nop + 1058: R_D30V_21 .text + 1060: 80280000 80000018 bsr.l 18 \(1078 <exit>\) + 1068: 80180000 80001078 jmp.l 1078 <exit> + 1068: R_D30V_32 .text + +00001070 <longzero>: + ... + +00001078 <exit>: + 1078: 0010003e 00f00000 jmp.s r62 || nop diff --git a/gas/testsuite/gas/d30v/reloc.s b/gas/testsuite/gas/d30v/reloc.s new file mode 100644 index 00000000000..2a99bf9447e --- /dev/null +++ b/gas/testsuite/gas/d30v/reloc.s @@ -0,0 +1,68 @@ +# D30V relocation test + + .text +start: + add r2, r0, hello + add r4, r0, bar + add r4, r0, bar2 + add r4, r0, unk + bra cont +hello: .ascii "Hello World\n" + .align 3 +cont: jmp cont2 + abs r2,r3 +cont2: + bra start || nop + bra.s exit + jmp 0 || nop + bsrtnz.s r1,cont + bsrtnz r1,cont + bratnz.s r1,cont + bratnz r1,cont + jmptnz.s r1,cont + bsrtnz.s r1, foo + jmptnz.s r1, unk + bsrtnz.s r1, unk + jmptnz r1, unk + bsrtnz r1, unk + bra.s foo + bra foo + bra start + jmp start + jmp start + jmp.s start + jmp.s foo + bra start + bra unknown + jmp unknown + jmp.s unknown + bra.s unknown + + .data +bar: .asciz "XYZZY" +bar2: .long 0xdeadbeef + + .text + .space 0xF00,0 + +foo: + add r1,r0,r0 + ld2w r60, @(r0,longzero) + add r62,r0,r0 + bsr.s exit + bsr.s foo + bra.s cont2 + bra.s cont2 + bsr.s exit + jmp.s exit + jmp.s exit + jmp.s exit + bsr exit + jmp exit + +longzero: + .quad 0 + + .text +exit: + jmp r62 diff --git a/gas/testsuite/gas/d30v/serial.l b/gas/testsuite/gas/d30v/serial.l new file mode 100644 index 00000000000..f7a5a670766 --- /dev/null +++ b/gas/testsuite/gas/d30v/serial.l @@ -0,0 +1,46 @@ +.*: Assembler messages: +.*:6: Error: Unable to mix instructions as specified +.*:7: Error: Unable to mix instructions as specified +.*:8: Error: Unable to mix instructions as specified +.*:9: Error: Unable to mix instructions as specified +GAS LISTING .* + + + 1 # serial.s + 2 # + 3 # In the following examples, the right-subinstructions + 4 # will never be executed. GAS should detect this. + 5 + 6 \?\?\?\? 000000F0 trap r21 -> add r2, r0, r0 ; right instruction will never be executed. +\*\*\*\* Error:Unable to mix instructions as specified + 6 000000F0 + 6 000000F0 + 6 00000090 + 6 001500F0 + 7 \?\?\?\? 08002000 dbt -> add r2, r0, r0 ; ditto +\*\*\*\* Error:Unable to mix instructions as specified + 7 00F00000 + 7 00B00000 + 7 00F00000 + 8 \?\?\?\? 08002000 rtd -> add r2, r0, r0 ; ditto +\*\*\*\* Error:Unable to mix instructions as specified + 8 00F00000 + 8 00A00000 + 8 00F00000 + 9 \?\?\?\? 08002000 reit -> add r2, r0, r0 ; ditto +\*\*\*\* Error:Unable to mix instructions as specified + 9 00F00000 + 9 00800000 + 9 00F00000 + 10 \?\?\?\? 08002000 mvtsys psw, r1 -> add r2, r0, r0 ; OK + 10 00F00000 + 10 00E00040 + 10 88002000 + 11 \?\?\?\? 00E00042 mvtsys pswh, r1 -> add r2, r0, r0 ; OK + 11 88002000 + 12 \?\?\?\? 00E00041 mvtsys pswl, r1 -> add r2, r0, r0 ; OK + 12 88002000 + 13 \?\?\?\? 00E00043 mvtsys f0, r1 -> add r2, r0, r0 ; OK + 13 88002000 + 14 \?\?\?\? 00E0A040 mvtsys mod_s, r1 -> add r2, r0, r0 ; OK + 14 88002000 diff --git a/gas/testsuite/gas/d30v/serial.s b/gas/testsuite/gas/d30v/serial.s new file mode 100644 index 00000000000..0995d634b84 --- /dev/null +++ b/gas/testsuite/gas/d30v/serial.s @@ -0,0 +1,14 @@ +# serial.s +# +# In the following examples, the right-subinstructions +# will never be executed. GAS should detect this. + + trap r21 -> add r2, r0, r0 ; right instruction will never be executed. + dbt -> add r2, r0, r0 ; ditto + rtd -> add r2, r0, r0 ; ditto + reit -> add r2, r0, r0 ; ditto + mvtsys psw, r1 -> add r2, r0, r0 ; OK + mvtsys pswh, r1 -> add r2, r0, r0 ; OK + mvtsys pswl, r1 -> add r2, r0, r0 ; OK + mvtsys f0, r1 -> add r2, r0, r0 ; OK + mvtsys mod_s, r1 -> add r2, r0, r0 ; OK diff --git a/gas/testsuite/gas/d30v/serial2.l b/gas/testsuite/gas/d30v/serial2.l new file mode 100644 index 00000000000..2de04dc2dbb --- /dev/null +++ b/gas/testsuite/gas/d30v/serial2.l @@ -0,0 +1,138 @@ +.*: Assembler messages: +.*:5: Error: Unable to mix instructions as specified +.*:6: Error: Unable to mix instructions as specified +.*:8: Error: Unable to mix instructions as specified +.*:9: Error: Unable to mix instructions as specified +.*:11: Error: Unable to mix instructions as specified +.*:12: Error: Unable to mix instructions as specified +.*:13: Error: Unable to mix instructions as specified +.*:14: Error: Unable to mix instructions as specified +.*:16: Error: Unable to mix instructions as specified +.*:17: Error: Unable to mix instructions as specified +.*:18: Error: Unable to mix instructions as specified +.*:19: Error: Unable to mix instructions as specified +.*:21: Error: Unable to mix instructions as specified +.*:22: Error: Unable to mix instructions as specified +.*:23: Error: Unable to mix instructions as specified +.*:24: Error: Unable to mix instructions as specified +.*:26: Error: Unable to mix instructions as specified +.*:27: Error: Unable to mix instructions as specified +.*:28: Error: Unable to mix instructions as specified +.*:29: Error: Unable to mix instructions as specified +GAS LISTING .* + + + 1 # D30V serial execution test + 2 + 3 .text + 4 + 5 \?\?\?\? 000000F0 bra -3 -> add r3,r0,0 ; Invalid +\*\*\*\* Error:Unable to mix instructions as specified + 5 000000F0 + 5 000000F0 + 5 0000000B + 5 FFFF00F0 + 6 \?\?\?\? 08083000 bsr -3 -> add r3,r0,0 ; Invalid +\*\*\*\* Error:Unable to mix instructions as specified + 6 00F00000 + 6 002BFFFF + 6 00F00000 + 7 + 8 \?\?\?\? 08083000 bra/tx -3 -> add r3,r0,0 ; Valid +\*\*\*\* Error:Unable to mix instructions as specified + 8 00F00000 + 8 100BFFFF + 8 00F00000 + 9 \?\?\?\? 08083000 bsr/tx -3 -> add r3,r0,0 ; Valid +\*\*\*\* Error:Unable to mix instructions as specified + 9 00F00000 + 9 102BFFFF + 9 00F00000 + 10 + 11 \?\?\?\? 08083000 bsr -3 -> bsr -10 ; Invalid +\*\*\*\* Error:Unable to mix instructions as specified + 11 00F00000 + 11 002BFFFF + 11 00F00000 + 12 \?\?\?\? 002BFFFE bsr -3 -> bsr/xt -10 ; Invalid +\*\*\*\* Error:Unable to mix instructions as specified + 12 00F00000 + 12 002BFFFF + 12 00F00000 + 13 \?\?\?\? 302BFFFE bsr/tx -3 -> bsr -10 ; Valid +\*\*\*\* Error:Unable to mix instructions as specified + 13 00F00000 + 13 102BFFFF + 13 00F00000 + 14 \?\?\?\? 002BFFFE bsr/tx -3 -> bsr/fx -10 ; Valid +\*\*\*\* Error:Unable to mix instructions as specified + 14 00F00000 + 14 102BFFFF + 14 00F00000 + 15 + 16 \?\?\?\? 202BFFFE bra -3 -> bra 10 ; Invalid +\*\*\*\* Error:Unable to mix instructions as specified + 16 00F00000 + 16 000BFFFF + 16 00F00000 + 17 \?\?\?\? 00080001 bra -3 -> bra/tx 10 ; Invalid +\*\*\*\* Error:Unable to mix instructions as specified + 17 00F00000 + 17 000BFFFF + GAS LISTING .* + + + 17 00F00000 + 18 \?\?\?\? 10080001 bra/tx -3 -> bra 10 ; Valid +\*\*\*\* Error:Unable to mix instructions as specified + 18 00F00000 + 18 100BFFFF + 18 00F00000 + 19 \?\?\?\? 00080001 bra/tx -3 -> bra/fx 10 ; Valid +\*\*\*\* Error:Unable to mix instructions as specified + 19 00F00000 + 19 100BFFFF + 19 00F00000 + 20 + 21 \?\?\?\? 20080001 bsr -3 -> bra 10 ; Invalid +\*\*\*\* Error:Unable to mix instructions as specified + 21 00F00000 + 21 002BFFFF + 21 00F00000 + 22 \?\?\?\? 00080001 bsr -3 -> bra/tx 10 ; Invalid +\*\*\*\* Error:Unable to mix instructions as specified + 22 00F00000 + 22 002BFFFF + 22 00F00000 + 23 \?\?\?\? 10080001 bsr/tx -3 -> bra 10 ; Valid +\*\*\*\* Error:Unable to mix instructions as specified + 23 00F00000 + 23 102BFFFF + 23 00F00000 + 24 \?\?\?\? 00080001 bsr/tx -3 -> bra/fx 10 ; Valid +\*\*\*\* Error:Unable to mix instructions as specified + 24 00F00000 + 24 102BFFFF + 24 00F00000 + 25 + 26 \?\?\?\? 20080001 bra -3 -> bsr 10 ; Invalid +\*\*\*\* Error:Unable to mix instructions as specified + 26 00F00000 + 26 000BFFFF + 26 00F00000 + 27 \?\?\?\? 00280001 bra -3 -> bsr/tx 10 ; Invalid +\*\*\*\* Error:Unable to mix instructions as specified + 27 00F00000 + 27 000BFFFF + 27 00F00000 + 28 \?\?\?\? 10280001 bra/tx -3 -> bsr 10 ; Valid +\*\*\*\* Error:Unable to mix instructions as specified + 28 00F00000 + 28 100BFFFF + 28 00F00000 + 29 \?\?\?\? 00280001 bra/tx -3 -> bsr/fx 10 ; Valid +\*\*\*\* Error:Unable to mix instructions as specified + 29 00F00000 + 29 100BFFFF + 29 00F00000 + 29 20280001 diff --git a/gas/testsuite/gas/d30v/serial2.s b/gas/testsuite/gas/d30v/serial2.s new file mode 100644 index 00000000000..04531590228 --- /dev/null +++ b/gas/testsuite/gas/d30v/serial2.s @@ -0,0 +1,29 @@ +# D30V serial execution test + + .text + + bra -3 -> add r3,r0,0 ; Invalid + bsr -3 -> add r3,r0,0 ; Invalid + + bra/tx -3 -> add r3,r0,0 ; Valid + bsr/tx -3 -> add r3,r0,0 ; Valid + + bsr -3 -> bsr -10 ; Invalid + bsr -3 -> bsr/xt -10 ; Invalid + bsr/tx -3 -> bsr -10 ; Valid + bsr/tx -3 -> bsr/fx -10 ; Valid + + bra -3 -> bra 10 ; Invalid + bra -3 -> bra/tx 10 ; Invalid + bra/tx -3 -> bra 10 ; Valid + bra/tx -3 -> bra/fx 10 ; Valid + + bsr -3 -> bra 10 ; Invalid + bsr -3 -> bra/tx 10 ; Invalid + bsr/tx -3 -> bra 10 ; Valid + bsr/tx -3 -> bra/fx 10 ; Valid + + bra -3 -> bsr 10 ; Invalid + bra -3 -> bsr/tx 10 ; Invalid + bra/tx -3 -> bsr 10 ; Valid + bra/tx -3 -> bsr/fx 10 ; Valid diff --git a/gas/testsuite/gas/d30v/serial2O.l b/gas/testsuite/gas/d30v/serial2O.l new file mode 100644 index 00000000000..d9eb05cb1a9 --- /dev/null +++ b/gas/testsuite/gas/d30v/serial2O.l @@ -0,0 +1,99 @@ +.*: Assembler messages: +.*:5: Error: Unable to mix instructions as specified +.*:6: Error: Unable to mix instructions as specified +.*:11: Error: Unable to mix instructions as specified +.*:12: Error: Unable to mix instructions as specified +.*:16: Error: Unable to mix instructions as specified +.*:17: Error: Unable to mix instructions as specified +.*:21: Error: Unable to mix instructions as specified +.*:22: Error: Unable to mix instructions as specified +.*:26: Error: Unable to mix instructions as specified +.*:27: Error: Unable to mix instructions as specified +GAS LISTING .* + + + 1 # D30V serial execution test + 2 + 3 .text + 4 + 5 \?\?\?\? 000000F0 bra -3 -> add r3,r0,0 ; Invalid +\*\*\*\* Error:Unable to mix instructions as specified + 5 000000F0 + 5 000000F0 + 5 0000000B + 5 FFFF00F0 + 6 \?\?\?\? 08083000 bsr -3 -> add r3,r0,0 ; Invalid +\*\*\*\* Error:Unable to mix instructions as specified + 6 00F00000 + 6 002BFFFF + 6 00F00000 + 7 + 8 \?\?\?\? 08083000 bra/tx -3 -> add r3,r0,0 ; Valid + 8 00F00000 + 8 100BFFFF + 8 88083000 + 9 \?\?\?\? 102BFFFF bsr/tx -3 -> add r3,r0,0 ; Valid + 9 88083000 + 10 + 11 \?\?\?\? 002BFFFF bsr -3 -> bsr -10 ; Invalid +\*\*\*\* Error:Unable to mix instructions as specified + 11 00F00000 + 12 \?\?\?\? 002BFFFE bsr -3 -> bsr/xt -10 ; Invalid +\*\*\*\* Error:Unable to mix instructions as specified + 12 00F00000 + 12 002BFFFF + 12 00F00000 + 13 \?\?\?\? 302BFFFE bsr/tx -3 -> bsr -10 ; Valid + 13 00F00000 + 13 102BFFFF + 13 802BFFFE + 14 \?\?\?\? 102BFFFF bsr/tx -3 -> bsr/fx -10 ; Valid + 14 A02BFFFE + 15 + 16 \?\?\?\? 000BFFFF bra -3 -> bra 10 ; Invalid +\*\*\*\* Error:Unable to mix instructions as specified + 16 00F00000 + 17 \?\?\?\? 00080001 bra -3 -> bra/tx 10 ; Invalid +\*\*\*\* Error:Unable to mix instructions as specified + 17 00F00000 + 17 000BFFFF + 17 00F00000 + 18 \?\?\?\? 10080001 bra/tx -3 -> bra 10 ; Valid + 18 00F00000 + 18 100BFFFF + 18 80080001 + 19 \?\?\?\? 100BFFFF bra/tx -3 -> bra/fx 10 ; Valid + 19 A0080001 + 20 + 21 \?\?\?\? 002BFFFF bsr -3 -> bra 10 ; Invalid +\*\*\*\* Error:Unable to mix instructions as specified + 21 00F00000 + 22 \?\?\?\? 00080001 bsr -3 -> bra/tx 10 ; Invalid + GAS LISTING .* + + +\*\*\*\* Error:Unable to mix instructions as specified + 22 00F00000 + 22 002BFFFF + 22 00F00000 + 23 \?\?\?\? 10080001 bsr/tx -3 -> bra 10 ; Valid + 23 00F00000 + 23 102BFFFF + 23 80080001 + 24 \?\?\?\? 102BFFFF bsr/tx -3 -> bra/fx 10 ; Valid + 24 A0080001 + 25 + 26 \?\?\?\? 000BFFFF bra -3 -> bsr 10 ; Invalid +\*\*\*\* Error:Unable to mix instructions as specified + 26 00F00000 + 27 \?\?\?\? 00280001 bra -3 -> bsr/tx 10 ; Invalid +\*\*\*\* Error:Unable to mix instructions as specified + 27 00F00000 + 27 000BFFFF + 27 00F00000 + 28 \?\?\?\? 10280001 bra/tx -3 -> bsr 10 ; Valid + 28 00F00000 + 28 100BFFFF + 28 80280001 + 29 \?\?\?\? 100BFFFF bra/tx -3 -> bsr/fx 10 ; Valid + 29 A0280001 diff --git a/gas/testsuite/gas/d30v/serial2O.s b/gas/testsuite/gas/d30v/serial2O.s new file mode 100644 index 00000000000..04531590228 --- /dev/null +++ b/gas/testsuite/gas/d30v/serial2O.s @@ -0,0 +1,29 @@ +# D30V serial execution test + + .text + + bra -3 -> add r3,r0,0 ; Invalid + bsr -3 -> add r3,r0,0 ; Invalid + + bra/tx -3 -> add r3,r0,0 ; Valid + bsr/tx -3 -> add r3,r0,0 ; Valid + + bsr -3 -> bsr -10 ; Invalid + bsr -3 -> bsr/xt -10 ; Invalid + bsr/tx -3 -> bsr -10 ; Valid + bsr/tx -3 -> bsr/fx -10 ; Valid + + bra -3 -> bra 10 ; Invalid + bra -3 -> bra/tx 10 ; Invalid + bra/tx -3 -> bra 10 ; Valid + bra/tx -3 -> bra/fx 10 ; Valid + + bsr -3 -> bra 10 ; Invalid + bsr -3 -> bra/tx 10 ; Invalid + bsr/tx -3 -> bra 10 ; Valid + bsr/tx -3 -> bra/fx 10 ; Valid + + bra -3 -> bsr 10 ; Invalid + bra -3 -> bsr/tx 10 ; Invalid + bra/tx -3 -> bsr 10 ; Valid + bra/tx -3 -> bsr/fx 10 ; Valid diff --git a/gas/testsuite/gas/d30v/warn_oddreg.l b/gas/testsuite/gas/d30v/warn_oddreg.l new file mode 100644 index 00000000000..f1fb43cb2ca --- /dev/null +++ b/gas/testsuite/gas/d30v/warn_oddreg.l @@ -0,0 +1,40 @@ +.*: Assembler messages: +.*:5: Warning: Odd numbered register used as target of multi-register instruction +.*:6: Warning: Odd numbered register used as target of multi-register instruction +.*:7: Warning: Odd numbered register used as target of multi-register instruction +.*:8: Warning: Odd numbered register used as target of multi-register instruction +.*:9: Warning: Odd numbered register used as target of multi-register instruction +.*:10: Warning: Odd numbered register used as target of multi-register instruction +.*:11: Warning: Odd numbered register used as target of multi-register instruction +.*:12: Warning: Odd numbered register used as target of multi-register instruction +GAS LISTING .* + + + 1 # GAS should print a warning when an odd register is used as a target + 2 # of multi-word instructions: ld2w, ld4bh, ld4bhu, ld2h, st2w, st4hb, st2h, + 3 # and mulx2h + 4 + 5 0000 05681000 st2w r1, @(r0, 0) || nop +.* Warning:Odd numbered register used as target of multi-register instruction + 5 00F00000 + 6 0008 04681000 ld2w r1, @(r0, 0) || nop +.* Warning:Odd numbered register used as target of multi-register instruction + 6 00F00000 + 7 0010 04581000 ld4bh r1, @(r0, 0) || nop +.* Warning:Odd numbered register used as target of multi-register instruction + 7 00F00000 + 8 0018 04D81000 ld4bhu r1, @(r0, 0) || nop +.* Warning:Odd numbered register used as target of multi-register instruction + 8 00F00000 + 9 0020 04381000 ld2h r1, @(r0, 0) || nop +.* Warning:Odd numbered register used as target of multi-register instruction + 9 00F00000 + 10 0028 05581000 st4hb r1, @(r0, 0) || nop +.* Warning:Odd numbered register used as target of multi-register instruction + 10 00F00000 + 11 0030 05381000 st2h r1, @(r0, 0) || nop +.* Warning:Odd numbered register used as target of multi-register instruction + 11 00F00000 + 12 0038 00F00000 nop || mulx2h r1, r5, r6 +.* Warning:Odd numbered register used as target of multi-register instruction + 12 0A101146 diff --git a/gas/testsuite/gas/d30v/warn_oddreg.s b/gas/testsuite/gas/d30v/warn_oddreg.s new file mode 100644 index 00000000000..c09f750948a --- /dev/null +++ b/gas/testsuite/gas/d30v/warn_oddreg.s @@ -0,0 +1,12 @@ +# GAS should print a warning when an odd register is used as a target +# of multi-word instructions: ld2w, ld4bh, ld4bhu, ld2h, st2w, st4hb, st2h, +# and mulx2h + +st2w r1, @(r0, 0) || nop +ld2w r1, @(r0, 0) || nop +ld4bh r1, @(r0, 0) || nop +ld4bhu r1, @(r0, 0) || nop +ld2h r1, @(r0, 0) || nop +st4hb r1, @(r0, 0) || nop +st2h r1, @(r0, 0) || nop +nop || mulx2h r1, r5, r6 |