diff options
| -rw-r--r-- | gas/ChangeLog | 25 | ||||
| -rw-r--r-- | gas/config/tc-aarch64.c | 214 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/diagnostic.l | 12 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/diagnostic.s | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/illegal-lse.l | 456 |
5 files changed, 371 insertions, 339 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 28b12b4323a..e56f239e27f 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,30 @@ 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> + * config/tc-aarch64.c (REG_TYPE_R_Z, REG_TYPE_R_SP): New register + types. + (get_reg_expected_msg): Handle them and REG_TYPE_R64_SP. + (aarch64_check_reg_type): Simplify. + (aarch64_reg_parse_32_64): Return the reg_entry instead of the + register number. Return the type as a qualifier rather than an + "isreg32" boolean. Remove reject_sp, reject_rz and isregzero + parameters. + (parse_shifter_operand): Update call to aarch64_parse_32_64_reg. + Use get_reg_expected_msg. + (parse_address_main): Likewise. Use aarch64_check_reg_type. + (po_int_reg_or_fail): Replace reject_sp and reject_rz parameters + with a reg_type parameter. Update call to aarch64_parse_32_64_reg. + Use aarch64_check_reg_type to test the result. + (parse_operands): Update after the above changes. Parse ADDR_SIMPLE + addresses normally before enforcing the syntax restrictions. + * testsuite/gas/aarch64/diagnostic.s: Add tests for a post-index + zero register and for a stack pointer index. + * testsuite/gas/aarch64/diagnostic.l: Update accordingly. + Also update existing diagnostic messages after the above changes. + * testsuite/gas/aarch64/illegal-lse.l: Update the error message + for 32-bit register bases. + +2016-09-21 Richard Sandiford <richard.sandiford@arm.com> + * config/tc-aarch64.c (parse_aarch64_imm_float): Remove range check. (parse_operands): Check the range of 8-bit FP immediates here instead. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 2489d5bc1d2..7b5be8b2f99 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -265,16 +265,22 @@ struct reloc_entry BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \ BASIC_REG_TYPE(CN) /* c[0-7] */ \ BASIC_REG_TYPE(VN) /* v[0-31] */ \ - /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \ + /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \ MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \ - /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \ + /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \ + MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \ + | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \ + /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \ + MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \ + | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \ + /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \ MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \ | REG_TYPE(SP_32) | REG_TYPE(SP_64) \ | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \ /* Typecheck: any [BHSDQ]P FP. */ \ MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \ | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \ - /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \ + /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \ MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \ | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \ | REG_TYPE(FP_B) | REG_TYPE(FP_H) \ @@ -344,6 +350,15 @@ get_reg_expected_msg (aarch64_reg_type reg_type) case REG_TYPE_R_N: msg = N_("integer register expected"); break; + case REG_TYPE_R64_SP: + msg = N_("64-bit integer or SP register expected"); + break; + case REG_TYPE_R_Z: + msg = N_("integer or zero register expected"); + break; + case REG_TYPE_R_SP: + msg = N_("integer or SP register expected"); + break; case REG_TYPE_R_Z_SP: msg = N_("integer, zero or SP register expected"); break; @@ -390,9 +405,6 @@ get_reg_expected_msg (aarch64_reg_type reg_type) /* Instructions take 4 bytes in the object file. */ #define INSN_SIZE 4 -/* Define some common error messages. */ -#define BAD_SP _("SP not allowed here") - static struct hash_control *aarch64_ops_hsh; static struct hash_control *aarch64_cond_hsh; static struct hash_control *aarch64_shift_hsh; @@ -671,72 +683,45 @@ parse_reg (char **ccp) static bfd_boolean aarch64_check_reg_type (const reg_entry *reg, aarch64_reg_type type) { - if (reg->type == type) - return TRUE; - - switch (type) - { - case REG_TYPE_R64_SP: /* 64-bit integer reg (inc SP exc XZR). */ - case REG_TYPE_R_Z_SP: /* Integer reg (inc {X}SP inc [WX]ZR). */ - case REG_TYPE_R_Z_BHSDQ_V: /* Any register apart from Cn. */ - case REG_TYPE_BHSDQ: /* Any [BHSDQ]P FP or SIMD scalar register. */ - case REG_TYPE_VN: /* Vector register. */ - gas_assert (reg->type < REG_TYPE_MAX && type < REG_TYPE_MAX); - return ((reg_type_masks[reg->type] & reg_type_masks[type]) - == reg_type_masks[reg->type]); - default: - as_fatal ("unhandled type %d", type); - abort (); - } + return (reg_type_masks[type] & (1 << reg->type)) != 0; } -/* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP. - Return the register number otherwise. *ISREG32 is set to one if the - register is 32-bit wide; *ISREGZERO is set to one if the register is - of type Z_32 or Z_64. +/* Try to parse a base or offset register. Return the register entry + on success, setting *QUALIFIER to the register qualifier. Return null + otherwise. + Note that this function does not issue any diagnostics. */ -static int -aarch64_reg_parse_32_64 (char **ccp, int reject_sp, int reject_rz, - int *isreg32, int *isregzero) +static const reg_entry * +aarch64_reg_parse_32_64 (char **ccp, aarch64_opnd_qualifier_t *qualifier) { char *str = *ccp; const reg_entry *reg = parse_reg (&str); if (reg == NULL) - return PARSE_FAIL; - - if (! aarch64_check_reg_type (reg, REG_TYPE_R_Z_SP)) - return PARSE_FAIL; + return NULL; switch (reg->type) { + case REG_TYPE_R_32: case REG_TYPE_SP_32: - case REG_TYPE_SP_64: - if (reject_sp) - return PARSE_FAIL; - *isreg32 = reg->type == REG_TYPE_SP_32; - *isregzero = 0; + case REG_TYPE_Z_32: + *qualifier = AARCH64_OPND_QLF_W; break; - case REG_TYPE_R_32: + case REG_TYPE_R_64: - *isreg32 = reg->type == REG_TYPE_R_32; - *isregzero = 0; - break; - case REG_TYPE_Z_32: + case REG_TYPE_SP_64: case REG_TYPE_Z_64: - if (reject_rz) - return PARSE_FAIL; - *isreg32 = reg->type == REG_TYPE_Z_32; - *isregzero = 1; + *qualifier = AARCH64_OPND_QLF_X; break; + default: - return PARSE_FAIL; + return NULL; } *ccp = str; - return reg->number; + return reg; } /* Parse the qualifier of a SIMD vector register or a SIMD vector element. @@ -3032,13 +3017,13 @@ static bfd_boolean parse_shifter_operand (char **str, aarch64_opnd_info *operand, enum parse_shift_mode mode) { - int reg; - int isreg32, isregzero; + const reg_entry *reg; + aarch64_opnd_qualifier_t qualifier; enum aarch64_operand_class opd_class = aarch64_get_operand_class (operand->type); - if ((reg = - aarch64_reg_parse_32_64 (str, 0, 0, &isreg32, &isregzero)) != PARSE_FAIL) + reg = aarch64_reg_parse_32_64 (str, &qualifier); + if (reg) { if (opd_class == AARCH64_OPND_CLASS_IMMEDIATE) { @@ -3046,14 +3031,14 @@ parse_shifter_operand (char **str, aarch64_opnd_info *operand, return FALSE; } - if (!isregzero && reg == REG_SP) + if (!aarch64_check_reg_type (reg, REG_TYPE_R_Z)) { - set_syntax_error (BAD_SP); + set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z))); return FALSE; } - operand->reg.regno = reg; - operand->qualifier = isreg32 ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X; + operand->reg.regno = reg->number; + operand->qualifier = qualifier; /* Accept optional shift operation on register. */ if (! skip_past_comma (str)) @@ -3192,8 +3177,9 @@ parse_address_main (char **str, aarch64_opnd_info *operand, int reloc, int accept_reg_post_index) { char *p = *str; - int reg; - int isreg32, isregzero; + const reg_entry *reg; + aarch64_opnd_qualifier_t base_qualifier; + aarch64_opnd_qualifier_t offset_qualifier; expressionS *exp = &inst.reloc.exp; if (! skip_past_char (&p, '[')) @@ -3270,14 +3256,13 @@ parse_address_main (char **str, aarch64_opnd_info *operand, int reloc, /* [ */ - /* Accept SP and reject ZR */ - reg = aarch64_reg_parse_32_64 (&p, 0, 1, &isreg32, &isregzero); - if (reg == PARSE_FAIL || isreg32) + reg = aarch64_reg_parse_32_64 (&p, &base_qualifier); + if (!reg || !aarch64_check_reg_type (reg, REG_TYPE_R64_SP)) { - set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64))); + set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R64_SP))); return FALSE; } - operand->addr.base_regno = reg; + operand->addr.base_regno = reg->number; /* [Xn */ if (skip_past_comma (&p)) @@ -3285,12 +3270,17 @@ parse_address_main (char **str, aarch64_opnd_info *operand, int reloc, /* [Xn, */ operand->addr.preind = 1; - /* Reject SP and accept ZR */ - reg = aarch64_reg_parse_32_64 (&p, 1, 0, &isreg32, &isregzero); - if (reg != PARSE_FAIL) + reg = aarch64_reg_parse_32_64 (&p, &offset_qualifier); + if (reg) { + if (!aarch64_check_reg_type (reg, REG_TYPE_R_Z)) + { + set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z))); + return FALSE; + } + /* [Xn,Rm */ - operand->addr.offset.regno = reg; + operand->addr.offset.regno = reg->number; operand->addr.offset.is_reg = 1; /* Shifted index. */ if (skip_past_comma (&p)) @@ -3309,13 +3299,13 @@ parse_address_main (char **str, aarch64_opnd_info *operand, int reloc, || operand->shifter.kind == AARCH64_MOD_LSL || operand->shifter.kind == AARCH64_MOD_SXTX) { - if (isreg32) + if (offset_qualifier == AARCH64_OPND_QLF_W) { set_syntax_error (_("invalid use of 32-bit register offset")); return FALSE; } } - else if (!isreg32) + else if (offset_qualifier == AARCH64_OPND_QLF_X) { set_syntax_error (_("invalid use of 64-bit register offset")); return FALSE; @@ -3399,16 +3389,16 @@ parse_address_main (char **str, aarch64_opnd_info *operand, int reloc, } if (accept_reg_post_index - && (reg = aarch64_reg_parse_32_64 (&p, 1, 1, &isreg32, - &isregzero)) != PARSE_FAIL) + && (reg = aarch64_reg_parse_32_64 (&p, &offset_qualifier))) { /* [Xn],Xm */ - if (isreg32) + if (!aarch64_check_reg_type (reg, REG_TYPE_R_64)) { - set_syntax_error (_("invalid 32-bit register offset")); + set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64))); return FALSE; } - operand->addr.offset.regno = reg; + + operand->addr.offset.regno = reg->number; operand->addr.offset.is_reg = 1; } else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1)) @@ -3723,19 +3713,15 @@ parse_sys_ins_reg (char **str, struct hash_control *sys_ins_regs) } \ } while (0) -#define po_int_reg_or_fail(reject_sp, reject_rz) do { \ - val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \ - &isreg32, &isregzero); \ - if (val == PARSE_FAIL) \ +#define po_int_reg_or_fail(reg_type) do { \ + reg = aarch64_reg_parse_32_64 (&str, &qualifier); \ + if (!reg || !aarch64_check_reg_type (reg, reg_type)) \ { \ set_default_error (); \ goto failure; \ } \ - info->reg.regno = val; \ - if (isreg32) \ - info->qualifier = AARCH64_OPND_QLF_W; \ - else \ - info->qualifier = AARCH64_OPND_QLF_X; \ + info->reg.regno = reg->number; \ + info->qualifier = qualifier; \ } while (0) #define po_imm_nc_or_fail() do { \ @@ -4993,10 +4979,11 @@ parse_operands (char *str, const aarch64_opcode *opcode) for (i = 0; operands[i] != AARCH64_OPND_NIL; i++) { int64_t val; - int isreg32, isregzero; + const reg_entry *reg; int comma_skipped_p = 0; aarch64_reg_type rtype; struct vector_type_el vectype; + aarch64_opnd_qualifier_t qualifier; aarch64_opnd_info *info = &inst.base.operands[i]; DEBUG_TRACE ("parse operand %d", i); @@ -5032,12 +5019,12 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_Ra: case AARCH64_OPND_Rt_SYS: case AARCH64_OPND_PAIRREG: - po_int_reg_or_fail (1, 0); + po_int_reg_or_fail (REG_TYPE_R_Z); break; case AARCH64_OPND_Rd_SP: case AARCH64_OPND_Rn_SP: - po_int_reg_or_fail (0, 1); + po_int_reg_or_fail (REG_TYPE_R_SP); break; case AARCH64_OPND_Rm_EXT: @@ -5498,24 +5485,39 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_ADDR_SIMPLE: case AARCH64_OPND_SIMD_ADDR_SIMPLE: - /* [<Xn|SP>{, #<simm>}] */ - po_char_or_fail ('['); - po_reg_or_fail (REG_TYPE_R64_SP); - /* Accept optional ", #0". */ - if (operands[i] == AARCH64_OPND_ADDR_SIMPLE - && skip_past_char (&str, ',')) - { - skip_past_char (&str, '#'); - if (! skip_past_char (&str, '0')) - { - set_fatal_syntax_error - (_("the optional immediate offset can only be 0")); - goto failure; - } - } - po_char_or_fail (']'); - info->addr.base_regno = val; - break; + { + /* [<Xn|SP>{, #<simm>}] */ + char *start = str; + /* First use the normal address-parsing routines, to get + the usual syntax errors. */ + po_misc_or_fail (parse_address (&str, info, 0)); + if (info->addr.pcrel || info->addr.offset.is_reg + || !info->addr.preind || info->addr.postind + || info->addr.writeback) + { + set_syntax_error (_("invalid addressing mode")); + goto failure; + } + + /* Then retry, matching the specific syntax of these addresses. */ + str = start; + po_char_or_fail ('['); + po_reg_or_fail (REG_TYPE_R64_SP); + /* Accept optional ", #0". */ + if (operands[i] == AARCH64_OPND_ADDR_SIMPLE + && skip_past_char (&str, ',')) + { + skip_past_char (&str, '#'); + if (! skip_past_char (&str, '0')) + { + set_fatal_syntax_error + (_("the optional immediate offset can only be 0")); + goto failure; + } + } + po_char_or_fail (']'); + break; + } case AARCH64_OPND_ADDR_REGOFF: /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */ diff --git a/gas/testsuite/gas/aarch64/diagnostic.l b/gas/testsuite/gas/aarch64/diagnostic.l index 67ef484b7b7..ef2357759f3 100644 --- a/gas/testsuite/gas/aarch64/diagnostic.l +++ b/gas/testsuite/gas/aarch64/diagnostic.l @@ -54,7 +54,7 @@ [^:]*:56: Error: operand 2 should be a floating-point register -- `fcmp d0,x0' [^:]*:57: Error: immediate zero expected at operand 3 -- `cmgt v0.4s,v2.4s,#1' [^:]*:58: Error: unexpected characters following instruction at operand 2 -- `fmov d3,1.00,lsl#3' -[^:]*:59: Error: writeback value should be an immediate constant at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],sp' +[^:]*:59: Error: integer 64-bit register expected at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],sp' [^:]*:60: Error: writeback value should be an immediate constant at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],zr' [^:]*:61: Error: invalid shift for the register offset addressing mode at operand 2 -- `ldr q0,\[x0,w0,lsr#4\]' [^:]*:62: Error: only 'LSL' shift is permitted at operand 3 -- `adds x1,sp,2134,uxtw#12' @@ -116,10 +116,10 @@ [^:]*:125: Warning: unpredictable transfer with writeback -- `ldp x0,x1,\[x1\],#16' [^:]*:126: Error: this relocation modifier is not allowed on this instruction at operand 2 -- `adr x2,:got:s1' [^:]*:127: Error: this relocation modifier is not allowed on this instruction at operand 2 -- `ldr x0,\[x0,:got:s1\]' -[^:]*:130: Error: integer 64-bit register expected at operand 2 -- `ldr x1,\[wsp,#8\]!' -[^:]*:131: Error: integer 64-bit register expected at operand 3 -- `ldp x6,x29,\[w7,#8\]!' -[^:]*:132: Error: integer 64-bit register expected at operand 2 -- `str x30,\[w11,#8\]!' -[^:]*:133: Error: integer 64-bit register expected at operand 3 -- `stp x8,x27,\[wsp,#8\]!' +[^:]*:130: Error: 64-bit integer or SP register expected at operand 2 -- `ldr x1,\[wsp,#8\]!' +[^:]*:131: Error: 64-bit integer or SP register expected at operand 3 -- `ldp x6,x29,\[w7,#8\]!' +[^:]*:132: Error: 64-bit integer or SP register expected at operand 2 -- `str x30,\[w11,#8\]!' +[^:]*:133: Error: 64-bit integer or SP register expected at operand 3 -- `stp x8,x27,\[wsp,#8\]!' [^:]*:213: Error: register element index out of range 0 to 1 at operand 2 -- `dup v0\.2d,v1\.2d\[-1\]' [^:]*:216: Error: register element index out of range 0 to 1 at operand 2 -- `dup v0\.2d,v1\.2d\[2\]' [^:]*:217: Error: register element index out of range 0 to 1 at operand 2 -- `dup v0\.2d,v1\.2d\[64\]' @@ -148,3 +148,5 @@ [^:]*:262: Error: invalid floating-point constant at operand 2 -- `fmov d0,#-2' [^:]*:263: Error: invalid floating-point constant at operand 2 -- `fmov s0,2' [^:]*:264: Error: invalid floating-point constant at operand 2 -- `fmov s0,-2' +[^:]*:266: Error: integer 64-bit register expected at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],xzr' +[^:]*:267: Error: integer or zero register expected at operand 2 -- `str x1,\[x2,sp\]' diff --git a/gas/testsuite/gas/aarch64/diagnostic.s b/gas/testsuite/gas/aarch64/diagnostic.s index 3092b9b7ca1..8dbb5422334 100644 --- a/gas/testsuite/gas/aarch64/diagnostic.s +++ b/gas/testsuite/gas/aarch64/diagnostic.s @@ -262,3 +262,6 @@ fmov d0, #-2 fmov s0, 2 fmov s0, -2 + + st2 {v0.4s, v1.4s}, [sp], xzr + str x1, [x2, sp] diff --git a/gas/testsuite/gas/aarch64/illegal-lse.l b/gas/testsuite/gas/aarch64/illegal-lse.l index ed70065281a..dd57f99ed73 100644 --- a/gas/testsuite/gas/aarch64/illegal-lse.l +++ b/gas/testsuite/gas/aarch64/illegal-lse.l @@ -1,433 +1,433 @@ [^:]*: Assembler messages: [^:]*:68: Error: operand mismatch -- `cas w0,x1,\[x2\]' -[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `cas w2,w3,\[w4\]' +[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `cas w2,w3,\[w4\]' [^:]*:68: Error: operand mismatch -- `casa w0,x1,\[x2\]' -[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casa w2,w3,\[w4\]' +[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casa w2,w3,\[w4\]' [^:]*:68: Error: operand mismatch -- `casl w0,x1,\[x2\]' -[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casl w2,w3,\[w4\]' +[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casl w2,w3,\[w4\]' [^:]*:68: Error: operand mismatch -- `casal w0,x1,\[x2\]' -[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casal w2,w3,\[w4\]' +[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casal w2,w3,\[w4\]' [^:]*:68: Error: operand mismatch -- `casb w0,x1,\[x2\]' -[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casb w2,w3,\[w4\]' +[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casb w2,w3,\[w4\]' [^:]*:68: Error: operand mismatch -- `cash w0,x1,\[x2\]' -[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `cash w2,w3,\[w4\]' +[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `cash w2,w3,\[w4\]' [^:]*:68: Error: operand mismatch -- `casab w0,x1,\[x2\]' -[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casab w2,w3,\[w4\]' +[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casab w2,w3,\[w4\]' [^:]*:68: Error: operand mismatch -- `caslb w0,x1,\[x2\]' -[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `caslb w2,w3,\[w4\]' +[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `caslb w2,w3,\[w4\]' [^:]*:68: Error: operand mismatch -- `casalb w0,x1,\[x2\]' -[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casalb w2,w3,\[w4\]' +[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casalb w2,w3,\[w4\]' [^:]*:68: Error: operand mismatch -- `casah w0,x1,\[x2\]' -[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casah w2,w3,\[w4\]' +[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casah w2,w3,\[w4\]' [^:]*:68: Error: operand mismatch -- `caslh w0,x1,\[x2\]' -[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `caslh w2,w3,\[w4\]' +[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `caslh w2,w3,\[w4\]' [^:]*:68: Error: operand mismatch -- `casalh w0,x1,\[x2\]' -[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casalh w2,w3,\[w4\]' +[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casalh w2,w3,\[w4\]' [^:]*:68: Error: operand mismatch -- `cas w0,x1,\[x2\]' -[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `cas x2,x3,\[w4\]' +[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `cas x2,x3,\[w4\]' [^:]*:68: Error: operand mismatch -- `casa w0,x1,\[x2\]' -[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casa x2,x3,\[w4\]' +[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casa x2,x3,\[w4\]' [^:]*:68: Error: operand mismatch -- `casl w0,x1,\[x2\]' -[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casl x2,x3,\[w4\]' +[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casl x2,x3,\[w4\]' [^:]*:68: Error: operand mismatch -- `casal w0,x1,\[x2\]' -[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casal x2,x3,\[w4\]' +[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casal x2,x3,\[w4\]' [^:]*:69: Error: operand mismatch -- `swp w0,x1,\[x2\]' -[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swp w2,w3,\[w4\]' +[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swp w2,w3,\[w4\]' [^:]*:69: Error: operand mismatch -- `swpa w0,x1,\[x2\]' -[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpa w2,w3,\[w4\]' +[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpa w2,w3,\[w4\]' [^:]*:69: Error: operand mismatch -- `swpl w0,x1,\[x2\]' -[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpl w2,w3,\[w4\]' +[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpl w2,w3,\[w4\]' [^:]*:69: Error: operand mismatch -- `swpal w0,x1,\[x2\]' -[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpal w2,w3,\[w4\]' +[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpal w2,w3,\[w4\]' [^:]*:69: Error: operand mismatch -- `swpb w0,x1,\[x2\]' -[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpb w2,w3,\[w4\]' +[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpb w2,w3,\[w4\]' [^:]*:69: Error: operand mismatch -- `swph w0,x1,\[x2\]' -[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swph w2,w3,\[w4\]' +[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swph w2,w3,\[w4\]' [^:]*:69: Error: operand mismatch -- `swpab w0,x1,\[x2\]' -[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpab w2,w3,\[w4\]' +[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpab w2,w3,\[w4\]' [^:]*:69: Error: operand mismatch -- `swplb w0,x1,\[x2\]' -[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swplb w2,w3,\[w4\]' +[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swplb w2,w3,\[w4\]' [^:]*:69: Error: operand mismatch -- `swpalb w0,x1,\[x2\]' -[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpalb w2,w3,\[w4\]' +[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpalb w2,w3,\[w4\]' [^:]*:69: Error: operand mismatch -- `swpah w0,x1,\[x2\]' -[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpah w2,w3,\[w4\]' +[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpah w2,w3,\[w4\]' [^:]*:69: Error: operand mismatch -- `swplh w0,x1,\[x2\]' -[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swplh w2,w3,\[w4\]' +[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swplh w2,w3,\[w4\]' [^:]*:69: Error: operand mismatch -- `swpalh w0,x1,\[x2\]' -[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpalh w2,w3,\[w4\]' +[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpalh w2,w3,\[w4\]' [^:]*:69: Error: operand mismatch -- `swp w0,x1,\[x2\]' -[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swp x2,x3,\[w4\]' +[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swp x2,x3,\[w4\]' [^:]*:69: Error: operand mismatch -- `swpa w0,x1,\[x2\]' -[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpa x2,x3,\[w4\]' +[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpa x2,x3,\[w4\]' [^:]*:69: Error: operand mismatch -- `swpl w0,x1,\[x2\]' -[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpl x2,x3,\[w4\]' +[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpl x2,x3,\[w4\]' [^:]*:69: Error: operand mismatch -- `swpal w0,x1,\[x2\]' -[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpal x2,x3,\[w4\]' +[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpal x2,x3,\[w4\]' [^:]*:70: Error: reg pair must start from even reg at operand 1 -- `casp w1,w1,w2,w3,\[x5\]' [^:]*:70: Error: reg pair must be contiguous at operand 2 -- `casp w4,w4,w6,w7,\[sp\]' [^:]*:70: Error: operand mismatch -- `casp w0,x1,x2,x3,\[x2\]' -[^:]*:70: Error: operand 5 should be an address with base register \(no offset\) -- `casp x4,x5,x6,x7,\[w8\]' +[^:]*:70: Error: 64-bit integer or SP register expected at operand 5 -- `casp x4,x5,x6,x7,\[w8\]' [^:]*:70: Error: reg pair must start from even reg at operand 1 -- `caspa w1,w1,w2,w3,\[x5\]' [^:]*:70: Error: reg pair must be contiguous at operand 2 -- `caspa w4,w4,w6,w7,\[sp\]' [^:]*:70: Error: operand mismatch -- `caspa w0,x1,x2,x3,\[x2\]' -[^:]*:70: Error: operand 5 should be an address with base register \(no offset\) -- `caspa x4,x5,x6,x7,\[w8\]' +[^:]*:70: Error: 64-bit integer or SP register expected at operand 5 -- `caspa x4,x5,x6,x7,\[w8\]' [^:]*:70: Error: reg pair must start from even reg at operand 1 -- `caspl w1,w1,w2,w3,\[x5\]' [^:]*:70: Error: reg pair must be contiguous at operand 2 -- `caspl w4,w4,w6,w7,\[sp\]' [^:]*:70: Error: operand mismatch -- `caspl w0,x1,x2,x3,\[x2\]' -[^:]*:70: Error: operand 5 should be an address with base register \(no offset\) -- `caspl x4,x5,x6,x7,\[w8\]' +[^:]*:70: Error: 64-bit integer or SP register expected at operand 5 -- `caspl x4,x5,x6,x7,\[w8\]' [^:]*:70: Error: reg pair must start from even reg at operand 1 -- `caspal w1,w1,w2,w3,\[x5\]' [^:]*:70: Error: reg pair must be contiguous at operand 2 -- `caspal w4,w4,w6,w7,\[sp\]' [^:]*:70: Error: operand mismatch -- `caspal w0,x1,x2,x3,\[x2\]' -[^:]*:70: Error: operand 5 should be an address with base register \(no offset\) -- `caspal x4,x5,x6,x7,\[w8\]' +[^:]*:70: Error: 64-bit integer or SP register expected at operand 5 -- `caspal x4,x5,x6,x7,\[w8\]' [^:]*:71: Error: operand mismatch -- `ldadd w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldadd w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldadd w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldadda w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldadda w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldadda w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldaddl w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddl w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddl w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldaddal w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddal w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddal w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldaddb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldaddh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldaddab w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddab w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddab w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldaddlb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddlb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddlb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldaddalb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddalb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddalb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldaddah w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddah w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddah w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldaddlh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddlh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddlh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldaddalh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddalh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddalh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldadd w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldadd x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldadd x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldadda w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldadda x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldadda x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldaddl w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddl x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddl x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldaddal w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddal x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddal x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldclr w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclr w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclr w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldclra w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclra w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclra w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldclrl w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrl w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrl w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldclral w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclral w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclral w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldclrb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldclrh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldclrab w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrab w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrab w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldclrlb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrlb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrlb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldclralb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclralb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclralb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldclrah w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrah w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrah w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldclrlh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrlh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrlh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldclralh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclralh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclralh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldclr w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclr x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclr x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldclra w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclra x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclra x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldclrl w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrl x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrl x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldclral w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclral x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclral x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldeor w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeor w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeor w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldeora w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeora w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeora w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldeorl w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorl w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorl w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldeoral w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeoral w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeoral w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldeorb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldeorh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldeorab w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorab w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorab w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldeorlb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorlb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorlb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldeoralb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeoralb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeoralb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldeorah w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorah w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorah w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldeorlh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorlh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorlh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldeoralh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeoralh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeoralh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldeor w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeor x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeor x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldeora w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeora x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeora x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldeorl w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorl x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorl x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldeoral w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeoral x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeoral x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldset w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldset w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldset w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldseta w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldseta w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldseta w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsetl w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetl w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetl w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsetal w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetal w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetal w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsetb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldseth w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldseth w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldseth w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsetab w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetab w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetab w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsetlb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetlb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetlb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsetalb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetalb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetalb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsetah w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetah w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetah w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsetlh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetlh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetlh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsetalh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetalh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetalh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldset w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldset x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldset x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldseta w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldseta x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldseta x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsetl w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetl x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetl x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsetal w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetal x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetal x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsmax w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmax w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmax w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsmaxa w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxa w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxa w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsmaxl w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxl w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxl w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsmaxal w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxal w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxal w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsmaxb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsmaxh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsmaxab w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxab w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxab w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsmaxlb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxlb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxlb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsmaxalb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxalb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxalb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsmaxah w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxah w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxah w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsmaxlh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxlh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxlh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsmaxalh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxalh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxalh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsmax w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmax x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmax x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsmaxa w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxa x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxa x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsmaxl w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxl x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxl x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsmaxal w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxal x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxal x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsmin w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmin w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmin w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsmina w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmina w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmina w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsminl w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminl w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminl w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsminal w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminal w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminal w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsminb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsminh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsminab w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminab w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminab w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsminlb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminlb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminlb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsminalb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminalb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminalb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsminah w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminah w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminah w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsminlh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminlh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminlh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsminalh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminalh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminalh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsmin w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmin x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmin x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsmina w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmina x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmina x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsminl w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminl x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminl x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldsminal w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminal x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminal x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldumax w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumax w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumax w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldumaxa w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxa w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxa w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldumaxl w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxl w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxl w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldumaxal w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxal w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxal w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldumaxb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldumaxh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldumaxab w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxab w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxab w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldumaxlb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxlb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxlb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldumaxalb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxalb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxalb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldumaxah w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxah w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxah w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldumaxlh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxlh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxlh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldumaxalh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxalh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxalh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldumax w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumax x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumax x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldumaxa w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxa x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxa x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldumaxl w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxl x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxl x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldumaxal w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxal x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxal x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldumin w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumin w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumin w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldumina w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumina w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumina w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `lduminl w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminl w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminl w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `lduminal w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminal w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminal w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `lduminb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `lduminh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `lduminab w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminab w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminab w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `lduminlb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminlb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminlb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `lduminalb w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminalb w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminalb w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `lduminah w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminah w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminah w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `lduminlh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminlh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminlh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `lduminalh w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminalh w2,w3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminalh w2,w3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldumin w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumin x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumin x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `ldumina w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumina x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumina x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `lduminl w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminl x2,x3,\[w4\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminl x2,x3,\[w4\]' [^:]*:71: Error: operand mismatch -- `lduminal w0,x1,\[x2\]' -[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminal x2,x3,\[w4\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stadd w2,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `staddl w2,\[w3\]' +[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminal x2,x3,\[w4\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stadd w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `staddl w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `staddb x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `staddb w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `staddb w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `staddh x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `staddh w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `staddh w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `staddlb x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `staddlb w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `staddlb w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `staddlh x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `staddlh w2,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stadd x0,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `staddl x0,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclr w2,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclrl w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `staddlh w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stadd x0,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `staddl x0,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stclr w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stclrl w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stclrb x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclrb w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stclrb w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stclrh x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclrh w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stclrh w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stclrlb x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclrlb w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stclrlb w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stclrlh x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclrlh w2,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclr x0,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclrl x0,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steor w2,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steorl w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stclrlh w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stclr x0,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stclrl x0,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `steor w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `steorl w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `steorb x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steorb w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `steorb w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `steorh x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steorh w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `steorh w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `steorlb x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steorlb w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `steorlb w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `steorlh x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steorlh w2,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steor x0,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steorl x0,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stset w2,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsetl w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `steorlh w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `steor x0,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `steorl x0,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stset w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsetl w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stsetb x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsetb w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsetb w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stseth x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stseth w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stseth w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stsetlb x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsetlb w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsetlb w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stsetlh x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsetlh w2,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stset x0,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsetl x0,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmax w2,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmaxl w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsetlh w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stset x0,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsetl x0,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsmax w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxl w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stsmaxb x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmaxb w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxb w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stsmaxh x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmaxh w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxh w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stsmaxlb x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmaxlb w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxlb w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stsmaxlh x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmaxlh w2,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmax x0,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmaxl x0,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmin w2,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsminl w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxlh w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsmax x0,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxl x0,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsmin w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsminl w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stsminb x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsminb w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsminb w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stsminh x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsminh w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsminh w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stsminlb x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsminlb w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsminlb w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stsminlh x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsminlh w2,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmin x0,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsminl x0,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumax w2,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumaxl w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsminlh w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsmin x0,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsminl x0,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stumax w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxl w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stumaxb x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumaxb w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxb w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stumaxh x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumaxh w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxh w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stumaxlb x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumaxlb w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxlb w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stumaxlh x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumaxlh w2,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumax x0,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumaxl x0,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumin w2,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stuminl w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxlh w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stumax x0,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxl x0,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stumin w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stuminl w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stuminb x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stuminb w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stuminb w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stuminh x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stuminh w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stuminh w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stuminlb x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stuminlb w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stuminlb w2,\[w3\]' [^:]*:72: Error: operand mismatch -- `stuminlh x0,\[x2\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stuminlh w2,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumin x0,\[w3\]' -[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stuminl x0,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stuminlh w2,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stumin x0,\[w3\]' +[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stuminl x0,\[w3\]' |