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| author | Chris Demetriou <cgd@google.com> | 2002-06-14 18:49:09 +0000 |
|---|---|---|
| committer | Chris Demetriou <cgd@google.com> | 2002-06-14 18:49:09 +0000 |
| commit | e7e811813229598b44f7851121feddcffa911faa (patch) | |
| tree | 878c702920bc97142a3276e5697b9329eb64de2a /sim/mips/sim-main.h | |
| parent | ad2f7632f9c475a71481499715635ea3344b92d8 (diff) | |
| download | binutils-gdb-e7e811813229598b44f7851121feddcffa911faa.tar.gz | |
2002-06-14 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips3d.igen: New file which contains MIPS-3D ASE instructions.
* Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
* mips.igen: Include mips3d.igen.
(mips3d): New model name for MIPS-3D ASE instructions.
(CVT.W.fmt): Don't use this instruction for word (source) format
instructions.
* cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
(fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
(fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
(NR_FRAC_GUARD, IMPLICIT_1): New macros.
* sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
(RSquareRoot1, RSquareRoot2): New macros.
(fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
(fp_rsqrt2): New functions.
* configure.in: Add MIPS-3D support to mipsisa64 simulator.
* configure: Regenerate.
Diffstat (limited to 'sim/mips/sim-main.h')
| -rw-r--r-- | sim/mips/sim-main.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index 833fd5f9b01..fed625ecb54 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -82,6 +82,10 @@ typedef enum { fmt_uninterpreted_64 = 0x80000000U, } FP_formats; +/* For paired word (pw) operations, the opcode representation is fmt_word, + but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long. */ +#define fmt_pw fmt_long + /* This should be the COC1 value at the start of the preceding instruction: */ #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0) @@ -732,6 +736,23 @@ unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from, #define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to) +/* MIPS-3D ASE operations. */ +#define CompareAbs(op1,op2,fmt,cond,cc) \ +fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc) +unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +#define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt) +unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +#define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt) +unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt); +#define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt) +unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +#define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt) +unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt); +#define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt) +unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +#define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt) + + /* MDMX access. */ typedef unsigned int MX_fmtsel; /* MDMX format select field (5 bits). */ |