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| author | Mike Frysinger <vapier@gentoo.org> | 2011-03-15 03:16:17 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-03-15 03:16:17 +0000 |
| commit | 028f6515424e832ee10a1e4cb1f96ea241e2acae (patch) | |
| tree | c8ce68621a3ed2425b8dde4e2f523cbae0bf11fe /sim/common/sim-alu.h | |
| parent | 7f35e991971df570411a2688b948cd72adb4cf90 (diff) | |
| download | binutils-gdb-028f6515424e832ee10a1e4cb1f96ea241e2acae.tar.gz | |
sim: common: trim trailing whitespace
Diffstat (limited to 'sim/common/sim-alu.h')
| -rw-r--r-- | sim/common/sim-alu.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/sim/common/sim-alu.h b/sim/common/sim-alu.h index aeb994872b9..becc224a9c8 100644 --- a/sim/common/sim-alu.h +++ b/sim/common/sim-alu.h @@ -82,7 +82,7 @@ if (ALU16_HAD_OVERFLOW) \ sim_engine_halt (...); \ (RES) = ALU16_OVERFLOW_RESULT - + ALU*_HAD_CARRY_BORROW: Returns a nonzero value if unsigned overflow or underflow (also referred to as carry and borrow) occurred. @@ -93,8 +93,8 @@ #define ALU64_END(RES) \ State.carry = ALU64_HAD_CARRY_BORROW; \ (RES) = ALU64_CARRY_BORROW_RESULT - - + + Addition: ALU*_ADD(VAL): Add VAL to the ALU accumulator. Record any @@ -135,7 +135,7 @@ /* Twos complement arithmetic - addition/subtraction - carry/borrow (or you thought you knew the answer to 0-0) - + Notation and Properties: @@ -154,7 +154,7 @@ UMAXn: The upper bound of an unsigned N bit value (the lower bound is always zero). - Un: UMAXn + 1. Unsigned arithmetic is computed `modulo (Un)'. + Un: UMAXn + 1. Unsigned arithmetic is computed `modulo (Un)'. X[p]: Is bit P of X. X[0] denotes the least significant bit. @@ -193,7 +193,7 @@ The two N bit operands are sign extended to M>N bits and then added. Overflow occurs when SIGN_BIT<n> and SIGN_BIT<m> do not match. - + Rm = (SEXTn (Xn) + SEXTn (Yn)) V = MSBn ((Rm >> (M - N)) ^ Rm) @@ -241,7 +241,7 @@ The following table lists the output for all given inputs into a full-adder. - + I X Y R | C ------------+--- 0 0 0 0 | 0 @@ -264,7 +264,7 @@ XY\R 0 1 +------- - 00 | 0 0 + 00 | 0 0 01 | 1 0 11 | 1 1 10 | 1 0 @@ -275,7 +275,7 @@ Verifying: - I X Y R | C | X&Y X&~R Y&~R + I X Y R | C | X&Y X&~R Y&~R ------------+---+--------------- 0 0 0 0 | 0 | 0 0 0 0 0 1 1 | 0 | 0 0 0 |