diff options
| author | Alexandre Oliva <aoliva@redhat.com> | 2000-07-04 06:06:30 +0000 |
|---|---|---|
| committer | Alexandre Oliva <aoliva@redhat.com> | 2000-07-04 06:06:30 +0000 |
| commit | 4ef2594f4ed0fe4191d9e791e84b6241f968fc7c (patch) | |
| tree | 545186364e09c607b926694db19d6ec5755133f7 /sim/arm/armemu.c | |
| parent | 8de8f17e3d3138b6f1e31105823d8bb4efc66723 (diff) | |
| download | binutils-gdb-4ef2594f4ed0fe4191d9e791e84b6241f968fc7c.tar.gz | |
* armemu.h (PSR_FBITS, PSR_SBITS, PSR_XBITS, PSR_CBITS): New.
(SETPSR_F, SETPSR_S, SETPSR_X, SETPSR_C): New macros.
(SETPSR, SET_INTMODE, SETCC): Removed.
* armsupp.c (ARMul_FixCPSR, ARMul_FixSPSR): Do not test bit
mask. Use SETPSR_* to modify PSR.
(ARMul_SetCPSR): Load all bits from value.
* armemu.c (ARMul_Emulate, msr): Do not test bit mask.
Diffstat (limited to 'sim/arm/armemu.c')
| -rw-r--r-- | sim/arm/armemu.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c index ffdcaa72b95..373ec728473 100644 --- a/sim/arm/armemu.c +++ b/sim/arm/armemu.c @@ -1113,7 +1113,7 @@ ARMul_Emulate26 (register ARMul_State * state) } } #endif - if (DESTReg == 15 && BITS (17, 18) == 0) + if (DESTReg == 15) { /* MSR reg to CPSR */ UNDEF_MSRPC; temp = DPRegRHS; @@ -1241,7 +1241,7 @@ ARMul_Emulate26 (register ARMul_State * state) break; } #endif - if (DESTReg == 15 && BITS (17, 18) == 0) + if (DESTReg == 15) { /* MSR */ UNDEF_MSRPC; ARMul_FixSPSR (state, instr, DPRegRHS); @@ -1590,7 +1590,7 @@ ARMul_Emulate26 (register ARMul_State * state) break; case 0x32: /* TEQ immed and MSR immed to CPSR */ - if (DESTReg == 15 && BITS (17, 18) == 0) + if (DESTReg == 15) { /* MSR immed to CPSR */ ARMul_FixCPSR (state, instr, DPImmRHS); } @@ -1655,7 +1655,7 @@ ARMul_Emulate26 (register ARMul_State * state) break; case 0x36: /* CMN immed and MSR immed to SPSR */ - if (DESTReg == 15 && BITS (17, 18) == 0) /* MSR */ + if (DESTReg == 15) /* MSR */ ARMul_FixSPSR (state, instr, DPImmRHS); else { |