Add support for the MIPS eXtended Physical Address (XPA) ASE.

ChangeLog:

binutils/
	* doc/binutils.texi: Document the disassemble MIPS XPA instructions
	command line option.

gas/
	* config/tc-mips.c (options): Add OPTION_XPA and OPTION_NO_XPA.
 	(md_longopts): Add xpa and no-xpa command line options.
 	(mips_ases): Add MIPS XPA ASE.
 	(mips_cpu_info_table): Update p5600 entry to allow the XPA ASE.
 	* doc/as.texinfo: Document the MIPS XPA command line options.
 	* doc/c-mips.texi: Document the MIPS XPA command line options,
 	and assembler directives.

gas/testsuite/
 	* gas/mips/mips.exp: Add xpa tests.
 	* gas/mips/xpa.s: New test.
 	* gas/mips/xpa.d: Likewise.

include/
 	* opcode/mips.h (ASE_XPA): New define.

opcodes/
 	* mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
 	to allow the MIPS XPA ASE.
 	(parse_mips_dis_option): Process the -Mxpa option.
 	* mips-opc.c (XPA): New define.
 	(mips_builtin_opcodes): Add MIPS XPA instructions and move the
 	locations of the ctc0 and cfc0 instructions.

3 files changed, 40 insertions, 4 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index fda57ef1e49..62b96f2115b 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,12 @@
+2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+	* mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
+	to allow the MIPS XPA ASE.
+	(parse_mips_dis_option): Process the -Mxpa option.
+	* mips-opc.c (XPA): New define.
+	(mips_builtin_opcodes): Add MIPS XPA instructions and move the
+	locations of the ctc0 and cfc0 instructions.
+
 2014-04-22  Christian Svensson  <blue@cmd.nu>
 
 	* Makefile.am: Remove openrisc and or32 support.  Add support for or1k.
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 1de2ca3b20e..0f8624efa2c 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -551,7 +551,7 @@ const struct mips_arch_choice mips_arch_choices[] =
   { "mips32r2",	1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
     ISA_MIPS32R2,
     (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
-     | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA),
+     | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA),
     mips_cp0_names_mips3264r2,
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
     mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
@@ -566,7 +566,7 @@ const struct mips_arch_choice mips_arch_choices[] =
   { "mips64r2",	1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
     ISA_MIPS64R2,
     (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
-     | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64),
+     | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA),
     mips_cp0_names_mips3264r2,
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
     mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
@@ -810,6 +810,13 @@ parse_mips_dis_option (const char *option, unsigned int len)
 	mips_ase |= ASE_VIRT64;
       return;
     }
+
+  if (CONST_STRNEQ (option, "xpa"))
+    {
+      mips_ase |= ASE_XPA;
+      return;
+    }
+  
   
   /* Look for the = that delimits the end of the option name.  */
   for (i = 0; i < len; i++)
@@ -2196,6 +2203,9 @@ with the -M switch (multiple options should be separated by commas):\n"));
   virt            Recognize the virtualization ASE instructions.\n"));
 
   fprintf (stream, _("\n\
+  xpa            Recognize the eXtended Physical Address (XPA) ASE instructions.\n"));
+
+  fprintf (stream, _("\n\
   gpr-names=ABI            Print GPR names according to  specified ABI.\n\
                            Default: based on binary being disassembled.\n"));
 
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 8e26f48ccab..9181c3f5444 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -359,6 +359,9 @@ decode_mips_operand (const char *p)
 #define MSA	ASE_MSA
 #define MSA64	ASE_MSA64
 
+/* eXtended Physical Address (XPA) support.  */
+#define XPA     ASE_XPA
+
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
    for arguments must apear in the correct order in this table for the
@@ -895,7 +898,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ceil.l.s",		"D,S",		0x4600000a, 0xffff003f, WR_1|RD_2|FP_S|FP_D,	0,		I3_33,		0,	0 },
 {"ceil.w.d",		"D,S",		0x4620000e, 0xffff003f, WR_1|RD_2|FP_S|FP_D,	0,		I2,		0,	SF },
 {"ceil.w.s",		"D,S",		0x4600000e, 0xffff003f, WR_1|RD_2|FP_S,		0,		I2,		0,	EE },
-{"cfc0",		"t,G",		0x40400000, 0xffe007ff,	WR_1|RD_C0|LCD,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
+/* cfc0 is at the bottom of the table.  */
 {"cfc1",		"t,G",		0x44400000, 0xffe007ff,	WR_1|RD_C1|LCD|FP_S,	0,		I1,		0,	0 },
 {"cfc1",		"t,S",		0x44400000, 0xffe007ff,	WR_1|RD_C1|LCD|FP_S,	0,		I1,		0,	0 },
 /* cfc2 is at the bottom of the table.  */
@@ -908,7 +911,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"cins",		"t,r,+p,+S",	0x70000032, 0xfc00003f, WR_1|RD_2,		0,		IOCT,		0,	0 },
 {"clo",			"U,s",		0x70000021, 0xfc0007ff, WR_1|RD_2, 	0,		I32|N55,	0,	0 },
 {"clz",			"U,s",		0x70000020, 0xfc0007ff, WR_1|RD_2, 	0,		I32|N55,	0,	0 },
-{"ctc0",		"t,G",		0x40c00000, 0xffe007ff,	RD_1|WR_CC|COD,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
+/* ctc0 is at the bottom of the table.  */
 {"ctc1",		"t,G",		0x44c00000, 0xffe007ff,	RD_1|WR_CC|COD|FP_S,	0,		I1,		0,	0 },
 {"ctc1",		"t,S",		0x44c00000, 0xffe007ff,	RD_1|WR_CC|COD|FP_S,	0,		I1,		0,	0 },
 /* ctc2 is at the bottom of the table.  */
@@ -1300,6 +1303,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mfc0",		"t,G,H",	0x40000000, 0xffe007f8,	WR_1|RD_C0|LCD,		0,		I32,		0,	0 },
 {"mfgc0",		"t,G",		0x40600000, 0xffe007ff,	WR_1|RD_C0|LCD,		0,		0,		IVIRT,	0 },
 {"mfgc0",		"t,G,H",	0x40600000, 0xffe007f8, WR_1|RD_C0|LCD, 	0,		0,		IVIRT,	0 },
+{"mfhc0",		"t,G",		0x40400000, 0xffe007ff,	WR_1|RD_C0|LCD,		0,		I33,		XPA,	0 },
+{"mfhc0",		"t,G,H",	0x40400000, 0xffe007f8,	WR_1|RD_C0|LCD,		0,		I33,		XPA,	0 },
+{"mfhgc0",		"t,G",		0x40600400, 0xffe007ff,	WR_1|RD_C0|LCD,		0,		I33,		IVIRT|XPA,	0 },
+{"mfhgc0",		"t,G,H",	0x40600400, 0xffe007f8,	WR_1|RD_C0|LCD,		0,		I33,		IVIRT|XPA,	0 },
 {"mfc1",		"t,S",		0x44000000, 0xffe007ff,	WR_1|RD_2|LCD|FP_S,	0,		I1,		0,	0 },
 {"mfc1",		"t,G",		0x44000000, 0xffe007ff,	WR_1|RD_2|LCD|FP_S,	0,		I1,		0,	0 },
 {"mfhc1",		"t,S",		0x44600000, 0xffe007ff,	WR_1|RD_2|LCD|FP_D,	0,		I33,		0,	0 },
@@ -1393,6 +1400,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtc0",		"t,G,H",	0x40800000, 0xffe007f8,	RD_1|WR_C0|WR_CC|COD,	0,		I32,		0,	0 },
 {"mtgc0",		"t,G",		0x40600200, 0xffe007ff,	RD_1|WR_C0|WR_CC|COD,	0,		0,		IVIRT,	0 },
 {"mtgc0",		"t,G,H",	0x40600200, 0xffe007f8, RD_1|WR_C0|WR_CC|COD,   0,		0,		IVIRT,	0 },
+{"mthc0",		"t,G",		0x40c00000, 0xffe007ff,	RD_1|WR_C0|WR_CC|COD,	0,		I33,		XPA,	0 },
+{"mthc0",		"t,G,H",	0x40c00000, 0xffe007f8,	RD_1|WR_C0|WR_CC|COD,	0,		I33,		XPA,	0 },
+{"mthgc0",		"t,G",		0x40600600, 0xffe007ff,	RD_1|WR_C0|WR_CC|COD,	0,		I33,		IVIRT|XPA,	0 },
+{"mthgc0",		"t,G,H",	0x40600600, 0xffe007f8,	RD_1|WR_C0|WR_CC|COD,	0,		I33,		IVIRT|XPA,	0 },
 {"mtc1",		"t,S",		0x44800000, 0xffe007ff,	RD_1|WR_2|COD|FP_S,	0,		I1,		0,	0 },
 {"mtc1",		"t,G",		0x44800000, 0xffe007ff,	RD_1|WR_2|COD|FP_S,	0,		I1,		0,	0 },
 {"mthc1",		"t,S",		0x44e00000, 0xffe007ff,	RD_1|WR_2|COD|FP_D,	0,		I33,		0,	0 },
@@ -1954,6 +1965,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"zcb",			"(b)",		0x7000071f, 0xfc1fffff, RD_1|SM,		0,		IOCT2,		0,	0 },
 {"zcbt",		"(b)",		0x7000075f, 0xfc1fffff, RD_1|SM,		0,		IOCT2,		0,	0 },
 
+/* Coprocessor 0 move instructions cfc0 and ctc0 conflict with the 
+   mfhc0 and mthc0 XPA instructions, so they have been placed here 
+   to allow the XPA instructions to take precedence.  */
+{"ctc0",		"t,G",		0x40c00000, 0xffe007ff,	RD_1|WR_CC|COD,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
+{"cfc0",		"t,G",		0x40400000, 0xffe007ff,	WR_1|RD_C0|LCD,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
+
 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
    instructions so they are here for the latters to take precedence.  */
 {"bc2f",		"p",		0x49000000, 0xffff0000,	RD_CC|CBD,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },