diff options
| author | Peter Bergner <bergner@vnet.ibm.com> | 2016-06-03 18:38:02 -0500 |
|---|---|---|
| committer | Peter Bergner <bergner@vnet.ibm.com> | 2016-06-03 18:38:02 -0500 |
| commit | 026122a670440bc51266f8e013e5c5877c19b54e (patch) | |
| tree | c0b540c10fb4dd87e6af498158f9408d449958da /opcodes/ppc-opc.c | |
| parent | 07f5af7d3c635234284e7a0f7dd7a410b1628b8b (diff) | |
| download | binutils-gdb-026122a670440bc51266f8e013e5c5877c19b54e.tar.gz | |
Re-add support for lbarx, lharx, stbcx. and sthcx. insns back to the E6500 cpu.
opcodes/
PR binutils/20196
* ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
opcodes for E6500.
gas/
PR binutils/20196
* gas/testsuite/gas/ppc/e6500.s <lbarx, lharx, lwarx, ldarx,
stbcx., sthcx., stwcx., stdcx.>: Add tests.
* gas/testsuite/gas/ppc/e6500.d: Likewise.
* gas/testsuite/gas/ppc/power8.s: Likewise.
* gas/testsuite/gas/ppc/power8.d: Likewise.
* gas/testsuite/gas/ppc/power4.s <lwarx, ldarx, stwcx.,
stdcx.>: Add tests.
* gas/testsuite/gas/ppc/power4.d: Likewise.
Diffstat (limited to 'opcodes/ppc-opc.c')
| -rw-r--r-- | opcodes/ppc-opc.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index d73bca8852a..a5948e50b97 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -4824,7 +4824,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}}, {"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}}, -{"lbarx", X(31,52), XEH_MASK, POWER8|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, +{"lbarx", X(31,52), XEH_MASK, POWER8|E6500|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, {"ldux", X(31,53), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}}, @@ -4904,7 +4904,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}}, {"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, PPCNONE, {RA, XS6}}, -{"lharx", X(31,116), XEH_MASK, POWER8|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, +{"lharx", X(31,116), XEH_MASK, POWER8|E6500|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, {"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}}, @@ -5954,7 +5954,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, PPCNONE, {0}}, {"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, PPCNONE, {HTM_A}}, -{"stbcx.", XRC(31,694,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}}, +{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, PPCNONE, {RS, RA0, RB}}, {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, @@ -5986,7 +5986,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stswi", X(31,725), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RS, RA0, NB}}, {"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}}, -{"sthcx.", XRC(31,726,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}}, +{"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, PPCNONE, {RS, RA0, RB}}, {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, |