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| author | Andrew Bennett <andrew.bennett@imgtec.com> | 2014-04-23 11:24:30 +0100 |
|---|---|---|
| committer | Andrew Bennett <andrew.bennett@imgtec.com> | 2014-04-23 13:01:18 +0100 |
| commit | 7d64c587c15f290d228ca550bb288d53f0eb2ac4 (patch) | |
| tree | 72600357f6d2371bd27de80b4e69a4216855293a /opcodes/mips-dis.c | |
| parent | cd0449ab05e9045682a81bf521bd0c8732c98feb (diff) | |
| download | binutils-gdb-7d64c587c15f290d228ca550bb288d53f0eb2ac4.tar.gz | |
Add support for the MIPS eXtended Physical Address (XPA) ASE.
ChangeLog:
binutils/
* doc/binutils.texi: Document the disassemble MIPS XPA instructions
command line option.
gas/
* config/tc-mips.c (options): Add OPTION_XPA and OPTION_NO_XPA.
(md_longopts): Add xpa and no-xpa command line options.
(mips_ases): Add MIPS XPA ASE.
(mips_cpu_info_table): Update p5600 entry to allow the XPA ASE.
* doc/as.texinfo: Document the MIPS XPA command line options.
* doc/c-mips.texi: Document the MIPS XPA command line options,
and assembler directives.
gas/testsuite/
* gas/mips/mips.exp: Add xpa tests.
* gas/mips/xpa.s: New test.
* gas/mips/xpa.d: Likewise.
include/
* opcode/mips.h (ASE_XPA): New define.
opcodes/
* mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
to allow the MIPS XPA ASE.
(parse_mips_dis_option): Process the -Mxpa option.
* mips-opc.c (XPA): New define.
(mips_builtin_opcodes): Add MIPS XPA instructions and move the
locations of the ctc0 and cfc0 instructions.
Diffstat (limited to 'opcodes/mips-dis.c')
| -rw-r--r-- | opcodes/mips-dis.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 1de2ca3b20e..0f8624efa2c 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -551,7 +551,7 @@ const struct mips_arch_choice mips_arch_choices[] = { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, ISA_MIPS32R2, (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D - | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA), + | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, @@ -566,7 +566,7 @@ const struct mips_arch_choice mips_arch_choices[] = { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, ISA_MIPS64R2, (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT - | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64), + | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, @@ -810,6 +810,13 @@ parse_mips_dis_option (const char *option, unsigned int len) mips_ase |= ASE_VIRT64; return; } + + if (CONST_STRNEQ (option, "xpa")) + { + mips_ase |= ASE_XPA; + return; + } + /* Look for the = that delimits the end of the option name. */ for (i = 0; i < len; i++) @@ -2196,6 +2203,9 @@ with the -M switch (multiple options should be separated by commas):\n")); virt Recognize the virtualization ASE instructions.\n")); fprintf (stream, _("\n\ + xpa Recognize the eXtended Physical Address (XPA) ASE instructions.\n")); + + fprintf (stream, _("\n\ gpr-names=ABI Print GPR names according to specified ABI.\n\ Default: based on binary being disassembled.\n")); |