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| author | Jan Beulich <jbeulich@novell.com> | 2017-02-24 10:04:26 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2017-02-24 10:04:26 +0100 |
| commit | 7db2c58848ca683f3b09e687a9b012dbb49316af (patch) | |
| tree | b0f8ed4878288cbd67afa90decac70abcd26f8c9 /opcodes/i386-dis.c | |
| parent | 1b3cee563cafa73340314bbf32e4218dead72718 (diff) | |
| download | binutils-gdb-7db2c58848ca683f3b09e687a9b012dbb49316af.tar.gz | |
x86: also correctly support TEST opcode aliases
Opcodes F6/1 and F7/1 are aliases of F6/0 and F7/0 in all modes. This
complements commit 8b89fe14b5 ("X86: Decode opcode 0x82 as opcode 0x80
in 32-bit mode"), just that here 64-bit mode is also covered.
Diffstat (limited to 'opcodes/i386-dis.c')
| -rw-r--r-- | opcodes/i386-dis.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 108f0e3b236..2b61d4a1008 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -3511,7 +3511,7 @@ static const struct dis386 reg_table[][8] = { /* REG_F6 */ { { "testA", { Eb, Ib }, 0 }, - { Bad_Opcode }, + { "testA", { Eb, Ib }, 0 }, { "notA", { Ebh1 }, 0 }, { "negA", { Ebh1 }, 0 }, { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ @@ -3522,7 +3522,7 @@ static const struct dis386 reg_table[][8] = { /* REG_F7 */ { { "testQ", { Ev, Iv }, 0 }, - { Bad_Opcode }, + { "testQ", { Ev, Iv }, 0 }, { "notQ", { Evh1 }, 0 }, { "negQ", { Evh1 }, 0 }, { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ |