[ARM/STM32L4XX] PR 20030: --fix-stm32l4xx-629360 fails to create vldm/vpop veneers for double-precision registers

bfd/
	PR ld/20030
	* elf32-arm.c (is_thumb2_vldm): Account for T1 (DP) encoding.
	(stm32l4xx_need_create_replacing_stub): Rename ambiguous nb_regs
	to nb_words.
	(create_instruction_vldmia): Add is_dp to disambiguate SP/DP
	encoding.
	(create_instruction_vldmdb): Likewise.
	(stm32l4xx_create_replacing_stub_vldm): is_dp detects DP encoding,
	uses it to re-encode.

ld/
	PR ld/20030
	* testsuite/ld-arm/arm-elf.exp: Run new stm32l4xx-fix-vldm-dp
	tests. Fix misnamed stm32l4xx-fix-all.
	* testsuite/ld-arm/stm32l4xx-fix-vldm-dp.s: New tests for multiple
	loads with DP registers.
	* testsuite/ld-arm/stm32l4xx-fix-vldm-dp.d: New reference file.
	* testsuite/ld-arm/stm32l4xx-fix-vldm.s: Add missing comment.
	* testsuite/ld-arm/stm32l4xx-fix-all.s: Add tests for multiple
	loads with DP registers.
	* testsuite/ld-arm/stm32l4xx-fix-all.d: Update reference.

7 files changed, 155 insertions, 25 deletions

diff --git a/ld/ChangeLog b/ld/ChangeLog
index 2e07395c2d2..3188f29325a 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,16 @@
+2016-05-09  Christophe Monat  <christophe.monat@st.com>
+
+	PR ld/20030
+	* testsuite/ld-arm/arm-elf.exp: Run new stm32l4xx-fix-vldm-dp
+	tests. Fix misnamed stm32l4xx-fix-all.
+	* testsuite/ld-arm/stm32l4xx-fix-vldm-dp.s: New tests for multiple
+	loads with DP registers.
+	* testsuite/ld-arm/stm32l4xx-fix-vldm-dp.d: New reference file.
+	* testsuite/ld-arm/stm32l4xx-fix-vldm.s: Add missing comment.
+	* testsuite/ld-arm/stm32l4xx-fix-all.s: Add tests for multiple
+	loads with DP registers.
+	* testsuite/ld-arm/stm32l4xx-fix-all.d: Update reference.
+
 2016-05-09  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 
 	* testsuite/ld-elf/flags1.d (readelf): Dump section header instead
diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp
index 0af32c09e3d..fea70a18f41 100644
--- a/ld/testsuite/ld-arm/arm-elf.exp
+++ b/ld/testsuite/ld-arm/arm-elf.exp
@@ -167,10 +167,14 @@ set armelftests_common_1 {
      "-EL --fix-stm32l4xx-629360 -Ttext=0x8000" "" "-EL -mcpu=cortex-m4 -mfpu=fpv4-sp-d16" {stm32l4xx-fix-vldm.s}
      {{objdump -dr stm32l4xx-fix-vldm.d}}
      "stm32l4xx-fix-vldm"}
+    {"STM32L4XX erratum fix VLDM, DP registers"
+     "-EL --fix-stm32l4xx-629360 -Ttext=0x8000" "" "-EL -mcpu=cortex-m4 -mfpu=fpv4-sp-d16" {stm32l4xx-fix-vldm-dp.s}
+     {{objdump -dr stm32l4xx-fix-vldm-dp.d}}
+     "stm32l4xx-fix-vldm-dp"}
     {"STM32L4XX erratum fix ALL"
      "-EL --fix-stm32l4xx-629360=all -Ttext=0x8000" "" "-EL -mcpu=cortex-m4 -mfpu=fpv4-sp-d16" {stm32l4xx-fix-all.s}
      {{objdump -dr stm32l4xx-fix-all.d}}
-     "stm32l4xx-fix-vldm-all"}
+     "stm32l4xx-fix-all"}
     {"STM32L4XX erratum fix in IT context"
      "-EL --fix-stm32l4xx-629360 -Ttext=0x8000" "" "-EL -mcpu=cortex-m4 -mfpu=fpv4-sp-d16" {stm32l4xx-fix-it-block.s}
      {{objdump -dr stm32l4xx-fix-it-block.d}}
diff --git a/ld/testsuite/ld-arm/stm32l4xx-fix-all.d b/ld/testsuite/ld-arm/stm32l4xx-fix-all.d
index 59f3ed1c922..c67f95d2dd1 100644
--- a/ld/testsuite/ld-arm/stm32l4xx-fix-all.d
+++ b/ld/testsuite/ld-arm/stm32l4xx-fix-all.d
@@ -6,37 +6,37 @@ Disassembly of section \.text:
 
 00008000 <__stm32l4xx_veneer_0>:
     8000:	e899 01fe 	ldmia\.w	r9, {r1, r2, r3, r4, r5, r6, r7, r8}
-    8004:	f000 b84a 	b\.w	809c <__stm32l4xx_veneer_0_r>
+    8004:	f000 b86e 	b\.w	80e4 <__stm32l4xx_veneer_0_r>
     8008:	f7f0 a000 	udf\.w	#0
     800c:	f7f0 a000 	udf\.w	#0
 
 00008010 <__stm32l4xx_veneer_1>:
     8010:	e8b9 01fe 	ldmia\.w	r9!, {r1, r2, r3, r4, r5, r6, r7, r8}
-    8014:	f000 b844 	b\.w	80a0 <__stm32l4xx_veneer_1_r>
+    8014:	f000 b868 	b\.w	80e8 <__stm32l4xx_veneer_1_r>
     8018:	f7f0 a000 	udf\.w	#0
     801c:	f7f0 a000 	udf\.w	#0
 
 00008020 <__stm32l4xx_veneer_2>:
     8020:	e919 01fe 	ldmdb	r9, {r1, r2, r3, r4, r5, r6, r7, r8}
-    8024:	f000 b83e 	b\.w	80a4 <__stm32l4xx_veneer_2_r>
+    8024:	f000 b862 	b\.w	80ec <__stm32l4xx_veneer_2_r>
     8028:	f7f0 a000 	udf\.w	#0
     802c:	f7f0 a000 	udf\.w	#0
 
 00008030 <__stm32l4xx_veneer_3>:
     8030:	e939 01fe 	ldmdb	r9!, {r1, r2, r3, r4, r5, r6, r7, r8}
-    8034:	f000 b838 	b\.w	80a8 <__stm32l4xx_veneer_3_r>
+    8034:	f000 b85c 	b\.w	80f0 <__stm32l4xx_veneer_3_r>
     8038:	f7f0 a000 	udf\.w	#0
     803c:	f7f0 a000 	udf\.w	#0
 
 00008040 <__stm32l4xx_veneer_4>:
     8040:	e8bd 01fe 	ldmia\.w	sp!, {r1, r2, r3, r4, r5, r6, r7, r8}
-    8044:	f000 b832 	b\.w	80ac <__stm32l4xx_veneer_4_r>
+    8044:	f000 b856 	b\.w	80f4 <__stm32l4xx_veneer_4_r>
     8048:	f7f0 a000 	udf\.w	#0
     804c:	f7f0 a000 	udf\.w	#0
 
 00008050 <__stm32l4xx_veneer_5>:
     8050:	ecd9 0a08 	vldmia	r9, {s1-s8}
-    8054:	f000 b82c 	b\.w	80b0 <__stm32l4xx_veneer_5_r>
+    8054:	f000 b850 	b\.w	80f8 <__stm32l4xx_veneer_5_r>
     8058:	f7f0 a000 	udf\.w	#0
     805c:	f7f0 a000 	udf\.w	#0
     8060:	f7f0 a000 	udf\.w	#0
@@ -44,7 +44,7 @@ Disassembly of section \.text:
 
 00008068 <__stm32l4xx_veneer_6>:
     8068:	ecf6 4a08 	vldmia	r6!, {s9-s16}
-    806c:	f000 b822 	b\.w	80b4 <__stm32l4xx_veneer_6_r>
+    806c:	f000 b846 	b\.w	80fc <__stm32l4xx_veneer_6_r>
     8070:	f7f0 a000 	udf\.w	#0
     8074:	f7f0 a000 	udf\.w	#0
     8078:	f7f0 a000 	udf\.w	#0
@@ -52,32 +52,65 @@ Disassembly of section \.text:
 
 00008080 <__stm32l4xx_veneer_7>:
     8080:	ecfd 0a08 	vpop	{s1-s8}
-    8084:	f000 b818 	b\.w	80b8 <__stm32l4xx_veneer_7_r>
+    8084:	f000 b83c 	b\.w	8100 <__stm32l4xx_veneer_7_r>
     8088:	f7f0 a000 	udf\.w	#0
     808c:	f7f0 a000 	udf\.w	#0
     8090:	f7f0 a000 	udf\.w	#0
     8094:	f7f0 a000 	udf\.w	#0
 
-00008098 <_start>:
-    8098:	f7ff bfb2 	b\.w	8000 <__stm32l4xx_veneer_0>
+00008098 <__stm32l4xx_veneer_8>:
+    8098:	ec99 1b08 	vldmia	r9, {d1-d4}
+    809c:	f000 b832 	b\.w	8104 <__stm32l4xx_veneer_8_r>
+    80a0:	f7f0 a000 	udf\.w	#0
+    80a4:	f7f0 a000 	udf\.w	#0
+    80a8:	f7f0 a000 	udf\.w	#0
+    80ac:	f7f0 a000 	udf\.w	#0
 
-0000809c <__stm32l4xx_veneer_0_r>:
-    809c:	f7ff bfb8 	b\.w	8010 <__stm32l4xx_veneer_1>
+000080b0 <__stm32l4xx_veneer_9>:
+    80b0:	ecb6 8b08 	vldmia	r6!, {d8-d11}
+    80b4:	f000 b828 	b\.w	8108 <__stm32l4xx_veneer_9_r>
+    80b8:	f7f0 a000 	udf\.w	#0
+    80bc:	f7f0 a000 	udf\.w	#0
+    80c0:	f7f0 a000 	udf\.w	#0
+    80c4:	f7f0 a000 	udf\.w	#0
 
-000080a0 <__stm32l4xx_veneer_1_r>:
-    80a0:	f7ff bfbe 	b\.w	8020 <__stm32l4xx_veneer_2>
+000080c8 <__stm32l4xx_veneer_a>:
+    80c8:	ecbd 1b08 	vpop	{d1-d4}
+    80cc:	f000 b81e 	b\.w	810c <__stm32l4xx_veneer_a_r>
+    80d0:	f7f0 a000 	udf\.w	#0
+    80d4:	f7f0 a000 	udf\.w	#0
+    80d8:	f7f0 a000 	udf\.w	#0
+    80dc:	f7f0 a000 	udf\.w	#0
 
-000080a4 <__stm32l4xx_veneer_2_r>:
-    80a4:	f7ff bfc4 	b\.w	8030 <__stm32l4xx_veneer_3>
+000080e0 <_start>:
+    80e0:	f7ff bf8e 	b\.w	8000 <__stm32l4xx_veneer_0>
 
-000080a8 <__stm32l4xx_veneer_3_r>:
-    80a8:	f7ff bfca 	b\.w	8040 <__stm32l4xx_veneer_4>
+000080e4 <__stm32l4xx_veneer_0_r>:
+    80e4:	f7ff bf94 	b\.w	8010 <__stm32l4xx_veneer_1>
 
-000080ac <__stm32l4xx_veneer_4_r>:
-    80ac:	f7ff bfd0 	b\.w	8050 <__stm32l4xx_veneer_5>
+000080e8 <__stm32l4xx_veneer_1_r>:
+    80e8:	f7ff bf9a 	b\.w	8020 <__stm32l4xx_veneer_2>
 
-000080b0 <__stm32l4xx_veneer_5_r>:
-    80b0:	f7ff bfda 	b\.w	8068 <__stm32l4xx_veneer_6>
+000080ec <__stm32l4xx_veneer_2_r>:
+    80ec:	f7ff bfa0 	b\.w	8030 <__stm32l4xx_veneer_3>
 
-000080b4 <__stm32l4xx_veneer_6_r>:
-    80b4:	f7ff bfe4 	b\.w	8080 <__stm32l4xx_veneer_7>
+000080f0 <__stm32l4xx_veneer_3_r>:
+    80f0:	f7ff bfa6 	b\.w	8040 <__stm32l4xx_veneer_4>
+
+000080f4 <__stm32l4xx_veneer_4_r>:
+    80f4:	f7ff bfac 	b\.w	8050 <__stm32l4xx_veneer_5>
+
+000080f8 <__stm32l4xx_veneer_5_r>:
+    80f8:	f7ff bfb6 	b\.w	8068 <__stm32l4xx_veneer_6>
+
+000080fc <__stm32l4xx_veneer_6_r>:
+    80fc:	f7ff bfc0 	b\.w	8080 <__stm32l4xx_veneer_7>
+
+00008100 <__stm32l4xx_veneer_7_r>:
+    8100:	f7ff bfca 	b\.w	8098 <__stm32l4xx_veneer_8>
+
+00008104 <__stm32l4xx_veneer_8_r>:
+    8104:	f7ff bfd4 	b\.w	80b0 <__stm32l4xx_veneer_9>
+
+00008108 <__stm32l4xx_veneer_9_r>:
+    8108:	f7ff bfde 	b\.w	80c8 <__stm32l4xx_veneer_a>
diff --git a/ld/testsuite/ld-arm/stm32l4xx-fix-all.s b/ld/testsuite/ld-arm/stm32l4xx-fix-all.s
index 0c1826670ff..580e5b2e29b 100644
--- a/ld/testsuite/ld-arm/stm32l4xx-fix-all.s
+++ b/ld/testsuite/ld-arm/stm32l4xx-fix-all.s
@@ -20,3 +20,6 @@ _start:
         vldm r9, {s1-s8}
         vldm r6!, {s9-s16}
         vpop {s1-s8}
+        vldm r9, {d1-d4}
+        vldm r6!, {d8-d11}
+        vpop {d1-d4}
diff --git a/ld/testsuite/ld-arm/stm32l4xx-fix-vldm-dp.d b/ld/testsuite/ld-arm/stm32l4xx-fix-vldm-dp.d
new file mode 100644
index 00000000000..cd7de14b0d6
--- /dev/null
+++ b/ld/testsuite/ld-arm/stm32l4xx-fix-vldm-dp.d
@@ -0,0 +1,49 @@
+
+.*:     file format elf32-littlearm.*
+
+
+Disassembly of section \.text:
+
+00008000 <__stm32l4xx_veneer_0>:
+    8000:	ecba 1b08 	vldmia	sl!, {d1-d4}
+    8004:	ecba 5b08 	vldmia	sl!, {d5-d8}
+    8008:	ecba 9b08 	vldmia	sl!, {d9-d12}
+    800c:	ecba db06 	vldmia	sl!, {d13-d15}
+    8010:	f1aa 0a78 	sub\.w	sl, sl, #120	; 0x78
+    8014:	f000 b826 	b\.w	8064 <__stm32l4xx_veneer_0_r>
+
+00008018 <__stm32l4xx_veneer_1>:
+    8018:	ecb7 5b08 	vldmia	r7!, {d5-d8}
+    801c:	ecb7 9b08 	vldmia	r7!, {d9-d12}
+    8020:	ecb7 db06 	vldmia	r7!, {d13-d15}
+    8024:	f000 b820 	b\.w	8068 <__stm32l4xx_veneer_1_r>
+    8028:	f7f0 a000 	udf\.w	#0
+    802c:	f7f0 a000 	udf\.w	#0
+
+00008030 <__stm32l4xx_veneer_2>:
+    8030:	ecbd 1b08 	vpop	{d1-d4}
+    8034:	ecbd 5b02 	vpop	{d5}
+    8038:	f000 b818 	b\.w	806c <__stm32l4xx_veneer_2_r>
+    803c:	f7f0 a000 	udf\.w	#0
+    8040:	f7f0 a000 	udf\.w	#0
+    8044:	f7f0 a000 	udf\.w	#0
+
+00008048 <__stm32l4xx_veneer_3>:
+    8048:	ed3c 1b08 	vldmdb	ip!, {d1-d4}
+    804c:	ed3c 5b08 	vldmdb	ip!, {d5-d8}
+    8050:	ed3c 9b08 	vldmdb	ip!, {d9-d12}
+    8054:	ed3c db06 	vldmdb	ip!, {d13-d15}
+    8058:	f000 b80a 	b\.w	8070 <__stm32l4xx_veneer_3_r>
+    805c:	f7f0 a000 	udf\.w	#0
+
+00008060 <_start>:
+    8060:	f7ff bfce 	b\.w	8000 <__stm32l4xx_veneer_0>
+
+00008064 <__stm32l4xx_veneer_0_r>:
+    8064:	f7ff bfd8 	b\.w	8018 <__stm32l4xx_veneer_1>
+
+00008068 <__stm32l4xx_veneer_1_r>:
+    8068:	f7ff bfe2 	b\.w	8030 <__stm32l4xx_veneer_2>
+
+0000806c <__stm32l4xx_veneer_2_r>:
+    806c:	f7ff bfec 	b\.w	8048 <__stm32l4xx_veneer_3>
diff --git a/ld/testsuite/ld-arm/stm32l4xx-fix-vldm-dp.s b/ld/testsuite/ld-arm/stm32l4xx-fix-vldm-dp.s
new file mode 100644
index 00000000000..7c7ce018a16
--- /dev/null
+++ b/ld/testsuite/ld-arm/stm32l4xx-fix-vldm-dp.s
@@ -0,0 +1,27 @@
+        .syntax unified
+        .cpu cortex-m4
+        .fpu fpv4-sp-d16
+        .text
+        .align  1
+        .thumb
+        .thumb_func
+        .global _start
+_start:
+        @ VLDM CASE #1
+        @ vldm rx, {...}
+        @ -> vldm rx!, {8_words_or_less} for each
+        @ -> sub rx, rx, #size (list)
+        vldm r10, {d1-d15}
+
+        @ VLDM CASE #2
+        @ vldm rx!, {...}
+        @ -> vldm rx!, {8_words_or_less} for each needed 8_word
+        @ This also handles vpop instruction (when rx is sp)
+        vldm r7!, {d5-d15}
+        @ Explicit VPOP test
+        vpop {d1-d5}
+
+        @ VLDM CASE #3
+        @ vldmd rx!, {...}
+        @ -> vldmb rx!, {8_words_or_less} for each needed 8_word
+        vldmdb r12!, {d1-d15}
diff --git a/ld/testsuite/ld-arm/stm32l4xx-fix-vldm.s b/ld/testsuite/ld-arm/stm32l4xx-fix-vldm.s
index 94aa66e6d3b..b0728016fda 100644
--- a/ld/testsuite/ld-arm/stm32l4xx-fix-vldm.s
+++ b/ld/testsuite/ld-arm/stm32l4xx-fix-vldm.s
@@ -21,6 +21,7 @@ _start:
         @ Explicit VPOP test
         vpop {s1-s9}
 
+        @ VLDM CASE #3
         @ vldmd rx!, {...}
         @ -> vldmb rx!, {8_words_or_less} for each needed 8_word
         vldmdb r11!, {s1-s31}