diff options
| author | Siddhesh Poyarekar <siddesh.poyarekar@arm.com> | 2020-09-11 09:18:07 +0530 |
|---|---|---|
| committer | Luis Machado <luis.machado@linaro.org> | 2020-10-20 15:03:26 -0300 |
| commit | f7d2c6754aee4a080108521badd7cad1423b1bae (patch) | |
| tree | c1895cbc2b19e3c7bcd7c454e3ddfcb50eb060d2 /include | |
| parent | e9af8aad338694e2c3c000b47b67dc7c4e5f2a3c (diff) | |
| download | binutils-gdb-f7d2c6754aee4a080108521badd7cad1423b1bae.tar.gz | |
[Morello] LDR immediate
The 17-bit signed offset needs to be 16-byte aligned, but the
PCC-relative address resolution rounds down the final address to the
16-byte boundary. Due to this, disassembly of the instruction will
show as if it is loading from the middle of an object.
bfd/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* elfnn-aarch64.c (elfNN_aarch64_howto_table): Add
LD_PREL_LO17.
(elfNN_aarch64_final_link_relocate,
elfNN_aarch64_check_relocs): Likewise.
* elfxx-aarch64.c (reencode_ld_lit_ofs_17): New function.
(_bfd_aarch64_elf_put_addend,
_bfd_aarch64_elf_resolve_relocation): Add LD_PREL_LO17.
* libbfd.h (bfd_reloc_code_real_names): Add
BFD_RELOC_MORELLO_LD_LO17_PCREL.
* reloc.c: Add BFD_RELOC_AARCH64_LD_LO17_PCREL.
* bfd-in2.h: Regenerate.
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (encode_ld_lit_ofs_17): New function.
(parse_operands, programmer_friendly_fixup, md_apply_fix): Add
ADDR_PCREL17.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* elf/aarch64.h: New relocation R_MORELLO_LD_PREL_LO17.
* opcode/aarch64.h (aarch64_opnd): Add ADDR_PCREL17.
(aarch64_op): Add OP_LDR_LIT_2.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-opc.c (fields): Add imm17.
(operand_general_constraint_met_p, aarch64_print_operand): Add
ADDR_PCREL17.
* aarch64-opc.h (aarch64_field_kind): Add FLD_imm17.
* aarch64-tbl.h (QL2_A64C_CA_PCREL): New macro.
(aarch64_opcode_table): New instruction.
(AARCH64_OPERANDS): New operand.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 6 | ||||
| -rw-r--r-- | include/elf/aarch64.h | 5 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 2 |
3 files changed, 13 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index d1d009f6183..3fc617515d3 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,5 +1,11 @@ 2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com> + * elf/aarch64.h: New relocation R_MORELLO_LD_PREL_LO17. + * opcode/aarch64.h (aarch64_opnd): Add ADDR_PCREL17. + (aarch64_op): Add OP_LDR_LIT_2. + +2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com> + * opcode/aarch64.h (aarch64_opnd): Add A64C_ADDR_SIMM7. 2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com> diff --git a/include/elf/aarch64.h b/include/elf/aarch64.h index c55e74026b8..f69dcbb72ab 100644 --- a/include/elf/aarch64.h +++ b/include/elf/aarch64.h @@ -442,6 +442,11 @@ RELOC_NUMBER (R_AARCH64_TLS_TPREL, 1030) RELOC_NUMBER (R_AARCH64_TLSDESC, 1031) RELOC_NUMBER (R_AARCH64_IRELATIVE, 1032) +/* Morello Relocations. */ + +/* A64C LD-lit: ((S+A-P) >> 4) & 0x1ffff */ +RELOC_NUMBER (R_MORELLO_LD_PREL_LO17, 57348) + END_RELOC_NUMBERS (R_AARCH64_end) enum aarch64_st_branch_type diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 9574b3925bf..4c0da7f2c04 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -468,6 +468,7 @@ enum aarch64_opnd BLR/BR. */ AARCH64_OPND_CAPADDR_SIMPLE, /* Simple base address with no offset. */ AARCH64_OPND_A64C_ADDR_SIMM7, /* Address with 7-bit immediate offset. */ + AARCH64_OPND_ADDR_PCREL17, /* 17-bit PC-relative address for e.g. LDR. */ }; /* Qualifier constrains an operand. It either specifies a variant of an @@ -694,6 +695,7 @@ enum aarch64_op OP_PRFUM, OP_LDR_LIT, + OP_LDR_LIT_2, OP_LDRV_LIT, OP_LDRSW_LIT, OP_PRFM_LIT, |