diff options
| author | Daniel Jacobowitz <drow@false.org> | 2007-10-15 19:27:25 +0000 |
|---|---|---|
| committer | Daniel Jacobowitz <drow@false.org> | 2007-10-15 19:27:25 +0000 |
| commit | 8dc35b87076f7ffa5370932e054f0336aa01f122 (patch) | |
| tree | 0fc5ce0e68c5b49f7ddeaefc7083975690930041 /gdb/features/rs6000/power-altivec.xml | |
| parent | 81adfcedc899da6e7641d2c2d6aad68f60d97735 (diff) | |
| download | binutils-gdb-8dc35b87076f7ffa5370932e054f0336aa01f122.tar.gz | |
* features/rs6000/power-altivec.xml, features/rs6000/power-core.xml,
features/rs6000/power-fpu.xml, features/rs6000/power-oea.xml,
features/rs6000/power-spe.xml, features/rs6000/power64-core.xml: New
feature descriptions for standard PowerPC register sets.
* features/rs6000/powerpc-32.xml, features/rs6000/powerpc-403.xml,
features/rs6000/powerpc-403gc.xml, features/rs6000/powerpc-505.xml,
features/rs6000/powerpc-601.xml, features/rs6000/powerpc-602.xml,
features/rs6000/powerpc-603.xml, features/rs6000/powerpc-604.xml,
features/rs6000/powerpc-64.xml, features/rs6000/powerpc-7400.xml,
features/rs6000/powerpc-750.xml, features/rs6000/powerpc-860.xml,
features/rs6000/powerpc-e500.xml, features/rs6000/rs6000.xml: New
target descriptions for PowerPC processors.
Diffstat (limited to 'gdb/features/rs6000/power-altivec.xml')
| -rw-r--r-- | gdb/features/rs6000/power-altivec.xml | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/gdb/features/rs6000/power-altivec.xml b/gdb/features/rs6000/power-altivec.xml new file mode 100644 index 00000000000..cd326a74982 --- /dev/null +++ b/gdb/features/rs6000/power-altivec.xml @@ -0,0 +1,57 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2007 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.power.altivec"> + <vector id="v4f" type="ieee_single" count="4"/> + <vector id="v4i32" type="int32" count="4"/> + <vector id="v8i16" type="int16" count="8"/> + <vector id="v16i8" type="int8" count="16"/> + <union id="vec128"> + <field name="uint128" type="uint128"/> + <field name="v4_float" type="v4f"/> + <field name="v4_int32" type="v4i32"/> + <field name="v8_int16" type="v8i16"/> + <field name="v16_int8" type="v16i8"/> + </union> + + <reg name="vr0" bitsize="128" type="vec128"/> + <reg name="vr1" bitsize="128" type="vec128"/> + <reg name="vr2" bitsize="128" type="vec128"/> + <reg name="vr3" bitsize="128" type="vec128"/> + <reg name="vr4" bitsize="128" type="vec128"/> + <reg name="vr5" bitsize="128" type="vec128"/> + <reg name="vr6" bitsize="128" type="vec128"/> + <reg name="vr7" bitsize="128" type="vec128"/> + <reg name="vr8" bitsize="128" type="vec128"/> + <reg name="vr9" bitsize="128" type="vec128"/> + <reg name="vr10" bitsize="128" type="vec128"/> + <reg name="vr11" bitsize="128" type="vec128"/> + <reg name="vr12" bitsize="128" type="vec128"/> + <reg name="vr13" bitsize="128" type="vec128"/> + <reg name="vr14" bitsize="128" type="vec128"/> + <reg name="vr15" bitsize="128" type="vec128"/> + <reg name="vr16" bitsize="128" type="vec128"/> + <reg name="vr17" bitsize="128" type="vec128"/> + <reg name="vr18" bitsize="128" type="vec128"/> + <reg name="vr19" bitsize="128" type="vec128"/> + <reg name="vr20" bitsize="128" type="vec128"/> + <reg name="vr21" bitsize="128" type="vec128"/> + <reg name="vr22" bitsize="128" type="vec128"/> + <reg name="vr23" bitsize="128" type="vec128"/> + <reg name="vr24" bitsize="128" type="vec128"/> + <reg name="vr25" bitsize="128" type="vec128"/> + <reg name="vr26" bitsize="128" type="vec128"/> + <reg name="vr27" bitsize="128" type="vec128"/> + <reg name="vr28" bitsize="128" type="vec128"/> + <reg name="vr29" bitsize="128" type="vec128"/> + <reg name="vr30" bitsize="128" type="vec128"/> + <reg name="vr31" bitsize="128" type="vec128"/> + + <reg name="vscr" bitsize="32" group="vector"/> + <reg name="vrsave" bitsize="32" group="vector"/> +</feature> |