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authorJose E. Marchesi <jose.marchesi@oracle.com>2016-06-17 02:14:18 -0700
committerJose E. Marchesi <jose.marchesi@oracle.com>2016-06-17 02:14:18 -0700
commit7a10c22feb4dfb7e56855033d579338a6258722d (patch)
tree2960bcb39684b58b8e4a70384912c3c94484657f /gas
parent8b8c7c9f49992750f66f81b4601d593a3858d98c (diff)
downloadbinutils-gdb-7a10c22feb4dfb7e56855033d579338a6258722d.tar.gz
opcodes,gas: adjust sparc insns and make GAS aware of it
This patch marks the SPARC instructions in the opcodes table with their proper opcode architectures, and makes the assembler aware of them. This allows the assembler to properly realize when a new instruction needs a higher architecture (after v9b) and to react accordingly emitting an error message or bumping the architecture. It also expands architecture mismatch tests to cover architectures higher than v9b, and fixes a couple of minor bugs in the GAS testsuite. opcodes/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-opc.c (sparc_opcodes): Adjust instructions opcode architecture according to the hardware capabilities they require. (sparc_priv_regs): New table. (sparc_hpriv_regs): Likewise. (sparc_asr_regs): Likewise. (v9anotv9m): Define. gas/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (sparc_arch_table): adjust the GAS architectures to use the right opcode architecture. (sparc_md_end): Handle v9{c,d,e,v,m}. (sparc_ip): Fix some comments. * testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this instruction, which is v9d. * testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1' instruction from the test, as %mwait is not readable. * testsuite/gas/sparc/mwait.d: Likewise. * testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e mismatch architecture errors. * testsuite/gas/sparc/mism-2.s: New file.
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog15
-rw-r--r--gas/config/tc-sparc.c40
-rw-r--r--gas/testsuite/gas/sparc/ldx_efsr.d4
-rw-r--r--gas/testsuite/gas/sparc/mism-1.s7
-rw-r--r--gas/testsuite/gas/sparc/mism-2.s23
-rw-r--r--gas/testsuite/gas/sparc/mwait.d7
-rw-r--r--gas/testsuite/gas/sparc/mwait.s1
7 files changed, 75 insertions, 22 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index e183c112f31..22017c4841d 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,20 @@
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
+ * config/tc-sparc.c (sparc_arch_table): adjust the GAS
+ architectures to use the right opcode architecture.
+ (sparc_md_end): Handle v9{c,d,e,v,m}.
+ (sparc_ip): Fix some comments.
+ * testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
+ instruction, which is v9d.
+ * testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
+ instruction from the test, as %mwait is not readable.
+ * testsuite/gas/sparc/mwait.d: Likewise.
+ * testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
+ mismatch architecture errors.
+ * testsuite/gas/sparc/mism-2.s: New file.
+
+2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
+
* config/tc-sparc.c (priv_reg_table): Use NULL instead of the
empty string to mark the end of the array.
(hpriv_reg_table): Likewise.
diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c
index c8076bf1918..283e1323f91 100644
--- a/gas/config/tc-sparc.c
+++ b/gas/config/tc-sparc.c
@@ -264,8 +264,8 @@ static struct sparc_arch {
{ "sparcvis3", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC, 0 },
{ "sparcvis3r", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_FJFMAU, 0 },
- { "sparc4", "v9b", v9, 0, 1, HWS_VV, 0 },
- { "sparc5", "v9b", v9, 0, 1, HWS_VM, HWS2_VM },
+ { "sparc4", "v9v", v9, 0, 1, HWS_VV, 0 },
+ { "sparc5", "v9m", v9, 0, 1, HWS_VM, HWS2_VM },
{ "leon", "leon", leon, 32, 1, HWS_V8, 0 },
{ "sparclet", "sparclet", sparclet, 32, 1, HWS_V8, 0 },
@@ -275,20 +275,20 @@ static struct sparc_arch {
{ "v8plus", "v9", v9, 0, 1, HWCAP_V8PLUS|HWS_V9, 0 },
{ "v8plusa", "v9a", v9, 0, 1, HWCAP_V8PLUS|HWS_VA, 0 },
{ "v8plusb", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VB, 0 },
- { "v8plusc", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VC, 0 },
- { "v8plusd", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VD, 0 },
- { "v8pluse", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VE, 0 },
- { "v8plusv", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VV, 0 },
- { "v8plusm", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VM, 0 },
+ { "v8plusc", "v9c", v9, 0, 1, HWCAP_V8PLUS|HWS_VC, 0 },
+ { "v8plusd", "v9d", v9, 0, 1, HWCAP_V8PLUS|HWS_VD, 0 },
+ { "v8pluse", "v9e", v9, 0, 1, HWCAP_V8PLUS|HWS_VE, 0 },
+ { "v8plusv", "v9v", v9, 0, 1, HWCAP_V8PLUS|HWS_VV, 0 },
+ { "v8plusm", "v9m", v9, 0, 1, HWCAP_V8PLUS|HWS_VM, 0 },
{ "v9", "v9", v9, 0, 1, HWS_V9, 0 },
{ "v9a", "v9a", v9, 0, 1, HWS_VA, 0 },
{ "v9b", "v9b", v9, 0, 1, HWS_VB, 0 },
- { "v9c", "v9b", v9, 0, 1, HWS_VC, 0 },
- { "v9d", "v9b", v9, 0, 1, HWS_VD, 0 },
- { "v9e", "v9b", v9, 0, 1, HWS_VE, 0 },
- { "v9v", "v9b", v9, 0, 1, HWS_VV, 0 },
- { "v9m", "v9b", v9, 0, 1, HWS_VM, HWS2_VM },
+ { "v9c", "v9c", v9, 0, 1, HWS_VC, 0 },
+ { "v9d", "v9d", v9, 0, 1, HWS_VD, 0 },
+ { "v9e", "v9e", v9, 0, 1, HWS_VE, 0 },
+ { "v9v", "v9v", v9, 0, 1, HWS_VV, 0 },
+ { "v9m", "v9m", v9, 0, 1, HWS_VM, HWS2_VM },
/* This exists to allow configure.tgt to pass one
value to specify both the default machine and default word size. */
@@ -1152,6 +1152,11 @@ sparc_md_end (void)
{
case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
+ case SPARC_OPCODE_ARCH_V9C: mach = bfd_mach_sparc_v9c; break;
+ case SPARC_OPCODE_ARCH_V9D: mach = bfd_mach_sparc_v9d; break;
+ case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v9e; break;
+ case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v9v; break;
+ case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v9m; break;
default: mach = bfd_mach_sparc_v9; break;
}
else
@@ -1161,6 +1166,11 @@ sparc_md_end (void)
case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
+ case SPARC_OPCODE_ARCH_V9C: mach = bfd_mach_sparc_v8plusc; break;
+ case SPARC_OPCODE_ARCH_V9D: mach = bfd_mach_sparc_v8plusd; break;
+ case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v8pluse; break;
+ case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v8plusv; break;
+ case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v8plusm; break;
/* The sparclite is treated like a normal sparc. Perhaps it shouldn't
be but for now it is (since that's the way it's always been
treated). */
@@ -1947,7 +1957,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
case '_':
case '/':
- /* Parse a v9a/v9b ancillary state register. */
+ /* Parse a v9a or later ancillary state register. */
if (*s == '%')
{
struct priv_reg_entry *p;
@@ -1964,7 +1974,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
if (!p->name)
{
- error_message = _(": unrecognizable v9a or v9b ancillary state register");
+ error_message = _(": unrecognizable ancillary state register");
goto error;
}
if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
@@ -1989,7 +1999,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
}
else
{
- error_message = _(": unrecognizable v9a or v9b ancillary state register");
+ error_message = _(": unrecognizable ancillary state register");
goto error;
}
diff --git a/gas/testsuite/gas/sparc/ldx_efsr.d b/gas/testsuite/gas/sparc/ldx_efsr.d
index 63ddcb61d23..6cf63fcff31 100644
--- a/gas/testsuite/gas/sparc/ldx_efsr.d
+++ b/gas/testsuite/gas/sparc/ldx_efsr.d
@@ -1,5 +1,5 @@
-#as: -Av9b
-#objdump: -dr -m sparc:v9b
+#as: -Av9d
+#objdump: -dr -m sparc:v9d
#name: sparc LDXEFSR
.*: +file format .*sparc.*
diff --git a/gas/testsuite/gas/sparc/mism-1.s b/gas/testsuite/gas/sparc/mism-1.s
index fac5e482704..f1aa412e186 100644
--- a/gas/testsuite/gas/sparc/mism-1.s
+++ b/gas/testsuite/gas/sparc/mism-1.s
@@ -19,4 +19,11 @@
shutdown ! { dg-error "mismatch|v9a" "v9a shutdown mismatch" }
+! v9b
+
+ edge8n %g1,%g2,%g3 ! { dg-error "mismatch|v9b" "v9b edge8n mismatch" }
+
+! v9e
+
+ aes_kexpand0 %f0,%f2,%f4 ! { dg-error "mismatch|v9e" "v9b aes_kexpand0 mismatch" }
foo:
diff --git a/gas/testsuite/gas/sparc/mism-2.s b/gas/testsuite/gas/sparc/mism-2.s
new file mode 100644
index 00000000000..8d94b17ad08
--- /dev/null
+++ b/gas/testsuite/gas/sparc/mism-2.s
@@ -0,0 +1,23 @@
+! Test architecture mismatch warnings from v9b upwards.
+! We don't test every possible mismatch, we just want to be reasonable sure
+! the mismatch checking code works.
+!
+! { dg-do assemble { target sparc*-*-* } }
+! { dg-options -Av9b }
+
+! v9d
+
+ addxc %g1,%g2,%g3 ! { dg-error "mismatch|v9d" "v9d addxc mismatch" }
+
+! v9e
+
+ aes_kexpand0 %f0,%f2,%f4 ! { dg-error "mismatch|v9e" "v9b aes_kexpand0 mismatch" }
+
+! v9v
+
+ fnumaddd %f0,%f2,%f0,%f4 ! { dg-error "mismatch|v9v" "v9v fnumaddd mismatch" }
+
+! v9m
+
+ xmpmul 4 ! { dg-error "mismatch|v9m" "v9m xmpmul mismatch" }
+foo:
diff --git a/gas/testsuite/gas/sparc/mwait.d b/gas/testsuite/gas/sparc/mwait.d
index bbae4fd737e..e93c63322f7 100644
--- a/gas/testsuite/gas/sparc/mwait.d
+++ b/gas/testsuite/gas/sparc/mwait.d
@@ -7,7 +7,6 @@
Disassembly of section .text:
0+ <.text>:
- 0: 83 47 00 00 rd %mwait, %g1
- 4: b9 80 a0 03 wr %g2, 3, %mwait
- 8: b9 80 00 01 mwait %g1
- c: b9 80 20 03 mwait 3
+ 0: b9 80 a0 03 wr %g2, 3, %mwait
+ 4: b9 80 00 01 mwait %g1
+ 8: b9 80 20 03 mwait 3
diff --git a/gas/testsuite/gas/sparc/mwait.s b/gas/testsuite/gas/sparc/mwait.s
index 03797466f7b..51f58a8aa56 100644
--- a/gas/testsuite/gas/sparc/mwait.s
+++ b/gas/testsuite/gas/sparc/mwait.s
@@ -1,7 +1,6 @@
# Test reads/writes to the %mwait asr register and the MWAIT
# instruction
.text
- rd %mwait, %g1
wr %g2, 0x3, %mwait
mwait %g1
mwait 0x3
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