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| author | Jan Beulich <jbeulich@suse.com> | 2020-01-16 10:05:35 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2020-01-16 10:05:35 +0100 |
| commit | 4814632e69636177b71b8d091009a0ec614916ec (patch) | |
| tree | e369b389478d5cb47c129e74dabcc69bbe9c100a /gas | |
| parent | c96d7e04622b3e073c22bcd532333223d0f26dbb (diff) | |
| download | binutils-gdb-4814632e69636177b71b8d091009a0ec614916ec.tar.gz | |
x86: VPEXTRQ/VPINSRQ are unavailable outside of 64-bit mode
The AVX512DQ patterns lacking a Cpu64 attribute made the memory operand
forms accepted even outside of 64-bit mode, and this even without any
{evex} pseudo-prefix (otherwise one could argue that this is an attempt
to follow one possible, albeit somewhat odd, interpretation of the SDM
wording to this effect).
For consistency between the various involved templates drop the
* (now) unnecessary IgnoreSize attributes
* unnecessary (due to VexW1) Size64 attributes from VEX encoded forms
* redundant (with Reg64) Qword operand attributes
uniformly.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/avx512dq-inval.l | 13 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/avx512dq-inval.s | 22 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/i386.exp | 1 |
4 files changed, 42 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index d88d15cbe0e..ff04223e0ec 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2020-01-16 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/i386/avx512dq-inval.l, + testsuite/gas/i386/avx512dq-inval.s: New. + * testsuite/gas/i386/i386.exp: Run new test. + 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * config/tc-msp430.c (CHECK_RELOC_MSP430): Always generate 430X diff --git a/gas/testsuite/gas/i386/avx512dq-inval.l b/gas/testsuite/gas/i386/avx512dq-inval.l new file mode 100644 index 00000000000..1533fb44c87 --- /dev/null +++ b/gas/testsuite/gas/i386/avx512dq-inval.l @@ -0,0 +1,13 @@ +.*: Assembler messages: +.*:[0-9]*: Error:.* `vpextrq' .* +.*:[0-9]*: Error:.* `vpextrq' .* +.*:[0-9]*: Error:.* `vpinsrq' .* +.*:[0-9]*: Error:.* `vpinsrq' .* +.*:[0-9]*: Error:.* `vpextrq' .* +.*:[0-9]*: Error:.* `vpextrq' .* +.*:[0-9]*: Error:.* `vpextrq' .* +.*:[0-9]*: Error:.* `vpextrq' .* +.*:[0-9]*: Error:.* `vpinsrq' .* +.*:[0-9]*: Error:.* `vpinsrq' .* +.*:[0-9]*: Error:.* `vpinsrq' .* +.*:[0-9]*: Error:.* `vpinsrq' .* diff --git a/gas/testsuite/gas/i386/avx512dq-inval.s b/gas/testsuite/gas/i386/avx512dq-inval.s new file mode 100644 index 00000000000..7f0f0243ff6 --- /dev/null +++ b/gas/testsuite/gas/i386/avx512dq-inval.s @@ -0,0 +1,22 @@ +# Check AVX512DQ instructions not to be accepted outside of 64-bit mode + + .text +_start: + vpextrq $0, %xmm0, (%eax) + {evex} vpextrq $0, %xmm0, (%eax) + + vpinsrq $0, (%eax), %xmm0, %xmm0 + {evex} vpinsrq $0, (%eax), %xmm0, %xmm0 + + .intel_syntax noprefix + + vpextrq [eax], xmm0, 0 + {evex} vpextrq [eax], xmm0, 0 + vpextrq qword ptr [eax], xmm0, 0 + {evex} vpextrq qword ptr [eax], xmm0, 0 + + vpinsrq xmm0, xmm0, [eax], 0 + {evex} vpinsrq xmm0, xmm0, [eax], 0 + vpinsrq xmm0, xmm0, qword ptr [eax], 0 + {evex} vpinsrq xmm0, xmm0, qword ptr [eax], 0 + diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index b081e359e49..9be9c1a22eb 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -356,6 +356,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_dump_test "avx512bw_vl" run_dump_test "avx512dq-intel" run_dump_test "avx512dq" + run_list_test "avx512dq-inval" run_dump_test "avx512dq_vl-intel" run_dump_test "avx512dq_vl" run_dump_test "omit-lock-yes" |