diff options
| author | Jan Beulich <jbeulich@novell.com> | 2018-03-28 14:22:00 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2018-03-28 14:22:00 +0200 |
| commit | 9646c87b5a6c0462e8a9b6305d9e449bd099f19d (patch) | |
| tree | 9a4114863abfce657a7031e7d4212cc0a99c306a /gas/testsuite | |
| parent | f8745e1cd139b5c6a5bd8a30ea84ccbd45dec81c (diff) | |
| download | binutils-gdb-9646c87b5a6c0462e8a9b6305d9e449bd099f19d.tar.gz | |
x86: don't show suffixes for to-scalar-int conversion insns
In the course of folding their patterns (possible now that the pointless
and partly even bogus VecESize are no longer in the way) I've noticed
that vcvt*2usi, other than their vcvt*2si counterparts, don't allow for
any suffixes. As that is supposedly intentional, make the disassembler
consistently omit suffixes for all to-scalar-int conversion insns.
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/gas/i386/ilp32/x86-64-simd-suffix.d | 16 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/x86-64-simd-suffix.d | 16 |
2 files changed, 16 insertions, 16 deletions
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-simd-suffix.d b/gas/testsuite/gas/i386/ilp32/x86-64-simd-suffix.d index 73514ef3fe8..84f7681fef2 100644 --- a/gas/testsuite/gas/i386/ilp32/x86-64-simd-suffix.d +++ b/gas/testsuite/gas/i386/ilp32/x86-64-simd-suffix.d @@ -61,15 +61,15 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f 2a 00 cvtpi2ps \(%rax\),%xmm0 [ ]*[a-f0-9]+: 0f 2d 00 cvtps2pi \(%rax\),%mm0 [ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si \(%rax\),%eax -[ ]*[a-f0-9]+: f2 48 0f 2d 00 cvtsd2siq \(%rax\),%rax +[ ]*[a-f0-9]+: f2 48 0f 2d 00 cvtsd2si \(%rax\),%rax [ ]*[a-f0-9]+: f2 0f 2c 00 cvttsd2si \(%rax\),%eax -[ ]*[a-f0-9]+: f2 48 0f 2c 00 cvttsd2siq \(%rax\),%rax +[ ]*[a-f0-9]+: f2 48 0f 2c 00 cvttsd2si \(%rax\),%rax [ ]*[a-f0-9]+: f2 0f 5a 00 cvtsd2ss \(%rax\),%xmm0 [ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd \(%rax\),%xmm0 [ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si \(%rax\),%eax -[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2siq \(%rax\),%rax +[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2si \(%rax\),%rax [ ]*[a-f0-9]+: f3 0f 2c 00 cvttss2si \(%rax\),%eax -[ ]*[a-f0-9]+: f3 48 0f 2c 00 cvttss2siq \(%rax\),%rax +[ ]*[a-f0-9]+: f3 48 0f 2c 00 cvttss2si \(%rax\),%rax [ ]*[a-f0-9]+: f2 0f 5e 00 divsd \(%rax\),%xmm0 [ ]*[a-f0-9]+: f3 0f 5e 00 divss \(%rax\),%xmm0 [ ]*[a-f0-9]+: f2 0f 5f 00 maxsd \(%rax\),%xmm0 @@ -180,15 +180,15 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f 2a 00 cvtpi2ps \(%rax\),%xmm0 [ ]*[a-f0-9]+: 0f 2d 00 cvtps2pi \(%rax\),%mm0 [ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si \(%rax\),%eax -[ ]*[a-f0-9]+: f2 48 0f 2d 00 cvtsd2siq \(%rax\),%rax +[ ]*[a-f0-9]+: f2 48 0f 2d 00 cvtsd2si \(%rax\),%rax [ ]*[a-f0-9]+: f2 0f 2c 00 cvttsd2si \(%rax\),%eax -[ ]*[a-f0-9]+: f2 48 0f 2c 00 cvttsd2siq \(%rax\),%rax +[ ]*[a-f0-9]+: f2 48 0f 2c 00 cvttsd2si \(%rax\),%rax [ ]*[a-f0-9]+: f2 0f 5a 00 cvtsd2ss \(%rax\),%xmm0 [ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd \(%rax\),%xmm0 [ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si \(%rax\),%eax -[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2siq \(%rax\),%rax +[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2si \(%rax\),%rax [ ]*[a-f0-9]+: f3 0f 2c 00 cvttss2si \(%rax\),%eax -[ ]*[a-f0-9]+: f3 48 0f 2c 00 cvttss2siq \(%rax\),%rax +[ ]*[a-f0-9]+: f3 48 0f 2c 00 cvttss2si \(%rax\),%rax [ ]*[a-f0-9]+: f2 0f 5e 00 divsd \(%rax\),%xmm0 [ ]*[a-f0-9]+: f3 0f 5e 00 divss \(%rax\),%xmm0 [ ]*[a-f0-9]+: f2 0f 5f 00 maxsd \(%rax\),%xmm0 diff --git a/gas/testsuite/gas/i386/x86-64-simd-suffix.d b/gas/testsuite/gas/i386/x86-64-simd-suffix.d index e4431e0e25a..8c05c07f148 100644 --- a/gas/testsuite/gas/i386/x86-64-simd-suffix.d +++ b/gas/testsuite/gas/i386/x86-64-simd-suffix.d @@ -61,15 +61,15 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f 2a 00 cvtpi2ps \(%rax\),%xmm0 [ ]*[a-f0-9]+: 0f 2d 00 cvtps2pi \(%rax\),%mm0 [ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si \(%rax\),%eax -[ ]*[a-f0-9]+: f2 48 0f 2d 00 cvtsd2siq \(%rax\),%rax +[ ]*[a-f0-9]+: f2 48 0f 2d 00 cvtsd2si \(%rax\),%rax [ ]*[a-f0-9]+: f2 0f 2c 00 cvttsd2si \(%rax\),%eax -[ ]*[a-f0-9]+: f2 48 0f 2c 00 cvttsd2siq \(%rax\),%rax +[ ]*[a-f0-9]+: f2 48 0f 2c 00 cvttsd2si \(%rax\),%rax [ ]*[a-f0-9]+: f2 0f 5a 00 cvtsd2ss \(%rax\),%xmm0 [ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd \(%rax\),%xmm0 [ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si \(%rax\),%eax -[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2siq \(%rax\),%rax +[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2si \(%rax\),%rax [ ]*[a-f0-9]+: f3 0f 2c 00 cvttss2si \(%rax\),%eax -[ ]*[a-f0-9]+: f3 48 0f 2c 00 cvttss2siq \(%rax\),%rax +[ ]*[a-f0-9]+: f3 48 0f 2c 00 cvttss2si \(%rax\),%rax [ ]*[a-f0-9]+: f2 0f 5e 00 divsd \(%rax\),%xmm0 [ ]*[a-f0-9]+: f3 0f 5e 00 divss \(%rax\),%xmm0 [ ]*[a-f0-9]+: f2 0f 5f 00 maxsd \(%rax\),%xmm0 @@ -180,15 +180,15 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f 2a 00 cvtpi2ps \(%rax\),%xmm0 [ ]*[a-f0-9]+: 0f 2d 00 cvtps2pi \(%rax\),%mm0 [ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si \(%rax\),%eax -[ ]*[a-f0-9]+: f2 48 0f 2d 00 cvtsd2siq \(%rax\),%rax +[ ]*[a-f0-9]+: f2 48 0f 2d 00 cvtsd2si \(%rax\),%rax [ ]*[a-f0-9]+: f2 0f 2c 00 cvttsd2si \(%rax\),%eax -[ ]*[a-f0-9]+: f2 48 0f 2c 00 cvttsd2siq \(%rax\),%rax +[ ]*[a-f0-9]+: f2 48 0f 2c 00 cvttsd2si \(%rax\),%rax [ ]*[a-f0-9]+: f2 0f 5a 00 cvtsd2ss \(%rax\),%xmm0 [ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd \(%rax\),%xmm0 [ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si \(%rax\),%eax -[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2siq \(%rax\),%rax +[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2si \(%rax\),%rax [ ]*[a-f0-9]+: f3 0f 2c 00 cvttss2si \(%rax\),%eax -[ ]*[a-f0-9]+: f3 48 0f 2c 00 cvttss2siq \(%rax\),%rax +[ ]*[a-f0-9]+: f3 48 0f 2c 00 cvttss2si \(%rax\),%rax [ ]*[a-f0-9]+: f2 0f 5e 00 divsd \(%rax\),%xmm0 [ ]*[a-f0-9]+: f3 0f 5e 00 divss \(%rax\),%xmm0 [ ]*[a-f0-9]+: f2 0f 5f 00 maxsd \(%rax\),%xmm0 |