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| author | Maciej W. Rozycki <macro@imgtec.com> | 2017-05-12 02:28:54 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@imgtec.com> | 2017-05-12 02:34:56 +0100 |
| commit | be3f1006743f04f0b133de7fa8085a3e4c49b193 (patch) | |
| tree | f2525c87a41cc2afe9a955aac6cd9d54de3a605e /gas/testsuite/gas/mips | |
| parent | a4f89915135f6760917c01dc783de5b674234d84 (diff) | |
| download | binutils-gdb-be3f1006743f04f0b133de7fa8085a3e4c49b193.tar.gz | |
MIPS/GAS: Unify GP-relative percent-ops
For a reason that is unclear commit d6f165938798 ("Support for MIPS16
HI16/LO16 relocations"),
<https://sourceware.org/ml/binutils/2005-02/msg00332.html>, which has
added support for the R_MIPS16_GPREL relocation, has spelled its
corresponding MIPS16 percent-op as `%gprel', rather than `%gp_rel' which
is how its regular MIPS counterpart is spelled. To make assembly code
sharing easier between the regular MIPS and the MIPS16 ISA make both
percent-op spellings acceptable in both kinds of code now.
Parts of this change by Matthew Fortune.
gas/
* config/tc-mips.c (mips_percent_op): Add "%gprel".
(mips16_percent_op): Add "%gp_rel".
* testsuite/gas/mips/elf-rel8.s:: Add `%gprel' forms.
* testsuite/gas/mips/elf-rel8-mips16.s: Add `%gp_rel' forms.
* testsuite/gas/mips/elf-rel8.d: Adjust accordingly.
* testsuite/gas/mips/elf-rel8-mips16.d: Likewise.
Diffstat (limited to 'gas/testsuite/gas/mips')
| -rw-r--r-- | gas/testsuite/gas/mips/elf-rel8-mips16.d | 8 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/elf-rel8-mips16.s | 7 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/elf-rel8.d | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/elf-rel8.s | 6 |
4 files changed, 26 insertions, 1 deletions
diff --git a/gas/testsuite/gas/mips/elf-rel8-mips16.d b/gas/testsuite/gas/mips/elf-rel8-mips16.d index 7c834fa5d2b..f1def80a061 100644 --- a/gas/testsuite/gas/mips/elf-rel8-mips16.d +++ b/gas/testsuite/gas/mips/elf-rel8-mips16.d @@ -34,5 +34,11 @@ Disassembly of section \.text: 32: R_MIPS16_GPREL gvar 36: f000 4c00 addiu \$4,0 36: R_MIPS16_GPREL gvar - 3a: 6500 nop + 3a: f000 9a80 lw \$4,0\(\$2\) + 3a: R_MIPS16_GPREL gvar + 3e: f000 da80 sw \$4,0\(\$2\) + 3e: R_MIPS16_GPREL gvar + 42: f000 4c00 addiu \$4,0 + 42: R_MIPS16_GPREL gvar + 46: 6500 nop #pass diff --git a/gas/testsuite/gas/mips/elf-rel8-mips16.s b/gas/testsuite/gas/mips/elf-rel8-mips16.s index 0c9eefe652f..dfde21acf44 100644 --- a/gas/testsuite/gas/mips/elf-rel8-mips16.s +++ b/gas/testsuite/gas/mips/elf-rel8-mips16.s @@ -32,6 +32,13 @@ foo: lw $4,%gprel(gvar)($2) sw $4,%gprel(gvar)($2) addiu $4,%gprel(gvar) + + # Check the alternative form. + + lw $4,%gp_rel(gvar)($2) + sw $4,%gp_rel(gvar)($2) + addiu $4,%gp_rel(gvar) + .align 6 .end foo diff --git a/gas/testsuite/gas/mips/elf-rel8.d b/gas/testsuite/gas/mips/elf-rel8.d index 270533b2883..beacecf2c53 100644 --- a/gas/testsuite/gas/mips/elf-rel8.d +++ b/gas/testsuite/gas/mips/elf-rel8.d @@ -54,4 +54,10 @@ Disassembly of section \.text: 5c: R_MIPS_GPREL16 gvar 60: 27840000 addiu \$4,\$28,0 60: R_MIPS_GPREL16 gvar + 64: 8f840000 lw \$4,0\(\$28\) + 64: R_MIPS_GPREL16 gvar + 68: af840000 sw \$4,0\(\$28\) + 68: R_MIPS_GPREL16 gvar + 6c: 27840000 addiu \$4,\$28,0 + 6c: R_MIPS_GPREL16 gvar \.\.\. diff --git a/gas/testsuite/gas/mips/elf-rel8.s b/gas/testsuite/gas/mips/elf-rel8.s index b3f5dab58d6..4a84beec41e 100644 --- a/gas/testsuite/gas/mips/elf-rel8.s +++ b/gas/testsuite/gas/mips/elf-rel8.s @@ -46,6 +46,12 @@ foo: sw $4,%gp_rel(gvar)($28) addiu $4,$28,%gp_rel(gvar) + # Check the alternative form. + + lw $4,%gprel(gvar)($28) + sw $4,%gprel(gvar)($28) + addiu $4,$28,%gprel(gvar) + .space 64 .end foo |