[AArch64][SVE 07/32] Replace hard-coded uses of REG_TYPE_R_Z_BHSDQ_V

To remove parsing ambiguities and to avoid register names being
accidentally added to the symbol table, the immediate parsing
routines reject things like:

	.equ	x0, 0
	add	v0.4s, v0.4s, x0

An explicit '#' must be used instead:

	.equ	x0, 0
	add	v0.4s, v0.4s, #x0

Of course, it wasn't possible to predict what other register
names might be added in future, so this behaviour was restricted
to the register names that were defined at the time.  For backwards
compatibility, we should continue to allow things like:

	.equ	p0, 0
	add	v0.4s, v0.4s, p0

even though p0 is now an SVE register.

However, it seems reasonable to extend the x0 behaviour above to
SVE registers when parsing SVE instructions, especially since none
of the SVE immediate formats are relocatable.  Doing so removes the
same parsing ambiguity for SVE instructions as the x0 behaviour removes
for base AArch64 instructions.

As a prerequisite, we then need to be able to tell the parsing routines
which registers to reject.  This patch changes the interface to make
that possible, although the set of rejected registers doesn't change
at this stage.

gas/
	* config/tc-aarch64.c (parse_immediate_expression): Add a
	reg_type parameter.
	(parse_constant_immediate): Likewise, and update calls.
	(parse_aarch64_imm_float): Likewise.
	(parse_big_immediate): Likewise.
	(po_imm_nc_or_fail): Update accordingly, passing down a new
	imm_reg_type variable.
	(po_imm_of_fail): Likewise.
	(parse_operands): Likewise.

Change-Id: I315ee16d17c768d25bb9e0848bb14c4609435ecb

0 files changed, 0 insertions, 0 deletions