diff options
author | H.J. Lu <hjl.tools@gmail.com> | 2020-01-17 07:07:55 -0800 |
---|---|---|
committer | H.J. Lu <hjl.tools@gmail.com> | 2020-01-17 07:07:55 -0800 |
commit | 42e04b360158941f4d490a38cad14b11593854fa (patch) | |
tree | 9bf46016eb0fbf13ee7dde413deed9aa4e6ef5f5 | |
parent | 26f42329caf1dcd4a410de61045208024156169f (diff) | |
download | binutils-gdb-42e04b360158941f4d490a38cad14b11593854fa.tar.gz |
x86: Add {vex} pseudo prefix
There are 2-byte VEX prefix and 3-byte VEX prefix. 2-byte VEX prefix
can't encode all operands. By default, assembler tries 2-byte VEX prefix
first. {vex3} can be used to force 3-byte VEX prefix. This patch adds
{vex} pseudo prefix and keeps {vex2} for backward compatibility.
gas/
* config/tc-i386.c (_i386_insn): Replace vex_encoding_vex2
with vex_encoding_vex.
(parse_insn): Likewise.
* doc/c-i386.texi: Replace {vex2} with {vex}. Update {vex}
and {vex3} documentation.
* testsuite/gas/i386/pseudos.s: Replace 3 {vex2} tests with
{vex}.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
opcodes/
* i386-opc.tbl: Add {vex} pseudo prefix.
* i386-tbl.h: Regenerated.
-rw-r--r-- | gas/ChangeLog | 11 | ||||
-rw-r--r-- | gas/config/tc-i386.c | 6 | ||||
-rw-r--r-- | gas/doc/c-i386.texi | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/pseudos.s | 6 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/x86-64-pseudos.s | 6 | ||||
-rw-r--r-- | opcodes/ChangeLog | 5 | ||||
-rw-r--r-- | opcodes/i386-opc.tbl | 1 | ||||
-rw-r--r-- | opcodes/i386-tbl.h | 12 |
8 files changed, 40 insertions, 11 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index f2b49b7a89d..e3adaa722ac 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,14 @@ +2020-01-17 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-i386.c (_i386_insn): Replace vex_encoding_vex2 + with vex_encoding_vex. + (parse_insn): Likewise. + * doc/c-i386.texi: Replace {vex2} with {vex}. Update {vex} + and {vex3} documentation. + * testsuite/gas/i386/pseudos.s: Replace 3 {vex2} tests with + {vex}. + * testsuite/gas/i386/x86-64-pseudos.s: Likewise. + 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 3f7f4222bf5..8728725b82d 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -419,7 +419,7 @@ struct _i386_insn enum { vex_encoding_default = 0, - vex_encoding_vex2, + vex_encoding_vex, vex_encoding_vex3, vex_encoding_evex } vec_encoding; @@ -4722,8 +4722,8 @@ parse_insn (char *line, char *mnemonic) i.dir_encoding = dir_encoding_store; break; case 0x4: - /* {vex2} */ - i.vec_encoding = vex_encoding_vex2; + /* {vex} */ + i.vec_encoding = vex_encoding_vex; break; case 0x5: /* {vex3} */ diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 4b258030135..e8685dd046f 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -758,10 +758,10 @@ Different encoding options can be specified via pseudo prefixes: @samp{@{store@}} -- prefer store-form instruction. @item -@samp{@{vex2@}} -- prefer 2-byte VEX prefix for VEX instruction. +@samp{@{vex@}} -- encode with VEX prefix. @item -@samp{@{vex3@}} -- prefer 3-byte VEX prefix for VEX instruction. +@samp{@{vex3@}} -- encode with 3-byte VEX prefix. @item @samp{@{evex@}} -- encode with EVEX prefix. diff --git a/gas/testsuite/gas/i386/pseudos.s b/gas/testsuite/gas/i386/pseudos.s index 419a4c51e92..19900dd7e59 100644 --- a/gas/testsuite/gas/i386/pseudos.s +++ b/gas/testsuite/gas/i386/pseudos.s @@ -6,9 +6,9 @@ _start: {vex3} {load} vmovaps %xmm7,%xmm2 {vex3} {store} vmovaps %xmm7,%xmm2 vmovaps %xmm7,%xmm2 - {vex2} vmovaps %xmm7,%xmm2 - {vex2} {load} vmovaps %xmm7,%xmm2 - {vex2} {store} vmovaps %xmm7,%xmm2 + {vex} vmovaps %xmm7,%xmm2 + {vex} {load} vmovaps %xmm7,%xmm2 + {vex} {store} vmovaps %xmm7,%xmm2 {vex3} vmovaps (%eax),%xmm2 vmovaps (%eax),%xmm2 {vex2} vmovaps (%eax),%xmm2 diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.s b/gas/testsuite/gas/i386/x86-64-pseudos.s index 33712d3e636..14b6c92b864 100644 --- a/gas/testsuite/gas/i386/x86-64-pseudos.s +++ b/gas/testsuite/gas/i386/x86-64-pseudos.s @@ -6,9 +6,9 @@ _start: {vex3} {load} vmovaps %xmm7,%xmm2 {vex3} {store} vmovaps %xmm7,%xmm2 vmovaps %xmm7,%xmm2 - {vex2} vmovaps %xmm7,%xmm2 - {vex2} {load} vmovaps %xmm7,%xmm2 - {vex2} {store} vmovaps %xmm7,%xmm2 + {vex} vmovaps %xmm7,%xmm2 + {vex} {load} vmovaps %xmm7,%xmm2 + {vex} {store} vmovaps %xmm7,%xmm2 {vex3} vmovaps (%rax),%xmm2 vmovaps (%rax),%xmm2 {vex2} vmovaps (%rax),%xmm2 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 2d3b6d14401..e48e566cbc3 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2020-01-17 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.tbl: Add {vex} pseudo prefix. + * i386-tbl.h: Regenerated. + 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 73cd6c6a11e..d8af2599032 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -879,6 +879,7 @@ rex.wrxb, 0, 0x4f, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld {disp32}, 0, 0x1, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } {load}, 0, 0x2, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } {store}, 0, 0x3, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +{vex}, 0, 0x4, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } {vex2}, 0, 0x4, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } {vex3}, 0, 0x5, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } {evex}, 0, 0x6, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index e9381bf11b2..758d92bcfd2 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -7600,6 +7600,18 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, + { "{vex}", 0x4, None, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, { "{vex2}", 0x4, None, 0, 0, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |