From 8e64181a9986d2dd2e23bed1541590084eec0c57 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 15 Oct 2019 10:28:43 +0200 Subject: ARM: imx: Convert mccmon6 to use DM/DTS in the u-boot proper This commit converts mccmon6's u-boot proper (in a single commit to avoid build breaks) to use solely DM/DTS. The DTS description of the mccmon6 has been ported from Linux kernel (v4.20, SHA1: 8fe28cb58bcb235034b64cbbb7550a8a43fd88be) Signed-off-by: Lukasz Majewski --- include/configs/mccmon6.h | 13 ------------- 1 file changed, 13 deletions(-) (limited to 'include') diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 667dac7340..b25aacbf41 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -34,22 +34,12 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) -#define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT - -#define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_SYS_MEMTEST_START 0x10000000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* MMC Configuration */ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 @@ -66,10 +56,7 @@ #define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) } /* Ethernet Configuration */ -#define CONFIG_FEC_MXC #define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 1 #define CONFIG_EXTRA_ENV_SETTINGS \ -- cgit v1.2.1 From e4417ed03ed97eb40a4908a5cf7940a360a70a82 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 15 Oct 2019 10:28:46 +0200 Subject: ARM: imx: Convert mccmon6 to use fitImage instead of uImage+DTB This commit enabled support for fitImage on mccmon6 when we switch to DT/DTS (including falcon mode). Signed-off-by: Lukasz Majewski --- include/configs/mccmon6.h | 57 +++++++++++++++++++---------------------------- 1 file changed, 23 insertions(+), 34 deletions(-) (limited to 'include') diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index b25aacbf41..c685de6551 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -14,10 +14,6 @@ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000) -#define CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + 0x180000) -#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + 0x1980000) -#define CONFIG_SYS_FDT_SIZE (48 * SZ_1K) #define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 /* @@ -28,8 +24,7 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR (0x800) #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (0x80) #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (0x1000) -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "imx6q-mccmon.dtb" +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "fitImage" /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) @@ -61,14 +56,13 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200 quiet\0" \ - "fdtfile=imx6q-mccmon6.dtb\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "boot_os=yes\0" \ + "kernelsize=0x300000\0" \ "disable_giga=yes\0" \ "download_kernel=" \ - "tftpboot ${kernel_addr} ${kernel_file};" \ - "tftpboot ${fdt_addr} ${fdtfile};\0" \ + "tftpboot ${loadaddr} ${kernel_file};\0" \ "get_boot_medium=" \ "setenv boot_medium nor;" \ "setexpr.l _src_sbmr1 *0x020d8004;" \ @@ -76,10 +70,7 @@ "if test ${_b_medium} = 40; then " \ "setenv boot_medium sdcard;" \ "fi\0" \ - "kernel_file=uImage\0" \ - "load_kernel=" \ - "load mmc ${bootdev}:${bootpart} ${kernel_addr} uImage;" \ - "load mmc ${bootdev}:${bootpart} ${fdt_addr} ${fdtfile};\0" \ + "kernel_file=fitImage\0" \ "boot_sd=" \ "echo '#######################';" \ "echo '# Factory SDcard Boot #';" \ @@ -90,12 +81,11 @@ "run factory_flash_img;\0" \ "boot_nor=" \ "setenv kernelnor 0x08180000;" \ - "setenv dtbnor 0x09980000;" \ "setenv bootargs console=${console} " \ CONFIG_MTDPARTS_DEFAULT " " \ "root=/dev/mmcblk1 rootfstype=ext4 rw rootwait noinitrd;" \ - "cp.l ${dtbnor} ${dtbloadaddr} 0x8000;" \ - "bootm ${kernelnor} - ${dtbloadaddr};\0" \ + "cp.l ${kernelnor} ${loadaddr} ${kernelsize};" \ + "bootm ${loadaddr};reset;\0" \ "boot_recovery=" \ "echo '#######################';" \ "echo '# RECOVERY SWU Boot #';" \ @@ -103,14 +93,13 @@ "setenv rootfsloadaddr 0x13000000;" \ "setenv swukernelnor 0x08980000;" \ "setenv swurootfsnor 0x09180000;" \ - "setenv swudtbnor 0x099A0000;" \ "setenv bootargs console=${console} " \ CONFIG_MTDPARTS_DEFAULT " " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}::off root=/dev/ram rw;" \ "cp.l ${swurootfsnor} ${rootfsloadaddr} 0x200000;" \ - "cp.l ${swudtbnor} ${dtbloadaddr} 0x8000;" \ - "bootm ${swukernelnor} ${rootfsloadaddr} ${dtbloadaddr};\0" \ + "cp.l ${swukernelnor} ${loadaddr} ${kernelsize};" \ + "bootm ${loadaddr} ${rootfsloadaddr};reset;\0" \ "boot_tftp=" \ "echo '#######################';" \ "echo '# TFTP Boot #';" \ @@ -118,7 +107,7 @@ "if run download_kernel; then " \ "setenv bootargs console=${console} " \ "root=/dev/mmcblk0p2 rootwait;" \ - "bootm ${kernel_addr} - ${fdt_addr};" \ + "bootm $loadaddr};reset;" \ "fi\0" \ "bootcmd=" \ "if test -n ${recovery_status}; then " \ @@ -138,13 +127,10 @@ "fi;" \ "fi\0" \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "fdt_addr=0x18000000\0" \ "bootdev=1\0" \ "bootpart=1\0" \ - "kernel_addr=" __stringify(CONFIG_LOADADDR) "\0" \ "netdev=eth0\0" \ "load_addr=0x11000000\0" \ - "dtbloadaddr=0x12000000\0" \ "uboot_file=u-boot.img\0" \ "SPL_file=SPL\0" \ "load_uboot=tftp ${load_addr} ${uboot_file}\0" \ @@ -171,6 +157,7 @@ "device ${mmcdev};" \ "run factory_nor_img;" \ "run factory_eMMC_img;" \ + "run factory_SPL_falcon_setup;" \ "fi\0" \ "factory_eMMC_img="\ "echo 'Update mccmon6 eMMC image'; " \ @@ -192,6 +179,16 @@ "erase ${nor_bank_start} +${nor_img_size};" \ "setexpr nor_img_size ${nor_img_size} / 4; " \ "cp.l ${nor_img_addr} ${nor_bank_start} ${nor_img_size}\0" \ + "factory_SPL_falcon_setup="\ + "echo 'Write Falcon boot data'; " \ + "setenv kernelnor 0x08180000;" \ + "cp.l ${kernelnor} ${loadaddr} ${kernelsize};" \ + "spl export fdt ${loadaddr};" \ + "setenv nor_img_addr ${fdtargsaddr};" \ + "setenv nor_img_size 0x20000;" \ + "setenv nor_bank_start " \ + __stringify(CONFIG_CMD_SPL_NOR_OFS)";" \ + "run nor_update\0" \ "tftp_nor_uboot="\ "echo 'Update mccmon6 NOR U-BOOT via TFTP'; " \ "setenv nor_img_file u-boot.img; " \ @@ -200,22 +197,14 @@ "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \ "run nor_update;" \ "fi\0" \ - "tftp_nor_uImg="\ - "echo 'Update mccmon6 NOR uImage via TFTP'; " \ - "setenv nor_img_file uImage; " \ + "tftp_nor_fitImg="\ + "echo 'Update mccmon6 NOR fitImage via TFTP'; " \ + "setenv nor_img_file fitImage; " \ "setenv nor_img_size 0x500000; " \ "setenv nor_bank_start 0x08180000; " \ "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \ "run nor_update;" \ "fi\0" \ - "tftp_nor_dtb="\ - "echo 'Update mccmon6 NOR DTB via TFTP'; " \ - "setenv nor_img_file imx6q-mccmon6.dtb; " \ - "setenv nor_img_size 0x20000; " \ - "setenv nor_bank_start 0x09980000; " \ - "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \ - "run nor_update;" \ - "fi\0" \ "tftp_nor_img="\ "echo 'Update mccmon6 NOR image via TFTP'; " \ "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \ -- cgit v1.2.1 From 05737f35859756602e286cbd358f11b30cfb6383 Mon Sep 17 00:00:00 2001 From: Patrick Wildt Date: Mon, 14 Oct 2019 13:19:00 +0200 Subject: imx: update i.MX8MQ device trees This updates the i.MX8MQ device trees and, necessarily, also the i.MX8MQ clock bindings. These are taken verbatim from from the Linux kernel version v5.4-rc2, which three small changes which were already part of the previous device tree: * Keep the PSCI reserved memory range * Keep the alias for ethernet, so that the MAC address can be set * Keep the modified #include for the IOMUXC pins Signed-off-by: Patrick Wildt Acked-by: Peng Fan --- include/configs/imx8mq_evk.h | 2 +- include/dt-bindings/clock/imx8mq-clock.h | 571 ++++++++++--------------------- 2 files changed, 184 insertions(+), 389 deletions(-) (limited to 'include') diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index d4d8d20850..84fae34777 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -107,7 +107,7 @@ "fdt_addr=0x43000000\0" \ "fdt_high=0xffffffffffffffff\0" \ "boot_fdt=try\0" \ - "fdt_file=fsl-imx8mq-evk.dtb\0" \ + "fdt_file=imx8mq-evk.dtb\0" \ "initrd_addr=0x43800000\0" \ "initrd_high=0xffffffffffffffff\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h index 11dcafcfde..65463673d2 100644 --- a/include/dt-bindings/clock/imx8mq-clock.h +++ b/include/dt-bindings/clock/imx8mq-clock.h @@ -1,10 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright 2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H @@ -148,465 +145,263 @@ /* BUS TYPE */ /* MAIN AXI */ -#define IMX8MQ_CLK_MAIN_AXI_SRC 103 -#define IMX8MQ_CLK_MAIN_AXI_CG 104 -#define IMX8MQ_CLK_MAIN_AXI_PRE_DIV 105 -#define IMX8MQ_CLK_MAIN_AXI_DIV 106 +#define IMX8MQ_CLK_MAIN_AXI 103 /* ENET AXI */ -#define IMX8MQ_CLK_ENET_AXI_SRC 107 -#define IMX8MQ_CLK_ENET_AXI_CG 108 -#define IMX8MQ_CLK_ENET_AXI_PRE_DIV 109 -#define IMX8MQ_CLK_ENET_AXI_DIV 110 +#define IMX8MQ_CLK_ENET_AXI 104 /* NAND_USDHC_BUS */ -#define IMX8MQ_CLK_NAND_USDHC_BUS_SRC 111 -#define IMX8MQ_CLK_NAND_USDHC_BUS_CG 112 -#define IMX8MQ_CLK_NAND_USDHC_BUS_PRE_DIV 113 -#define IMX8MQ_CLK_NAND_USDHC_BUS_DIV 114 +#define IMX8MQ_CLK_NAND_USDHC_BUS 105 /* VPU BUS */ -#define IMX8MQ_CLK_VPU_BUS_SRC 115 -#define IMX8MQ_CLK_VPU_BUS_CG 116 -#define IMX8MQ_CLK_VPU_BUS_PRE_DIV 117 -#define IMX8MQ_CLK_VPU_BUS_DIV 118 +#define IMX8MQ_CLK_VPU_BUS 106 /* DISP_AXI */ -#define IMX8MQ_CLK_DISP_AXI_SRC 119 -#define IMX8MQ_CLK_DISP_AXI_CG 120 -#define IMX8MQ_CLK_DISP_AXI_PRE_DIV 121 -#define IMX8MQ_CLK_DISP_AXI_DIV 122 +#define IMX8MQ_CLK_DISP_AXI 107 /* DISP APB */ -#define IMX8MQ_CLK_DISP_APB_SRC 123 -#define IMX8MQ_CLK_DISP_APB_CG 124 -#define IMX8MQ_CLK_DISP_APB_PRE_DIV 125 -#define IMX8MQ_CLK_DISP_APB_DIV 126 +#define IMX8MQ_CLK_DISP_APB 108 /* DISP RTRM */ -#define IMX8MQ_CLK_DISP_RTRM_SRC 127 -#define IMX8MQ_CLK_DISP_RTRM_CG 128 -#define IMX8MQ_CLK_DISP_RTRM_PRE_DIV 129 -#define IMX8MQ_CLK_DISP_RTRM_DIV 130 +#define IMX8MQ_CLK_DISP_RTRM 109 /* USB_BUS */ -#define IMX8MQ_CLK_USB_BUS_SRC 131 -#define IMX8MQ_CLK_USB_BUS_CG 132 -#define IMX8MQ_CLK_USB_BUS_PRE_DIV 133 -#define IMX8MQ_CLK_USB_BUS_DIV 134 +#define IMX8MQ_CLK_USB_BUS 110 /* GPU_AXI */ -#define IMX8MQ_CLK_GPU_AXI_SRC 135 -#define IMX8MQ_CLK_GPU_AXI_CG 136 -#define IMX8MQ_CLK_GPU_AXI_PRE_DIV 137 -#define IMX8MQ_CLK_GPU_AXI_DIV 138 +#define IMX8MQ_CLK_GPU_AXI 111 /* GPU_AHB */ -#define IMX8MQ_CLK_GPU_AHB_SRC 139 -#define IMX8MQ_CLK_GPU_AHB_CG 140 -#define IMX8MQ_CLK_GPU_AHB_PRE_DIV 141 -#define IMX8MQ_CLK_GPU_AHB_DIV 142 +#define IMX8MQ_CLK_GPU_AHB 112 /* NOC */ -#define IMX8MQ_CLK_NOC_SRC 143 -#define IMX8MQ_CLK_NOC_CG 144 -#define IMX8MQ_CLK_NOC_PRE_DIV 145 -#define IMX8MQ_CLK_NOC_DIV 146 +#define IMX8MQ_CLK_NOC 113 /* NOC_APB */ -#define IMX8MQ_CLK_NOC_APB_SRC 147 -#define IMX8MQ_CLK_NOC_APB_CG 148 -#define IMX8MQ_CLK_NOC_APB_PRE_DIV 149 -#define IMX8MQ_CLK_NOC_APB_DIV 150 +#define IMX8MQ_CLK_NOC_APB 115 /* AHB */ -#define IMX8MQ_CLK_AHB_SRC 151 -#define IMX8MQ_CLK_AHB_CG 152 -#define IMX8MQ_CLK_AHB_PRE_DIV 153 -#define IMX8MQ_CLK_AHB_DIV 154 +#define IMX8MQ_CLK_AHB 116 /* AUDIO AHB */ -#define IMX8MQ_CLK_AUDIO_AHB_SRC 155 -#define IMX8MQ_CLK_AUDIO_AHB_CG 156 -#define IMX8MQ_CLK_AUDIO_AHB_PRE_DIV 157 -#define IMX8MQ_CLK_AUDIO_AHB_DIV 158 +#define IMX8MQ_CLK_AUDIO_AHB 117 /* DRAM_ALT */ -#define IMX8MQ_CLK_DRAM_ALT_SRC 159 -#define IMX8MQ_CLK_DRAM_ALT_CG 160 -#define IMX8MQ_CLK_DRAM_ALT_PRE_DIV 161 -#define IMX8MQ_CLK_DRAM_ALT_DIV 162 +#define IMX8MQ_CLK_DRAM_ALT 118 /* DRAM APB */ -#define IMX8MQ_CLK_DRAM_APB_SRC 163 -#define IMX8MQ_CLK_DRAM_APB_CG 164 -#define IMX8MQ_CLK_DRAM_APB_PRE_DIV 165 -#define IMX8MQ_CLK_DRAM_APB_DIV 166 +#define IMX8MQ_CLK_DRAM_APB 119 /* VPU_G1 */ -#define IMX8MQ_CLK_VPU_G1_SRC 167 -#define IMX8MQ_CLK_VPU_G1_CG 168 -#define IMX8MQ_CLK_VPU_G1_PRE_DIV 169 -#define IMX8MQ_CLK_VPU_G1_DIV 170 +#define IMX8MQ_CLK_VPU_G1 120 /* VPU_G2 */ -#define IMX8MQ_CLK_VPU_G2_SRC 171 -#define IMX8MQ_CLK_VPU_G2_CG 172 -#define IMX8MQ_CLK_VPU_G2_PRE_DIV 173 -#define IMX8MQ_CLK_VPU_G2_DIV 174 +#define IMX8MQ_CLK_VPU_G2 121 /* DISP_DTRC */ -#define IMX8MQ_CLK_DISP_DTRC_SRC 175 -#define IMX8MQ_CLK_DISP_DTRC_CG 176 -#define IMX8MQ_CLK_DISP_DTRC_PRE_DIV 177 -#define IMX8MQ_CLK_DISP_DTRC_DIV 178 +#define IMX8MQ_CLK_DISP_DTRC 122 /* DISP_DC8000 */ -#define IMX8MQ_CLK_DISP_DC8000_SRC 179 -#define IMX8MQ_CLK_DISP_DC8000_CG 180 -#define IMX8MQ_CLK_DISP_DC8000_PRE_DIV 181 -#define IMX8MQ_CLK_DISP_DC8000_DIV 182 +#define IMX8MQ_CLK_DISP_DC8000 123 /* PCIE_CTRL */ -#define IMX8MQ_CLK_PCIE1_CTRL_SRC 183 -#define IMX8MQ_CLK_PCIE1_CTRL_CG 184 -#define IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV 185 -#define IMX8MQ_CLK_PCIE1_CTRL_DIV 186 +#define IMX8MQ_CLK_PCIE1_CTRL 124 /* PCIE_PHY */ -#define IMX8MQ_CLK_PCIE1_PHY_SRC 187 -#define IMX8MQ_CLK_PCIE1_PHY_CG 188 -#define IMX8MQ_CLK_PCIE1_PHY_PRE_DIV 189 -#define IMX8MQ_CLK_PCIE1_PHY_DIV 190 +#define IMX8MQ_CLK_PCIE1_PHY 125 /* PCIE_AUX */ -#define IMX8MQ_CLK_PCIE1_AUX_SRC 191 -#define IMX8MQ_CLK_PCIE1_AUX_CG 192 -#define IMX8MQ_CLK_PCIE1_AUX_PRE_DIV 193 -#define IMX8MQ_CLK_PCIE1_AUX_DIV 194 +#define IMX8MQ_CLK_PCIE1_AUX 126 /* DC_PIXEL */ -#define IMX8MQ_CLK_DC_PIXEL_SRC 195 -#define IMX8MQ_CLK_DC_PIXEL_CG 196 -#define IMX8MQ_CLK_DC_PIXEL_PRE_DIV 197 -#define IMX8MQ_CLK_DC_PIXEL_DIV 198 +#define IMX8MQ_CLK_DC_PIXEL 127 /* LCDIF_PIXEL */ -#define IMX8MQ_CLK_LCDIF_PIXEL_SRC 199 -#define IMX8MQ_CLK_LCDIF_PIXEL_CG 200 -#define IMX8MQ_CLK_LCDIF_PIXEL_PRE_DIV 201 -#define IMX8MQ_CLK_LCDIF_PIXEL_DIV 202 +#define IMX8MQ_CLK_LCDIF_PIXEL 128 /* SAI1~6 */ -#define IMX8MQ_CLK_SAI1_SRC 203 -#define IMX8MQ_CLK_SAI1_CG 204 -#define IMX8MQ_CLK_SAI1_PRE_DIV 205 -#define IMX8MQ_CLK_SAI1_DIV 206 - -#define IMX8MQ_CLK_SAI2_SRC 207 -#define IMX8MQ_CLK_SAI2_CG 208 -#define IMX8MQ_CLK_SAI2_PRE_DIV 209 -#define IMX8MQ_CLK_SAI2_DIV 210 - -#define IMX8MQ_CLK_SAI3_SRC 211 -#define IMX8MQ_CLK_SAI3_CG 212 -#define IMX8MQ_CLK_SAI3_PRE_DIV 213 -#define IMX8MQ_CLK_SAI3_DIV 214 - -#define IMX8MQ_CLK_SAI4_SRC 215 -#define IMX8MQ_CLK_SAI4_CG 216 -#define IMX8MQ_CLK_SAI4_PRE_DIV 217 -#define IMX8MQ_CLK_SAI4_DIV 218 - -#define IMX8MQ_CLK_SAI5_SRC 219 -#define IMX8MQ_CLK_SAI5_CG 220 -#define IMX8MQ_CLK_SAI5_PRE_DIV 221 -#define IMX8MQ_CLK_SAI5_DIV 222 - -#define IMX8MQ_CLK_SAI6_SRC 223 -#define IMX8MQ_CLK_SAI6_CG 224 -#define IMX8MQ_CLK_SAI6_PRE_DIV 225 -#define IMX8MQ_CLK_SAI6_DIV 226 +#define IMX8MQ_CLK_SAI1 129 + +#define IMX8MQ_CLK_SAI2 130 + +#define IMX8MQ_CLK_SAI3 131 + +#define IMX8MQ_CLK_SAI4 132 + +#define IMX8MQ_CLK_SAI5 133 + +#define IMX8MQ_CLK_SAI6 134 /* SPDIF1 */ -#define IMX8MQ_CLK_SPDIF1_SRC 227 -#define IMX8MQ_CLK_SPDIF1_CG 228 -#define IMX8MQ_CLK_SPDIF1_PRE_DIV 229 -#define IMX8MQ_CLK_SPDIF1_DIV 230 +#define IMX8MQ_CLK_SPDIF1 135 /* SPDIF2 */ -#define IMX8MQ_CLK_SPDIF2_SRC 231 -#define IMX8MQ_CLK_SPDIF2_CG 232 -#define IMX8MQ_CLK_SPDIF2_PRE_DIV 233 -#define IMX8MQ_CLK_SPDIF2_DIV 234 +#define IMX8MQ_CLK_SPDIF2 136 /* ENET_REF */ -#define IMX8MQ_CLK_ENET_REF_SRC 235 -#define IMX8MQ_CLK_ENET_REF_CG 236 -#define IMX8MQ_CLK_ENET_REF_PRE_DIV 237 -#define IMX8MQ_CLK_ENET_REF_DIV 238 +#define IMX8MQ_CLK_ENET_REF 137 /* ENET_TIMER */ -#define IMX8MQ_CLK_ENET_TIMER_SRC 239 -#define IMX8MQ_CLK_ENET_TIMER_CG 240 -#define IMX8MQ_CLK_ENET_TIMER_PRE_DIV 241 -#define IMX8MQ_CLK_ENET_TIMER_DIV 242 +#define IMX8MQ_CLK_ENET_TIMER 138 /* ENET_PHY */ -#define IMX8MQ_CLK_ENET_PHY_REF_SRC 243 -#define IMX8MQ_CLK_ENET_PHY_REF_CG 244 -#define IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV 245 -#define IMX8MQ_CLK_ENET_PHY_REF_DIV 246 +#define IMX8MQ_CLK_ENET_PHY_REF 139 /* NAND */ -#define IMX8MQ_CLK_NAND_SRC 247 -#define IMX8MQ_CLK_NAND_CG 248 -#define IMX8MQ_CLK_NAND_PRE_DIV 249 -#define IMX8MQ_CLK_NAND_DIV 250 +#define IMX8MQ_CLK_NAND 140 /* QSPI */ -#define IMX8MQ_CLK_QSPI_SRC 251 -#define IMX8MQ_CLK_QSPI_CG 252 -#define IMX8MQ_CLK_QSPI_PRE_DIV 253 -#define IMX8MQ_CLK_QSPI_DIV 254 +#define IMX8MQ_CLK_QSPI 141 /* USDHC1 */ -#define IMX8MQ_CLK_USDHC1_SRC 255 -#define IMX8MQ_CLK_USDHC1_CG 256 -#define IMX8MQ_CLK_USDHC1_PRE_DIV 257 -#define IMX8MQ_CLK_USDHC1_DIV 258 +#define IMX8MQ_CLK_USDHC1 142 /* USDHC2 */ -#define IMX8MQ_CLK_USDHC2_SRC 259 -#define IMX8MQ_CLK_USDHC2_CG 260 -#define IMX8MQ_CLK_USDHC2_PRE_DIV 261 -#define IMX8MQ_CLK_USDHC2_DIV 262 +#define IMX8MQ_CLK_USDHC2 143 /* I2C1 */ -#define IMX8MQ_CLK_I2C1_SRC 263 -#define IMX8MQ_CLK_I2C1_CG 264 -#define IMX8MQ_CLK_I2C1_PRE_DIV 265 -#define IMX8MQ_CLK_I2C1_DIV 266 +#define IMX8MQ_CLK_I2C1 144 /* I2C2 */ -#define IMX8MQ_CLK_I2C2_SRC 267 -#define IMX8MQ_CLK_I2C2_CG 268 -#define IMX8MQ_CLK_I2C2_PRE_DIV 269 -#define IMX8MQ_CLK_I2C2_DIV 270 +#define IMX8MQ_CLK_I2C2 145 /* I2C3 */ -#define IMX8MQ_CLK_I2C3_SRC 271 -#define IMX8MQ_CLK_I2C3_CG 272 -#define IMX8MQ_CLK_I2C3_PRE_DIV 273 -#define IMX8MQ_CLK_I2C3_DIV 274 +#define IMX8MQ_CLK_I2C3 146 /* I2C4 */ -#define IMX8MQ_CLK_I2C4_SRC 275 -#define IMX8MQ_CLK_I2C4_CG 276 -#define IMX8MQ_CLK_I2C4_PRE_DIV 277 -#define IMX8MQ_CLK_I2C4_DIV 278 +#define IMX8MQ_CLK_I2C4 147 /* UART1 */ -#define IMX8MQ_CLK_UART1_SRC 279 -#define IMX8MQ_CLK_UART1_CG 280 -#define IMX8MQ_CLK_UART1_PRE_DIV 281 -#define IMX8MQ_CLK_UART1_DIV 282 +#define IMX8MQ_CLK_UART1 148 /* UART2 */ -#define IMX8MQ_CLK_UART2_SRC 283 -#define IMX8MQ_CLK_UART2_CG 284 -#define IMX8MQ_CLK_UART2_PRE_DIV 285 -#define IMX8MQ_CLK_UART2_DIV 286 +#define IMX8MQ_CLK_UART2 149 /* UART3 */ -#define IMX8MQ_CLK_UART3_SRC 287 -#define IMX8MQ_CLK_UART3_CG 288 -#define IMX8MQ_CLK_UART3_PRE_DIV 289 -#define IMX8MQ_CLK_UART3_DIV 290 +#define IMX8MQ_CLK_UART3 150 /* UART4 */ -#define IMX8MQ_CLK_UART4_SRC 291 -#define IMX8MQ_CLK_UART4_CG 292 -#define IMX8MQ_CLK_UART4_PRE_DIV 293 -#define IMX8MQ_CLK_UART4_DIV 294 +#define IMX8MQ_CLK_UART4 151 /* USB_CORE_REF */ -#define IMX8MQ_CLK_USB_CORE_REF_SRC 295 -#define IMX8MQ_CLK_USB_CORE_REF_CG 296 -#define IMX8MQ_CLK_USB_CORE_REF_PRE_DIV 297 -#define IMX8MQ_CLK_USB_CORE_REF_DIV 298 +#define IMX8MQ_CLK_USB_CORE_REF 152 /* USB_PHY_REF */ -#define IMX8MQ_CLK_USB_PHY_REF_SRC 299 -#define IMX8MQ_CLK_USB_PHY_REF_CG 300 -#define IMX8MQ_CLK_USB_PHY_REF_PRE_DIV 301 -#define IMX8MQ_CLK_USB_PHY_REF_DIV 302 +#define IMX8MQ_CLK_USB_PHY_REF 153 /* ECSPI1 */ -#define IMX8MQ_CLK_ECSPI1_SRC 303 -#define IMX8MQ_CLK_ECSPI1_CG 304 -#define IMX8MQ_CLK_ECSPI1_PRE_DIV 305 -#define IMX8MQ_CLK_ECSPI1_DIV 306 +#define IMX8MQ_CLK_ECSPI1 154 /* ECSPI2 */ -#define IMX8MQ_CLK_ECSPI2_SRC 307 -#define IMX8MQ_CLK_ECSPI2_CG 308 -#define IMX8MQ_CLK_ECSPI2_PRE_DIV 309 -#define IMX8MQ_CLK_ECSPI2_DIV 310 +#define IMX8MQ_CLK_ECSPI2 155 /* PWM1 */ -#define IMX8MQ_CLK_PWM1_SRC 311 -#define IMX8MQ_CLK_PWM1_CG 312 -#define IMX8MQ_CLK_PWM1_PRE_DIV 313 -#define IMX8MQ_CLK_PWM1_DIV 314 +#define IMX8MQ_CLK_PWM1 156 /* PWM2 */ -#define IMX8MQ_CLK_PWM2_SRC 315 -#define IMX8MQ_CLK_PWM2_CG 316 -#define IMX8MQ_CLK_PWM2_PRE_DIV 317 -#define IMX8MQ_CLK_PWM2_DIV 318 +#define IMX8MQ_CLK_PWM2 157 /* PWM3 */ -#define IMX8MQ_CLK_PWM3_SRC 319 -#define IMX8MQ_CLK_PWM3_CG 320 -#define IMX8MQ_CLK_PWM3_PRE_DIV 321 -#define IMX8MQ_CLK_PWM3_DIV 322 +#define IMX8MQ_CLK_PWM3 158 /* PWM4 */ -#define IMX8MQ_CLK_PWM4_SRC 323 -#define IMX8MQ_CLK_PWM4_CG 324 -#define IMX8MQ_CLK_PWM4_PRE_DIV 325 -#define IMX8MQ_CLK_PWM4_DIV 326 +#define IMX8MQ_CLK_PWM4 159 /* GPT1 */ -#define IMX8MQ_CLK_GPT1_SRC 327 -#define IMX8MQ_CLK_GPT1_CG 328 -#define IMX8MQ_CLK_GPT1_PRE_DIV 329 -#define IMX8MQ_CLK_GPT1_DIV 330 +#define IMX8MQ_CLK_GPT1 160 /* WDOG */ -#define IMX8MQ_CLK_WDOG_SRC 331 -#define IMX8MQ_CLK_WDOG_CG 332 -#define IMX8MQ_CLK_WDOG_PRE_DIV 333 -#define IMX8MQ_CLK_WDOG_DIV 334 +#define IMX8MQ_CLK_WDOG 161 /* WRCLK */ -#define IMX8MQ_CLK_WRCLK_SRC 335 -#define IMX8MQ_CLK_WRCLK_CG 336 -#define IMX8MQ_CLK_WRCLK_PRE_DIV 337 -#define IMX8MQ_CLK_WRCLK_DIV 338 +#define IMX8MQ_CLK_WRCLK 162 /* DSI_CORE */ -#define IMX8MQ_CLK_DSI_CORE_SRC 339 -#define IMX8MQ_CLK_DSI_CORE_CG 340 -#define IMX8MQ_CLK_DSI_CORE_PRE_DIV 341 -#define IMX8MQ_CLK_DSI_CORE_DIV 342 +#define IMX8MQ_CLK_DSI_CORE 163 /* DSI_PHY */ -#define IMX8MQ_CLK_DSI_PHY_REF_SRC 343 -#define IMX8MQ_CLK_DSI_PHY_REF_CG 344 -#define IMX8MQ_CLK_DSI_PHY_REF_PRE_DIV 345 -#define IMX8MQ_CLK_DSI_PHY_REF_DIV 346 +#define IMX8MQ_CLK_DSI_PHY_REF 164 /* DSI_DBI */ -#define IMX8MQ_CLK_DSI_DBI_SRC 347 -#define IMX8MQ_CLK_DSI_DBI_CG 348 -#define IMX8MQ_CLK_DSI_DBI_PRE_DIV 349 -#define IMX8MQ_CLK_DSI_DBI_DIV 350 +#define IMX8MQ_CLK_DSI_DBI 165 /*DSI_ESC */ -#define IMX8MQ_CLK_DSI_ESC_SRC 351 -#define IMX8MQ_CLK_DSI_ESC_CG 352 -#define IMX8MQ_CLK_DSI_ESC_PRE_DIV 353 -#define IMX8MQ_CLK_DSI_ESC_DIV 354 +#define IMX8MQ_CLK_DSI_ESC 166 /* CSI1_CORE */ -#define IMX8MQ_CLK_CSI1_CORE_SRC 355 -#define IMX8MQ_CLK_CSI1_CORE_CG 356 -#define IMX8MQ_CLK_CSI1_CORE_PRE_DIV 357 -#define IMX8MQ_CLK_CSI1_CORE_DIV 358 +#define IMX8MQ_CLK_CSI1_CORE 167 /* CSI1_PHY */ -#define IMX8MQ_CLK_CSI1_PHY_REF_SRC 359 -#define IMX8MQ_CLK_CSI1_PHY_REF_CG 360 -#define IMX8MQ_CLK_CSI1_PHY_REF_PRE_DIV 361 -#define IMX8MQ_CLK_CSI1_PHY_REF_DIV 362 +#define IMX8MQ_CLK_CSI1_PHY_REF 168 /* CSI_ESC */ -#define IMX8MQ_CLK_CSI1_ESC_SRC 363 -#define IMX8MQ_CLK_CSI1_ESC_CG 364 -#define IMX8MQ_CLK_CSI1_ESC_PRE_DIV 365 -#define IMX8MQ_CLK_CSI1_ESC_DIV 366 +#define IMX8MQ_CLK_CSI1_ESC 169 /* CSI2_CORE */ -#define IMX8MQ_CLK_CSI2_CORE_SRC 367 -#define IMX8MQ_CLK_CSI2_CORE_CG 368 -#define IMX8MQ_CLK_CSI2_CORE_PRE_DIV 369 -#define IMX8MQ_CLK_CSI2_CORE_DIV 370 +#define IMX8MQ_CLK_CSI2_CORE 170 /* CSI2_PHY */ -#define IMX8MQ_CLK_CSI2_PHY_REF_SRC 371 -#define IMX8MQ_CLK_CSI2_PHY_REF_CG 372 -#define IMX8MQ_CLK_CSI2_PHY_REF_PRE_DIV 373 -#define IMX8MQ_CLK_CSI2_PHY_REF_DIV 374 +#define IMX8MQ_CLK_CSI2_PHY_REF 171 /* CSI2_ESC */ -#define IMX8MQ_CLK_CSI2_ESC_SRC 375 -#define IMX8MQ_CLK_CSI2_ESC_CG 376 -#define IMX8MQ_CLK_CSI2_ESC_PRE_DIV 377 -#define IMX8MQ_CLK_CSI2_ESC_DIV 378 +#define IMX8MQ_CLK_CSI2_ESC 172 /* PCIE2_CTRL */ -#define IMX8MQ_CLK_PCIE2_CTRL_SRC 379 -#define IMX8MQ_CLK_PCIE2_CTRL_CG 380 -#define IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV 381 -#define IMX8MQ_CLK_PCIE2_CTRL_DIV 382 +#define IMX8MQ_CLK_PCIE2_CTRL 173 /* PCIE2_PHY */ -#define IMX8MQ_CLK_PCIE2_PHY_SRC 383 -#define IMX8MQ_CLK_PCIE2_PHY_CG 384 -#define IMX8MQ_CLK_PCIE2_PHY_PRE_DIV 385 -#define IMX8MQ_CLK_PCIE2_PHY_DIV 386 +#define IMX8MQ_CLK_PCIE2_PHY 174 /* PCIE2_AUX */ -#define IMX8MQ_CLK_PCIE2_AUX_SRC 387 -#define IMX8MQ_CLK_PCIE2_AUX_CG 388 -#define IMX8MQ_CLK_PCIE2_AUX_PRE_DIV 389 -#define IMX8MQ_CLK_PCIE2_AUX_DIV 390 +#define IMX8MQ_CLK_PCIE2_AUX 175 /* ECSPI3 */ -#define IMX8MQ_CLK_ECSPI3_SRC 391 -#define IMX8MQ_CLK_ECSPI3_CG 392 -#define IMX8MQ_CLK_ECSPI3_PRE_DIV 393 -#define IMX8MQ_CLK_ECSPI3_DIV 394 +#define IMX8MQ_CLK_ECSPI3 176 /* CCGR clocks */ -#define IMX8MQ_CLK_A53_ROOT 395 -#define IMX8MQ_CLK_DRAM_ROOT 396 -#define IMX8MQ_CLK_ECSPI1_ROOT 397 -#define IMX8MQ_CLK_ECSPI2_ROOT 398 -#define IMX8MQ_CLK_ECSPI3_ROOT 399 -#define IMX8MQ_CLK_ENET1_ROOT 400 -#define IMX8MQ_CLK_GPT1_ROOT 401 -#define IMX8MQ_CLK_I2C1_ROOT 402 -#define IMX8MQ_CLK_I2C2_ROOT 403 -#define IMX8MQ_CLK_I2C3_ROOT 404 -#define IMX8MQ_CLK_I2C4_ROOT 405 -#define IMX8MQ_CLK_M4_ROOT 406 -#define IMX8MQ_CLK_PCIE1_ROOT 407 -#define IMX8MQ_CLK_PCIE2_ROOT 408 -#define IMX8MQ_CLK_PWM1_ROOT 409 -#define IMX8MQ_CLK_PWM2_ROOT 410 -#define IMX8MQ_CLK_PWM3_ROOT 411 -#define IMX8MQ_CLK_PWM4_ROOT 412 -#define IMX8MQ_CLK_QSPI_ROOT 413 -#define IMX8MQ_CLK_SAI1_ROOT 414 -#define IMX8MQ_CLK_SAI2_ROOT 415 -#define IMX8MQ_CLK_SAI3_ROOT 416 -#define IMX8MQ_CLK_SAI4_ROOT 417 -#define IMX8MQ_CLK_SAI5_ROOT 418 -#define IMX8MQ_CLK_SAI6_ROOT 419 -#define IMX8MQ_CLK_UART1_ROOT 420 -#define IMX8MQ_CLK_UART2_ROOT 421 -#define IMX8MQ_CLK_UART3_ROOT 422 -#define IMX8MQ_CLK_UART4_ROOT 423 -#define IMX8MQ_CLK_USB1_CTRL_ROOT 424 -#define IMX8MQ_CLK_USB2_CTRL_ROOT 425 -#define IMX8MQ_CLK_USB1_PHY_ROOT 426 -#define IMX8MQ_CLK_USB2_PHY_ROOT 427 -#define IMX8MQ_CLK_USDHC1_ROOT 428 -#define IMX8MQ_CLK_USDHC2_ROOT 429 -#define IMX8MQ_CLK_WDOG1_ROOT 430 -#define IMX8MQ_CLK_WDOG2_ROOT 431 -#define IMX8MQ_CLK_WDOG3_ROOT 432 -#define IMX8MQ_CLK_GPU_ROOT 433 -#define IMX8MQ_CLK_HEVC_ROOT 434 -#define IMX8MQ_CLK_AVC_ROOT 435 -#define IMX8MQ_CLK_VP9_ROOT 436 -#define IMX8MQ_CLK_HEVC_INTER_ROOT 437 -#define IMX8MQ_CLK_DISP_ROOT 438 -#define IMX8MQ_CLK_HDMI_ROOT 439 -#define IMX8MQ_CLK_HDMI_PHY_ROOT 440 -#define IMX8MQ_CLK_VPU_DEC_ROOT 441 -#define IMX8MQ_CLK_CSI1_ROOT 442 -#define IMX8MQ_CLK_CSI2_ROOT 443 -#define IMX8MQ_CLK_RAWNAND_ROOT 444 -#define IMX8MQ_CLK_SDMA1_ROOT 445 -#define IMX8MQ_CLK_SDMA2_ROOT 446 -#define IMX8MQ_CLK_VPU_G1_ROOT 447 -#define IMX8MQ_CLK_VPU_G2_ROOT 448 +#define IMX8MQ_CLK_A53_ROOT 177 +#define IMX8MQ_CLK_DRAM_ROOT 178 +#define IMX8MQ_CLK_ECSPI1_ROOT 179 +#define IMX8MQ_CLK_ECSPI2_ROOT 180 +#define IMX8MQ_CLK_ECSPI3_ROOT 181 +#define IMX8MQ_CLK_ENET1_ROOT 182 +#define IMX8MQ_CLK_GPT1_ROOT 183 +#define IMX8MQ_CLK_I2C1_ROOT 184 +#define IMX8MQ_CLK_I2C2_ROOT 185 +#define IMX8MQ_CLK_I2C3_ROOT 186 +#define IMX8MQ_CLK_I2C4_ROOT 187 +#define IMX8MQ_CLK_M4_ROOT 188 +#define IMX8MQ_CLK_PCIE1_ROOT 189 +#define IMX8MQ_CLK_PCIE2_ROOT 190 +#define IMX8MQ_CLK_PWM1_ROOT 191 +#define IMX8MQ_CLK_PWM2_ROOT 192 +#define IMX8MQ_CLK_PWM3_ROOT 193 +#define IMX8MQ_CLK_PWM4_ROOT 194 +#define IMX8MQ_CLK_QSPI_ROOT 195 +#define IMX8MQ_CLK_SAI1_ROOT 196 +#define IMX8MQ_CLK_SAI2_ROOT 197 +#define IMX8MQ_CLK_SAI3_ROOT 198 +#define IMX8MQ_CLK_SAI4_ROOT 199 +#define IMX8MQ_CLK_SAI5_ROOT 200 +#define IMX8MQ_CLK_SAI6_ROOT 201 +#define IMX8MQ_CLK_UART1_ROOT 202 +#define IMX8MQ_CLK_UART2_ROOT 203 +#define IMX8MQ_CLK_UART3_ROOT 204 +#define IMX8MQ_CLK_UART4_ROOT 205 +#define IMX8MQ_CLK_USB1_CTRL_ROOT 206 +#define IMX8MQ_CLK_USB2_CTRL_ROOT 207 +#define IMX8MQ_CLK_USB1_PHY_ROOT 208 +#define IMX8MQ_CLK_USB2_PHY_ROOT 209 +#define IMX8MQ_CLK_USDHC1_ROOT 210 +#define IMX8MQ_CLK_USDHC2_ROOT 211 +#define IMX8MQ_CLK_WDOG1_ROOT 212 +#define IMX8MQ_CLK_WDOG2_ROOT 213 +#define IMX8MQ_CLK_WDOG3_ROOT 214 +#define IMX8MQ_CLK_GPU_ROOT 215 +#define IMX8MQ_CLK_HEVC_ROOT 216 +#define IMX8MQ_CLK_AVC_ROOT 217 +#define IMX8MQ_CLK_VP9_ROOT 218 +#define IMX8MQ_CLK_HEVC_INTER_ROOT 219 +#define IMX8MQ_CLK_DISP_ROOT 220 +#define IMX8MQ_CLK_HDMI_ROOT 221 +#define IMX8MQ_CLK_HDMI_PHY_ROOT 222 +#define IMX8MQ_CLK_VPU_DEC_ROOT 223 +#define IMX8MQ_CLK_CSI1_ROOT 224 +#define IMX8MQ_CLK_CSI2_ROOT 225 +#define IMX8MQ_CLK_RAWNAND_ROOT 226 +#define IMX8MQ_CLK_SDMA1_ROOT 227 +#define IMX8MQ_CLK_SDMA2_ROOT 228 +#define IMX8MQ_CLK_VPU_G1_ROOT 229 +#define IMX8MQ_CLK_VPU_G2_ROOT 230 /* SCCG PLL GATE */ -#define IMX8MQ_SYS1_PLL_OUT 449 -#define IMX8MQ_SYS2_PLL_OUT 450 -#define IMX8MQ_SYS3_PLL_OUT 451 -#define IMX8MQ_DRAM_PLL_OUT 452 - -#define IMX8MQ_GPT_3M_CLK 453 - -#define IMX8MQ_CLK_IPG_ROOT 454 -#define IMX8MQ_CLK_IPG_AUDIO_ROOT 455 -#define IMX8MQ_CLK_SAI1_IPG 456 -#define IMX8MQ_CLK_SAI2_IPG 457 -#define IMX8MQ_CLK_SAI3_IPG 458 -#define IMX8MQ_CLK_SAI4_IPG 459 -#define IMX8MQ_CLK_SAI5_IPG 460 -#define IMX8MQ_CLK_SAI6_IPG 461 +#define IMX8MQ_SYS1_PLL_OUT 231 +#define IMX8MQ_SYS2_PLL_OUT 232 +#define IMX8MQ_SYS3_PLL_OUT 233 +#define IMX8MQ_DRAM_PLL_OUT 234 + +#define IMX8MQ_GPT_3M_CLK 235 + +#define IMX8MQ_CLK_IPG_ROOT 236 +#define IMX8MQ_CLK_IPG_AUDIO_ROOT 237 +#define IMX8MQ_CLK_SAI1_IPG 238 +#define IMX8MQ_CLK_SAI2_IPG 239 +#define IMX8MQ_CLK_SAI3_IPG 240 +#define IMX8MQ_CLK_SAI4_IPG 241 +#define IMX8MQ_CLK_SAI5_IPG 242 +#define IMX8MQ_CLK_SAI6_IPG 243 /* DSI AHB/IPG clocks */ /* rxesc clock */ -#define IMX8MQ_CLK_DSI_AHB_SRC 462 -#define IMX8MQ_CLK_DSI_AHB_CG 463 -#define IMX8MQ_CLK_DSI_AHB_PRE_DIV 464 -#define IMX8MQ_CLK_DSI_AHB_DIV 465 +#define IMX8MQ_CLK_DSI_AHB 244 /* txesc clock */ -#define IMX8MQ_CLK_DSI_IPG_DIV 466 - -/* VIDEO2 PLL */ -#define IMX8MQ_VIDEO2_PLL1_REF_SEL 467 -#define IMX8MQ_VIDEO2_PLL1_REF_DIV 468 -#define IMX8MQ_VIDEO2_PLL1 469 -#define IMX8MQ_VIDEO2_PLL1_OUT 470 -#define IMX8MQ_VIDEO2_PLL1_OUT_DIV 471 -#define IMX8MQ_VIDEO2_PLL2 472 -#define IMX8MQ_VIDEO2_PLL2_DIV 473 -#define IMX8MQ_VIDEO2_PLL2_OUT 474 -#define IMX8MQ_CLK_TMU_ROOT 475 - -#define IMX8MQ_CLK_END 476 +#define IMX8MQ_CLK_DSI_IPG_DIV 245 + +#define IMX8MQ_CLK_TMU_ROOT 246 + +/* Display root clocks */ +#define IMX8MQ_CLK_DISP_AXI_ROOT 247 +#define IMX8MQ_CLK_DISP_APB_ROOT 248 +#define IMX8MQ_CLK_DISP_RTRM_ROOT 249 + +#define IMX8MQ_CLK_OCOTP_ROOT 250 + +#define IMX8MQ_CLK_DRAM_ALT_ROOT 251 +#define IMX8MQ_CLK_DRAM_CORE 252 + +#define IMX8MQ_CLK_MU_ROOT 253 +#define IMX8MQ_VIDEO2_PLL_OUT 254 + +#define IMX8MQ_CLK_CLKO2 255 + +#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 256 + +#define IMX8MQ_CLK_CLKO1 257 +#define IMX8MQ_CLK_ARM 258 + +#define IMX8MQ_CLK_GPIO1_ROOT 259 +#define IMX8MQ_CLK_GPIO2_ROOT 260 +#define IMX8MQ_CLK_GPIO3_ROOT 261 +#define IMX8MQ_CLK_GPIO4_ROOT 262 +#define IMX8MQ_CLK_GPIO5_ROOT 263 + +#define IMX8MQ_CLK_SNVS_ROOT 264 +#define IMX8MQ_CLK_GIC 265 + +#define IMX8MQ_CLK_END 266 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ -- cgit v1.2.1 From b72dd938ece60fba622a989f4e54f0599b5a0715 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?S=C3=A9bastien=20Szymanski?= Date: Mon, 21 Oct 2019 15:33:02 +0200 Subject: imx6ul: opos6ul: migrate to DM_ETH MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Migrate to DM_ETH and remove code that is no longer necessary. Reviewed-by: Peng Fan Signed-off-by: Sébastien Szymanski --- include/configs/opos6uldev.h | 8 -------- 1 file changed, 8 deletions(-) (limited to 'include') diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 309b4717c4..744317ddae 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -41,14 +41,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif -/* Ethernet */ -#ifdef CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1 -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "FEC" -#endif - /* LCD */ #ifndef CONFIG_SPL_BUILD #ifdef CONFIG_VIDEO -- cgit v1.2.1 From b1be79b4174b06d60335d2fac901e079fb27aa97 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?S=C3=A9bastien=20Szymanski?= Date: Mon, 21 Oct 2019 15:33:03 +0200 Subject: opos6uldev: migrate to DM_VIDEO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Migrate to DM_VIDEO, update the device tree and remove code that is no longer necessary. Reviewed-by: Peng Fan Signed-off-by: Sébastien Szymanski --- include/configs/opos6uldev.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 744317ddae..f80e34729a 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -43,7 +43,7 @@ /* LCD */ #ifndef CONFIG_SPL_BUILD -#ifdef CONFIG_VIDEO +#ifdef CONFIG_DM_VIDEO #define CONFIG_VIDEO_LOGO #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN @@ -51,6 +51,8 @@ #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_VIDEO_BMP_LOGO #define CONFIG_BMP_16BPP +#define CONFIG_BMP_24BPP +#define CONFIG_BMP_32BPP #define CONFIG_VIDEO_MXS #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR #endif @@ -87,6 +89,8 @@ "mmcroot=/dev/mmcblk0p2 ro\0" \ "mmcrootfstype=ext4 rootwait\0" \ "kernelimg=" __stringify(CONFIG_BOARD_NAME) "-linux.bin\0" \ + "splashpos=0,0\0" \ + "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ "videomode=video=ctfb:x:800,y:480,depth:18,pclk:33033,le:96,ri:96,up:20,lo:21,hs:64,vs:4,sync:0,vmode:0\0" \ "check_env=if test -n ${flash_env_version}; " \ "then env default env_version; " \ -- cgit v1.2.1 From 698c4398159f88aed87e762518b666396d8fa87d Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 16 Oct 2019 10:24:28 +0000 Subject: dt-bindings: import usb pd Import usb pd bindings from Linux 5.4.0-rc1. This file will be included by imx8mm-evk.dts. Signed-off-by: Peng Fan --- include/dt-bindings/usb/pd.h | 88 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 include/dt-bindings/usb/pd.h (limited to 'include') diff --git a/include/dt-bindings/usb/pd.h b/include/dt-bindings/usb/pd.h new file mode 100644 index 0000000000..985f2bbd4d --- /dev/null +++ b/include/dt-bindings/usb/pd.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_POWER_DELIVERY_H +#define __DT_POWER_DELIVERY_H + +/* Power delivery Power Data Object definitions */ +#define PDO_TYPE_FIXED 0 +#define PDO_TYPE_BATT 1 +#define PDO_TYPE_VAR 2 +#define PDO_TYPE_APDO 3 + +#define PDO_TYPE_SHIFT 30 +#define PDO_TYPE_MASK 0x3 + +#define PDO_TYPE(t) ((t) << PDO_TYPE_SHIFT) + +#define PDO_VOLT_MASK 0x3ff +#define PDO_CURR_MASK 0x3ff +#define PDO_PWR_MASK 0x3ff + +#define PDO_FIXED_DUAL_ROLE (1 << 29) /* Power role swap supported */ +#define PDO_FIXED_SUSPEND (1 << 28) /* USB Suspend supported (Source) */ +#define PDO_FIXED_HIGHER_CAP (1 << 28) /* Requires more than vSafe5V (Sink) */ +#define PDO_FIXED_EXTPOWER (1 << 27) /* Externally powered */ +#define PDO_FIXED_USB_COMM (1 << 26) /* USB communications capable */ +#define PDO_FIXED_DATA_SWAP (1 << 25) /* Data role swap supported */ +#define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */ +#define PDO_FIXED_CURR_SHIFT 0 /* 10mA units */ + +#define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT) +#define PDO_FIXED_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT) + +#define PDO_FIXED(mv, ma, flags) \ + (PDO_TYPE(PDO_TYPE_FIXED) | (flags) | \ + PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma)) + +#define VSAFE5V 5000 /* mv units */ + +#define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */ +#define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */ +#define PDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */ + +#define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT) +#define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT) +#define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT) + +#define PDO_BATT(min_mv, max_mv, max_mw) \ + (PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) | \ + PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw)) + +#define PDO_VAR_MAX_VOLT_SHIFT 20 /* 50mV units */ +#define PDO_VAR_MIN_VOLT_SHIFT 10 /* 50mV units */ +#define PDO_VAR_MAX_CURR_SHIFT 0 /* 10mA units */ + +#define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT) +#define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT) +#define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT) + +#define PDO_VAR(min_mv, max_mv, max_ma) \ + (PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) | \ + PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma)) + +#define APDO_TYPE_PPS 0 + +#define PDO_APDO_TYPE_SHIFT 28 /* Only valid value currently is 0x0 - PPS */ +#define PDO_APDO_TYPE_MASK 0x3 + +#define PDO_APDO_TYPE(t) ((t) << PDO_APDO_TYPE_SHIFT) + +#define PDO_PPS_APDO_MAX_VOLT_SHIFT 17 /* 100mV units */ +#define PDO_PPS_APDO_MIN_VOLT_SHIFT 8 /* 100mV units */ +#define PDO_PPS_APDO_MAX_CURR_SHIFT 0 /* 50mA units */ + +#define PDO_PPS_APDO_VOLT_MASK 0xff +#define PDO_PPS_APDO_CURR_MASK 0x7f + +#define PDO_PPS_APDO_MIN_VOLT(mv) \ + ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MIN_VOLT_SHIFT) +#define PDO_PPS_APDO_MAX_VOLT(mv) \ + ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MAX_VOLT_SHIFT) +#define PDO_PPS_APDO_MAX_CURR(ma) \ + ((((ma) / 50) & PDO_PPS_APDO_CURR_MASK) << PDO_PPS_APDO_MAX_CURR_SHIFT) + +#define PDO_PPS_APDO(min_mv, max_mv, max_ma) \ + (PDO_TYPE(PDO_TYPE_APDO) | PDO_APDO_TYPE(APDO_TYPE_PPS) | \ + PDO_PPS_APDO_MIN_VOLT(min_mv) | PDO_PPS_APDO_MAX_VOLT(max_mv) | \ + PDO_PPS_APDO_MAX_CURR(max_ma)) + + #endif /* __DT_POWER_DELIVERY_H */ -- cgit v1.2.1 From b06ff8f50dd54f57174c454f23ae50fd5dc074e4 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 25 Sep 2019 08:11:17 +0000 Subject: imx8qm: mek: add secure boot script Add secure boot script, use ahab to verify image Signed-off-by: Peng Fan --- include/configs/imx8qm_mek.h | 64 +++++++++++++++++++++++++++++++++----------- 1 file changed, 49 insertions(+), 15 deletions(-) (limited to 'include') diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 2b8f85ded1..37ef595e4e 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -54,8 +54,15 @@ #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ + AHAB_ENV \ "script=boot.scr\0" \ "image=Image\0" \ "panel=NULL\0" \ @@ -76,16 +83,27 @@ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "boot_os=booti ${loadaddr} - ${fdt_addr};\0" \ + "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ + "auth_os=auth_cntr ${cntr_addr}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ + "if test ${sec_boot} = yes; then " \ + "if run auth_os; then " \ + "run boot_os; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "echo ERR: failed to authenticate; " \ "fi; " \ "else " \ - "echo wait for boot; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;" \ "fi;\0" \ "netargs=setenv bootargs console=${console} " \ "root=/dev/nfs " \ @@ -97,15 +115,24 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${loadaddr} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ + "if test ${sec_boot} = yes; then " \ + "${get_cmd} ${cntr_addr} ${cntr_file}; " \ + "if run auth_os; then " \ + "run boot_os; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "echo ERR: failed to authenticate; " \ "fi; " \ "else " \ - "booti; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;" \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -113,10 +140,17 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ + "if test ${sec_boot} = yes; then " \ + "if run loadcntr; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ "fi; " \ "else booti ${loadaddr} - ${fdt_addr}; fi" -- cgit v1.2.1 From 6dcc6cebcf1a0d2ab2b8dde5936556b58807f77d Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 25 Sep 2019 08:11:19 +0000 Subject: imx8qxp: mek: add secure boot script Add secure boot script, use ahab to verify image Signed-off-by: Peng Fan --- include/configs/imx8qxp_mek.h | 64 +++++++++++++++++++++++++++++++++---------- 1 file changed, 49 insertions(+), 15 deletions(-) (limited to 'include') diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 872805cae6..59f88bd203 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -53,8 +53,15 @@ #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ + AHAB_ENV \ "script=boot.scr\0" \ "image=Image\0" \ "panel=NULL\0" \ @@ -75,16 +82,27 @@ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ + "auth_os=auth_cntr ${cntr_addr}\0" \ + "boot_os=booti ${loadaddr} - ${fdt_addr};\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ + "if test ${sec_boot} = yes; then " \ + "if run auth_os; then " \ + "run boot_os; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "echo ERR: failed to authenticate; " \ "fi; " \ "else " \ - "echo wait for boot; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;" \ "fi;\0" \ "netargs=setenv bootargs console=${console} " \ "root=/dev/nfs " \ @@ -96,15 +114,24 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${loadaddr} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ + "if test ${sec_boot} = yes; then " \ + "${get_cmd} ${cntr_addr} ${cntr_file}; " \ + "if run auth_os; then " \ + "run boot_os; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "echo ERR: failed to authenticate; " \ "fi; " \ "else " \ - "booti; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;" \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -112,10 +139,17 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ + "if test ${sec_boot} = yes; then " \ + "if run loadcntr; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ "fi; " \ "else booti ${loadaddr} - ${fdt_addr}; fi" -- cgit v1.2.1 From c04ac5bd408f3e132eb458b24fef8c0e11751b3c Mon Sep 17 00:00:00 2001 From: Hannes Schmelzer Date: Wed, 17 Jul 2019 14:29:53 +0200 Subject: board/BuR/brppt2: initial commit This commit adds support for the brppt2 board. The board is based on the i.mx6 dual-lite SoC. Signed-off-by: Hannes Schmelzer --- include/configs/brppt2.h | 120 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 include/configs/brppt2.h (limited to 'include') diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h new file mode 100644 index 0000000000..d369315090 --- /dev/null +++ b/include/configs/brppt2.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Config file for BuR BRPP2_IMX6 board + * + * Copyright (C) 2018 + * B&R Industrial Automation GmbH - http://www.br-automation.com/ + */ +#ifndef __CONFIG_BRPP2_IMX6_H +#define __CONFIG_BRPP2_IMX6_H + +#include +#include + +/* -- i.mx6 specifica -- */ +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE L2_PL310_BASE +#endif /* !CONFIG_SYS_L2CACHE_OFF */ + +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_MXC_GPT_HCLK + +#define CONFIG_LOADADDR 0x10700000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* MMC */ +#define CONFIG_FSL_USDHC + +/* Boot */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_MACH_TYPE 0xFFFFFFFF + +/* misc */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +/* Environment */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_OFFSET 0x20000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ +BUR_COMMON_ENV \ +"autoload=0\0" \ +"cfgaddr=0x106F0000\0" \ +"scraddr=0x10700000\0" \ +"loadaddr=0x10800000\0" \ +"dtbaddr=0x12000000\0" \ +"ramaddr=0x12100000\0" \ +"cfgscr=mw ${loadaddr} 0 128\0" \ +"cfgscrl=fdt addr ${dtbaddr} &&"\ +" sf probe; sf read ${cfgaddr} 0x40000 0x10000 && source ${cfgaddr}\0" \ +"console=ttymxc0,115200n8 consoleblank=0 quiet\0" \ +"t50args#0=setenv bootargs b_mode=${b_mode} console=${console} " \ + " root=/dev/mmcblk0p2 rootfstype=ext4 rootwait panic=2 \0" \ +"b_t50lgcy#0=" \ + "load ${loaddev}:2 ${loadaddr} /boot/zImage && " \ + "load ${loaddev}:2 ${dtbaddr} /boot/imx6dl-brppt50.dtb; " \ + "run t50args#0; run cfgscrl; bootz ${loadaddr} - ${dtbaddr}\0" \ +"t50args#1=setenv bootargs console=${console} b_mode=${b_mode}" \ + " rootwait panic=2\0" \ +"b_t50lgcy#1=" \ + "load ${loaddev}:1 ${loadaddr} zImage && " \ + "load ${loaddev}:1 ${dtbaddr} imx6dl-brppt50.dtb && " \ + "load ${loaddev}:1 ${ramaddr} rootfsPPT50.uboot && " \ + "run t50args#1; run cfgscrl; bootz ${loadaddr} ${ramaddr} ${dtbaddr}\0"\ +"b_mmc0=load ${loaddev}:1 ${scraddr} bootscr.img && source ${scraddr}\0" \ +"b_mmc1=load ${loaddev}:1 ${scraddr} /boot/bootscr.img && source ${scraddr}\0" \ +"b_usb0=usb start && load usb 0 ${scraddr} bootscr.img && source ${scraddr}\0" \ +"b_net=tftp ${scraddr} netscript.img && source ${scraddr}\0" \ +"b_tgts_std=mmc0 mmc1 t50lgcy#0 t50lgcy#1 usb0 net\0" \ +"b_tgts_rcy=t50lgcy#1 usb0 net\0" \ +"b_tgts_pme=net usb0 mmc0 mmc1\0" \ +"b_mode=4\0" \ +"b_break=0\0" \ +"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \ +" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \ +" else setenv b_tgts ${b_tgts_std}; fi\0" \ +"b_default=run b_deftgts; for target in ${b_tgts};"\ +" do echo \"### booting ${target} ###\"; run b_${target};" \ +" if test ${b_break} = 1; then; exit; fi; done\0" \ +"loaddev=mmc 0\0" \ +"altbootcmd=setenv b_mode 0; run b_default;\0" \ +"bootlimit=1\0" \ +"net2nor=sf probe && dhcp &&" \ +" tftp ${loadaddr} SPL && sf erase 0 +${filesize} &&" \ +" sf write ${loadaddr} 400 ${filesize} &&" \ +" tftp ${loadaddr} u-boot-dtb.img && sf erase 0x100000 +${filesize} &&" \ +" sf write ${loadaddr} 0x100000 ${filesize}\0" + +/* RAM */ +#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Ethernet */ +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_FIXED_SPEED _1000BASET +#define CONFIG_ARP_TIMEOUT 1500UL + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) + +/* SPL */ +#ifdef CONFIG_SPL +#include "imx6_spl.h" + +#endif /* CONFIG_SPL */ +#endif /* __CONFIG_BRPP2_IMX6_H */ -- cgit v1.2.1 From eef72440dbe83b7f1875507505911022e799e709 Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Fri, 20 Sep 2019 07:08:41 +0000 Subject: imx: support i.MX8QM ROM 7720 a1 board Add i.MX8QM ROM 7720a1 board support Boot log as below: U-Boot 2019.10-rc3-00004-gd073e0242f (Sep 20 2019 - 08:24:13 +0200) CPU: NXP i.MX8QM RevB A53 at 1200 MHz Model: Advantech iMX8QM Qseven series Board: ROM-7720-A1 4GB Build: SCFW 65afe5f6 Boot: SD2 DRAM: 4 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 Net: eth0: ethernet@5b040000Could not get PHY for FEC1: addr 1 , eth-1: ethernet@5b050000 Hit any key to stop autoboot: 0 Signed-off-by: Oliver Graute Cc: Stefano Babic Cc: Fabio Estevam Cc: Peng Fan Cc: Simon Glass Cc: Ye Li Cc: uboot-imx --- include/configs/imx8qm_rom7720.h | 180 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 180 insertions(+) create mode 100644 include/configs/imx8qm_rom7720.h (limited to 'include') diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h new file mode 100644 index 0000000000..fb31dc4627 --- /dev/null +++ b/include/configs/imx8qm_rom7720.h @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + */ + +#ifndef __IMX8QM_ROM7720_H +#define __IMX8QM_ROM7720_H + +#include +#include +#define CONFIG_REMAKE_ELF + +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ + +#undef CONFIG_BOOTM_NETBSD + +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +/* FUSE command */ +#define CONFIG_CMD_FUSE + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "m4_1_image=m4_1.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \ + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + MFG_NAND_PARTITION \ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=imx8qm-rom7720-a1.dtb\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp rw earlycon\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +/* Default environment is in SD */ +#define CONFIG_ENV_SIZE 0x2000 + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_ENV_OFFSET (4 * 1024 * 1024) +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#else +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board, + * USDHC3 is for SD on base board On DDR4 board, USDHC1 is mux for NAND, + * USDHC2 is for SD, USDHC3 is for SD on base board + */ +#define CONFIG_SYS_MMC_ENV_DEV 2 /* USDHC3 */ +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ +#define CONFIG_SYS_FSL_USDHC_NUM 3 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +/* LPDDR4 board total DDR is 6GB, DDR4 board total DDR is 4 GB */ +#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */ + +#define CONFIG_SYS_MEMTEST_START 0xA0000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2)) + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +/* Networking */ +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC + +#endif /* __IMX8QM_ROM7720_H */ -- cgit v1.2.1 From 9ab5f221a5e2b79ec98efa6b44f7e3d03c518bf8 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Sun, 3 Nov 2019 16:49:43 +0100 Subject: nand: mxs_nand: add API for switching different BCH layouts On i.MX7 in a sake of reducing the disturbances caused by a neighboring cells in the FCB page in the NAND chip, a randomizer is enabled when reading the FCB page by ROM bootloader. Add API for setting BCH to specific layout (and restoring it back) used by ROM bootloader to be able to burn it in a proper way to NAND using nandbcb command. Signed-off-by: Igor Opaniuk Signed-off-by: Anti Sullin Tested-by: Max Krummenacher Reviewed-by: Oleksandr Suvorov --- include/mxs_nand.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'include') diff --git a/include/mxs_nand.h b/include/mxs_nand.h index 4bd65cded9..ada20483d0 100644 --- a/include/mxs_nand.h +++ b/include/mxs_nand.h @@ -66,8 +66,30 @@ struct mxs_nand_info { /* DMA descriptors */ struct mxs_dma_desc **desc; uint32_t desc_index; + + /* Hardware BCH interface and randomizer */ + u32 en_randomizer; + u32 writesize; + u32 oobsize; + u32 bch_flash0layout0; + u32 bch_flash0layout1; +}; + +struct mxs_nand_layout { + u32 nblocks; + u32 meta_size; + u32 data0_size; + u32 ecc0; + u32 datan_size; + u32 eccn; }; int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info); int mxs_nand_init_spl(struct nand_chip *nand); int mxs_nand_setup_ecc(struct mtd_info *mtd); + +void mxs_nand_mode_fcb(struct mtd_info *mtd); +void mxs_nand_mode_normal(struct mtd_info *mtd); +u32 mxs_nand_mark_byte_offset(struct mtd_info *mtd); +u32 mxs_nand_mark_bit_offset(struct mtd_info *mtd); +void mxs_nand_get_layout(struct mtd_info *mtd, struct mxs_nand_layout *l); -- cgit v1.2.1