From 26e054c943a7348904a8b432fc9a85185b0861c7 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Mon, 5 Aug 2019 15:54:59 +0530 Subject: arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- include/versalpl.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 include/versalpl.h (limited to 'include/versalpl.h') diff --git a/include/versalpl.h b/include/versalpl.h new file mode 100644 index 0000000000..b94c82e6e6 --- /dev/null +++ b/include/versalpl.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2019 Xilinx, Inc, + * Siva Durga Prasad Paladugu + */ + +#ifndef _VERSALPL_H_ +#define _VERSALPL_H_ + +#include + +#define VERSAL_PM_LOAD_PDI 0x701 +#define VERSAL_PM_PDI_TYPE 0xF + +extern struct xilinx_fpga_op versal_op; + +#define XILINX_VERSAL_DESC \ +{ xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op } + +#endif /* _VERSALPL_H_ */ -- cgit v1.2.1