From a832ddba55f79801b6f75b79e96c3f5e1469335a Mon Sep 17 00:00:00 2001
From: Pavel Machek <pavel@denx.de>
Date: Mon, 8 Sep 2014 14:08:45 +0200
Subject: arm: socfpga: clock: Add code to read clock configuration

Add the entire bulk of code to read out clock configuration from the SoCFPGA
CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
they cannot determine the frequency of their upstream clock.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>

V2: Fixed the L4 MP clock divider and synced the clock code with latest
    rocketboards codebase (thanks Dinh for pointing this out)
---
 include/configs/socfpga_cyclone5.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include/configs/socfpga_cyclone5.h')

diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 39e9368340..708309b08f 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -24,6 +24,7 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_SINGLE_BOOTLOADER
 #define CONFIG_SOCFPGA
+#define CONFIG_CLOCKS
 
 /* base address for .text section */
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-- 
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