From 36bf57b6fb37089510b6dcfa6487dc5e2445c9f2 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 4 Apr 2014 15:25:11 +0900 Subject: arm: remove lubbock board support Enough time has passed since this board was moved to Orphan. Remove. - Remove board/lubbock/* - Remove include/configs/lubbock.h - Cleanup defined(CONFIG_LUBBOCK) - Move the entry from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada --- drivers/net/lan91c96.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'drivers/net') diff --git a/drivers/net/lan91c96.h b/drivers/net/lan91c96.h index 2f0d640ade..3e914ce5ad 100644 --- a/drivers/net/lan91c96.h +++ b/drivers/net/lan91c96.h @@ -58,13 +58,7 @@ typedef unsigned long int dword; #ifdef CONFIG_CPU_PXA25X -#ifdef CONFIG_LUBBOCK -#define SMC_IO_SHIFT 2 -#undef USE_32_BIT - -#else #define SMC_IO_SHIFT 0 -#endif #define SMCREG(edev, r) ((edev)->iobase+((r)< Date: Mon, 7 Apr 2014 16:41:46 +0100 Subject: pcnet: access descriptor rings & init block uncached The prior accesses to the descriptor rings & init block via cached memory had a few issues: - The memory needs cache flushes or invalidation at the appropriate times, but was not necessarily aligned on cache line boundaries. This could lead to data being incorrectly lost or written back to RAM at the wrong time. - There are points where ordering of writes to the memory is important, but because it's cached memory the pcnet controller would see cache lines written back ordered by address. This could occasionally lead to hardware seeing descriptors in an incorrect state. - Flushing the cache constantly is inefficient. So, to avoid all of those issues simply access the descriptors & init block via uncached memory. The MIPS-specific UNCACHED_SDRAM macro is used to do this (retrieving an address in kseg1) as I could see no existing generic solution. Since the MIPS Malta board is the only user of the pcnet driver, hopefully this doesn't matter. Signed-off-by: Paul Burton --- drivers/net/pcnet.c | 66 ++++++++++++++++++++++++++++------------------------- 1 file changed, 35 insertions(+), 31 deletions(-) (limited to 'drivers/net') diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 71a3110712..8c334c7abc 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -71,10 +71,14 @@ struct pcnet_init_block { u32 reserved2; }; -typedef struct pcnet_priv { +struct pcnet_uncached_priv { struct pcnet_rx_head rx_ring[RX_RING_SIZE]; struct pcnet_tx_head tx_ring[TX_RING_SIZE]; struct pcnet_init_block init_block; +}; + +typedef struct pcnet_priv { + struct pcnet_uncached_priv *uc; /* Receive Buffer space */ unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; int cur_rx; @@ -283,6 +287,7 @@ static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr) static int pcnet_init(struct eth_device *dev, bd_t *bis) { + struct pcnet_uncached_priv *uc; int i, val; u32 addr; @@ -325,24 +330,31 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis) addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10); addr = (addr + 0xf) & ~0xf; lp = (pcnet_priv_t *)addr; + + addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->uc)); + flush_dcache_range(addr, addr + sizeof(*lp->uc)); + addr = UNCACHED_SDRAM(addr); + lp->uc = (struct pcnet_uncached_priv *)addr; } - lp->init_block.mode = cpu_to_le16(0x0000); - lp->init_block.filter[0] = 0x00000000; - lp->init_block.filter[1] = 0x00000000; + uc = lp->uc; + + uc->init_block.mode = cpu_to_le16(0x0000); + uc->init_block.filter[0] = 0x00000000; + uc->init_block.filter[1] = 0x00000000; /* * Initialize the Rx ring. */ lp->cur_rx = 0; for (i = 0; i < RX_RING_SIZE; i++) { - lp->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]); - lp->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ); - lp->rx_ring[i].status = cpu_to_le16(0x8000); + uc->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]); + uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ); + uc->rx_ring[i].status = cpu_to_le16(0x8000); PCNET_DEBUG1 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i, - lp->rx_ring[i].base, lp->rx_ring[i].buf_length, - lp->rx_ring[i].status); + uc->rx_ring[i].base, uc->rx_ring[i].buf_length, + uc->rx_ring[i].status); } /* @@ -351,34 +363,34 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis) */ lp->cur_tx = 0; for (i = 0; i < TX_RING_SIZE; i++) { - lp->tx_ring[i].base = 0; - lp->tx_ring[i].status = 0; + uc->tx_ring[i].base = 0; + uc->tx_ring[i].status = 0; } /* * Setup Init Block. */ - PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->init_block); + PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block); for (i = 0; i < 6; i++) { - lp->init_block.phys_addr[i] = dev->enetaddr[i]; - PCNET_DEBUG1(" %02x", lp->init_block.phys_addr[i]); + lp->uc->init_block.phys_addr[i] = dev->enetaddr[i]; + PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]); } - lp->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS | + uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS | RX_RING_LEN_BITS); - lp->init_block.rx_ring = PCI_TO_MEM_LE(dev, lp->rx_ring); - lp->init_block.tx_ring = PCI_TO_MEM_LE(dev, lp->tx_ring); - flush_dcache_range((unsigned long)lp, (unsigned long)&lp->rx_buf); + uc->init_block.rx_ring = PCI_TO_MEM_LE(dev, uc->rx_ring); + uc->init_block.tx_ring = PCI_TO_MEM_LE(dev, uc->tx_ring); PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", - lp->init_block.tlen_rlen, - lp->init_block.rx_ring, lp->init_block.tx_ring); + uc->init_block.tlen_rlen, + uc->init_block.rx_ring, uc->init_block.tx_ring); /* * Tell the controller where the Init Block is located. */ - addr = PCI_TO_MEM(dev, &lp->init_block); + barrier(); + addr = PCI_TO_MEM(dev, &lp->uc->init_block); pcnet_write_csr(dev, 1, addr & 0xffff); pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff); @@ -408,7 +420,7 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis) static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) { int i, status; - struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx]; + struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx]; PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, packet); @@ -418,8 +430,6 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) /* Wait for completion by testing the OWN bit */ for (i = 1000; i > 0; i--) { - invalidate_dcache_range((unsigned long)entry, - (unsigned long)entry + sizeof(*entry)); status = le16_to_cpu(entry->status); if ((status & 0x8000) == 0) break; @@ -442,8 +452,6 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) entry->misc = 0x00000000; entry->base = PCI_TO_MEM_LE(dev, packet); entry->status = cpu_to_le16(status); - flush_dcache_range((unsigned long)entry, - (unsigned long)entry + sizeof(*entry)); /* Trigger an immediate send poll. */ pcnet_write_csr(dev, 0, 0x0008); @@ -463,9 +471,7 @@ static int pcnet_recv (struct eth_device *dev) u16 status; while (1) { - entry = &lp->rx_ring[lp->cur_rx]; - invalidate_dcache_range((unsigned long)entry, - (unsigned long)entry + sizeof(*entry)); + entry = &lp->uc->rx_ring[lp->cur_rx]; /* * If we own the next entry, it's a new packet. Send it up. */ @@ -505,8 +511,6 @@ static int pcnet_recv (struct eth_device *dev) } } entry->status |= cpu_to_le16(0x8000); - flush_dcache_range((unsigned long)entry, - (unsigned long)entry + sizeof(*entry)); if (++lp->cur_rx >= RX_RING_SIZE) lp->cur_rx = 0; -- cgit v1.2.1 From a354ddc3d7412c6d7cc702de60be32e580ccf348 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 7 Apr 2014 16:41:47 +0100 Subject: pcnet: align rx buffers for cache invalidation The RX buffers are invalidated when a packet is received, however they were not suitably cache-line aligned. Allocate them seperately to the pcnet_priv structure and align to ARCH_DMA_MINALIGN in order to ensure suitable alignment for the cache invalidation, preventing anything else being placed in the same lines & lost. Signed-off-by: Paul Burton --- drivers/net/pcnet.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) (limited to 'drivers/net') diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 8c334c7abc..2802411db1 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -80,7 +80,7 @@ struct pcnet_uncached_priv { typedef struct pcnet_priv { struct pcnet_uncached_priv *uc; /* Receive Buffer space */ - unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; + unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4]; int cur_rx; int cur_tx; } pcnet_priv_t; @@ -335,6 +335,10 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis) flush_dcache_range(addr, addr + sizeof(*lp->uc)); addr = UNCACHED_SDRAM(addr); lp->uc = (struct pcnet_uncached_priv *)addr; + + addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->rx_buf)); + flush_dcache_range(addr, addr + sizeof(*lp->rx_buf)); + lp->rx_buf = (void *)addr; } uc = lp->uc; @@ -348,7 +352,7 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis) */ lp->cur_rx = 0; for (i = 0; i < RX_RING_SIZE; i++) { - uc->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]); + uc->rx_ring[i].base = PCI_TO_MEM_LE(dev, (*lp->rx_buf)[i]); uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ); uc->rx_ring[i].status = cpu_to_le16(0x8000); PCNET_DEBUG1 @@ -467,6 +471,7 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) static int pcnet_recv (struct eth_device *dev) { struct pcnet_rx_head *entry; + unsigned char *buf; int pkt_len = 0; u16 status; @@ -500,14 +505,12 @@ static int pcnet_recv (struct eth_device *dev) printf("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len); } else { - invalidate_dcache_range( - (unsigned long)lp->rx_buf[lp->cur_rx], - (unsigned long)lp->rx_buf[lp->cur_rx] + - pkt_len); - NetReceive(lp->rx_buf[lp->cur_rx], pkt_len); + buf = (*lp->rx_buf)[lp->cur_rx]; + invalidate_dcache_range((unsigned long)buf, + (unsigned long)buf + pkt_len); + NetReceive(buf, pkt_len); PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n", - lp->cur_rx, pkt_len, - lp->rx_buf[lp->cur_rx]); + lp->cur_rx, pkt_len, buf); } } entry->status |= cpu_to_le16(0x8000); -- cgit v1.2.1 From 6fb49e4aa08e5d4f4081840b0b30160e98becf27 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 7 Apr 2014 16:41:48 +0100 Subject: pcnet: force ordering of descriptor accesses The ordering of accesses to the rx & tx descriptors is important, yet the send & recv functions accessed them via regular structure accesses. This leaves the compiler with the opportunity to reorder those accesses or to hoist them outside of loops. Prevent that from happening by using readl & writel to access the descriptors. As a nice bonus, this removes the need for the driver to care about endianness. Signed-off-by: Paul Burton --- drivers/net/pcnet.c | 37 +++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 18 deletions(-) (limited to 'drivers/net') diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 2802411db1..237fbba513 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -434,7 +434,7 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) /* Wait for completion by testing the OWN bit */ for (i = 1000; i > 0; i--) { - status = le16_to_cpu(entry->status); + status = readw(&entry->status); if ((status & 0x8000) == 0) break; udelay(100); @@ -451,11 +451,10 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) * Setup Tx ring. Caution: the write order is important here, * set the status with the "ownership" bits last. */ - status = 0x8300; - entry->length = cpu_to_le16(-pkt_len); - entry->misc = 0x00000000; - entry->base = PCI_TO_MEM_LE(dev, packet); - entry->status = cpu_to_le16(status); + writew(-pkt_len, &entry->length); + writel(0, &entry->misc); + writel(PCI_TO_MEM(dev, packet), &entry->base); + writew(0x8300, &entry->status); /* Trigger an immediate send poll. */ pcnet_write_csr(dev, 0, 0x0008); @@ -473,34 +472,34 @@ static int pcnet_recv (struct eth_device *dev) struct pcnet_rx_head *entry; unsigned char *buf; int pkt_len = 0; - u16 status; + u16 status, err_status; while (1) { entry = &lp->uc->rx_ring[lp->cur_rx]; /* * If we own the next entry, it's a new packet. Send it up. */ - status = le16_to_cpu(entry->status); + status = readw(&entry->status); if ((status & 0x8000) != 0) break; - status >>= 8; + err_status = status >> 8; - if (status != 0x03) { /* There was an error. */ + if (err_status != 0x03) { /* There was an error. */ printf("%s: Rx%d", dev->name, lp->cur_rx); - PCNET_DEBUG1(" (status=0x%x)", status); - if (status & 0x20) + PCNET_DEBUG1(" (status=0x%x)", err_status); + if (err_status & 0x20) printf(" Frame"); - if (status & 0x10) + if (err_status & 0x10) printf(" Overflow"); - if (status & 0x08) + if (err_status & 0x08) printf(" CRC"); - if (status & 0x04) + if (err_status & 0x04) printf(" Fifo"); printf(" Error\n"); - entry->status &= le16_to_cpu(0x03ff); + status &= 0x03ff; } else { - pkt_len = (le32_to_cpu(entry->msg_length) & 0xfff) - 4; + pkt_len = (readl(&entry->msg_length) & 0xfff) - 4; if (pkt_len < 60) { printf("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len); @@ -513,7 +512,9 @@ static int pcnet_recv (struct eth_device *dev) lp->cur_rx, pkt_len, buf); } } - entry->status |= cpu_to_le16(0x8000); + + status |= 0x8000; + writew(status, &entry->status); if (++lp->cur_rx >= RX_RING_SIZE) lp->cur_rx = 0; -- cgit v1.2.1 From d2ff5e55c346f012129cbce8b373eafd5f00c9b2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20M=C3=BCller=20=28ELSOFT=20AG=29?= Date: Wed, 16 Apr 2014 13:15:59 +0200 Subject: e1000: remove redundant assignment Signed-off-by: David Mueller Acked-by: Joe Hershberger --- drivers/net/e1000.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/net') diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 9a66e68ae0..9d9b259d64 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -4532,7 +4532,6 @@ static int e1000_set_phy_type (struct e1000_hw *hw) hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2) { hw->phy_type = e1000_phy_igp; - hw->phy_type = e1000_phy_igp; break; } case IGP03E1000_E_PHY_ID: -- cgit v1.2.1 From 538cf92c8c2e8ea7f78c87b5bfb2f705b4b02fa8 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Thu, 10 Apr 2014 00:39:28 +0200 Subject: MIPS: drop incaip board This is dead hardware and no one is interested in making the necessary changes for upcoming features like generic board or driver model. Signed-off-by: Daniel Schwierzeck Cc: Wolfgang Denk --- drivers/net/Makefile | 1 - drivers/net/inca-ip_sw.c | 793 ----------------------------------------------- 2 files changed, 794 deletions(-) delete mode 100644 drivers/net/inca-ip_sw.c (limited to 'drivers/net') diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 7f9ce90a6d..c25b3c93ce 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -29,7 +29,6 @@ obj-$(CONFIG_FTGMAC100) += ftgmac100.o obj-$(CONFIG_FTMAC110) += ftmac110.o obj-$(CONFIG_FTMAC100) += ftmac100.o obj-$(CONFIG_GRETH) += greth.o -obj-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_LAN91C96) += lan91c96.o diff --git a/drivers/net/inca-ip_sw.c b/drivers/net/inca-ip_sw.c deleted file mode 100644 index cdfbfa67d8..0000000000 --- a/drivers/net/inca-ip_sw.c +++ /dev/null @@ -1,793 +0,0 @@ -/* - * INCA-IP internal switch ethernet driver. - * - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include - -#include -#include -#include -#include -#include - - -#define NUM_RX_DESC PKTBUFSRX -#define NUM_TX_DESC 3 -#define TOUT_LOOP 1000000 - - -#define DELAY udelay(10000) - /* Sometimes the store word instruction hangs while writing to one - * of the Switch registers. Moving the instruction into a separate - * function somehow makes the problem go away. - */ -static void SWORD(volatile u32 * reg, u32 value) -{ - *reg = value; -} - -#define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value; -#define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg) -#define SW_WRITE_REG(reg, value) \ - SWORD(reg, value);\ - DELAY;\ - SWORD(reg, value); - -#define SW_READ_REG(reg, value) \ - value = (u32)*((volatile u32*)reg);\ - DELAY;\ - value = (u32)*((volatile u32*)reg); - -#define INCA_DMA_TX_POLLING_TIME 0x07 -#define INCA_DMA_RX_POLLING_TIME 0x07 - -#define INCA_DMA_TX_HOLD 0x80000000 -#define INCA_DMA_TX_EOP 0x40000000 -#define INCA_DMA_TX_SOP 0x20000000 -#define INCA_DMA_TX_ICPT 0x10000000 -#define INCA_DMA_TX_IEOP 0x08000000 - -#define INCA_DMA_RX_C 0x80000000 -#define INCA_DMA_RX_SOP 0x40000000 -#define INCA_DMA_RX_EOP 0x20000000 - -#define INCA_SWITCH_PHY_SPEED_10H 0x1 -#define INCA_SWITCH_PHY_SPEED_10F 0x5 -#define INCA_SWITCH_PHY_SPEED_100H 0x2 -#define INCA_SWITCH_PHY_SPEED_100F 0x6 - -/************************ Auto MDIX settings ************************/ -#define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR -#define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL -#define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT -#define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16 - -#define WAIT_SIGNAL_RETRIES 100 -#define WAIT_LINK_RETRIES 100 -#define LINK_RETRY_DELAY 2000 /* ms */ -/********************************************************************/ - -typedef struct -{ - union { - struct { - volatile u32 HOLD :1; - volatile u32 ICpt :1; - volatile u32 IEop :1; - volatile u32 offset :3; - volatile u32 reserved0 :4; - volatile u32 NFB :22; - }field; - - volatile u32 word; - }params; - - volatile u32 nextRxDescPtr; - - volatile u32 RxDataPtr; - - union { - struct { - volatile u32 C :1; - volatile u32 Sop :1; - volatile u32 Eop :1; - volatile u32 reserved3 :12; - volatile u32 NBT :17; - }field; - - volatile u32 word; - }status; - -} inca_rx_descriptor_t; - - -typedef struct -{ - union { - struct { - volatile u32 HOLD :1; - volatile u32 Eop :1; - volatile u32 Sop :1; - volatile u32 ICpt :1; - volatile u32 IEop :1; - volatile u32 reserved0 :5; - volatile u32 NBA :22; - }field; - - volatile u32 word; - }params; - - volatile u32 nextTxDescPtr; - - volatile u32 TxDataPtr; - - volatile u32 C :1; - volatile u32 reserved3 :31; - -} inca_tx_descriptor_t; - - -static inca_rx_descriptor_t rx_ring[NUM_RX_DESC] __attribute__ ((aligned(16))); -static inca_tx_descriptor_t tx_ring[NUM_TX_DESC] __attribute__ ((aligned(16))); - -static int tx_new, rx_new, tx_hold, rx_hold; -static int tx_old_hold = -1; -static int initialized = 0; - - -static int inca_switch_init(struct eth_device *dev, bd_t * bis); -static int inca_switch_send(struct eth_device *dev, void *packet, int length); -static int inca_switch_recv(struct eth_device *dev); -static void inca_switch_halt(struct eth_device *dev); -static void inca_init_switch_chip(void); -static void inca_dma_init(void); -static int inca_amdix(void); - - -int inca_switch_initialize(bd_t * bis) -{ - struct eth_device *dev; - -#if 0 - printf("Entered inca_switch_initialize()\n"); -#endif - - if (!(dev = (struct eth_device *) malloc (sizeof *dev))) { - printf("Failed to allocate memory\n"); - return 0; - } - memset(dev, 0, sizeof(*dev)); - - inca_dma_init(); - - inca_init_switch_chip(); - -#if defined(CONFIG_INCA_IP_SWITCH_AMDIX) - inca_amdix(); -#endif - - sprintf(dev->name, "INCA-IP Switch"); - dev->init = inca_switch_init; - dev->halt = inca_switch_halt; - dev->send = inca_switch_send; - dev->recv = inca_switch_recv; - - eth_register(dev); - -#if 0 - printf("Leaving inca_switch_initialize()\n"); -#endif - - return 0; -} - - -static int inca_switch_init(struct eth_device *dev, bd_t * bis) -{ - int i; - u32 v, regValue; - u16 wTmp; - -#if 0 - printf("Entering inca_switch_init()\n"); -#endif - - /* Set MAC address. - */ - wTmp = (u16)dev->enetaddr[0]; - regValue = (wTmp << 8) | dev->enetaddr[1]; - - SW_WRITE_REG(INCA_IP_Switch_PMAC_SA1, regValue); - - wTmp = (u16)dev->enetaddr[2]; - regValue = (wTmp << 8) | dev->enetaddr[3]; - regValue = regValue << 16; - wTmp = (u16)dev->enetaddr[4]; - regValue |= (wTmp<<8) | dev->enetaddr[5]; - - SW_WRITE_REG(INCA_IP_Switch_PMAC_SA2, regValue); - - /* Initialize the descriptor rings. - */ - for (i = 0; i < NUM_RX_DESC; i++) { - inca_rx_descriptor_t * rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[i]); - memset(rx_desc, 0, sizeof(rx_ring[i])); - - /* Set maximum size of receive buffer. - */ - rx_desc->params.field.NFB = PKTSIZE_ALIGN; - - /* Set the offset of the receive buffer. Zero means - * that the offset mechanism is not used. - */ - rx_desc->params.field.offset = 0; - - /* Check if it is the last descriptor. - */ - if (i == (NUM_RX_DESC - 1)) { - /* Let the last descriptor point to the first - * one. - */ - rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(rx_ring); - } else { - /* Set the address of the next descriptor. - */ - rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(&rx_ring[i+1]); - } - - rx_desc->RxDataPtr = (u32)CKSEG1ADDR(NetRxPackets[i]); - } - -#if 0 - printf("rx_ring = 0x%08X 0x%08X\n", (u32)rx_ring, (u32)&rx_ring[0]); - printf("tx_ring = 0x%08X 0x%08X\n", (u32)tx_ring, (u32)&tx_ring[0]); -#endif - - for (i = 0; i < NUM_TX_DESC; i++) { - inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[i]); - - memset(tx_desc, 0, sizeof(tx_ring[i])); - - tx_desc->params.word = 0; - tx_desc->params.field.HOLD = 1; - tx_desc->C = 1; - - /* Check if it is the last descriptor. - */ - if (i == (NUM_TX_DESC - 1)) { - /* Let the last descriptor point to the - * first one. - */ - tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(tx_ring); - } else { - /* Set the address of the next descriptor. - */ - tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(&tx_ring[i+1]); - } - } - - /* Initialize RxDMA. - */ - DMA_READ_REG(INCA_IP_DMA_DMA_RXISR, v); - debug("RX status = 0x%08X\n", v); - - /* Writing to the FRDA of CHANNEL. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXFRDA0, (u32)rx_ring); - - /* Writing to the COMMAND REG. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_INIT); - - /* Initialize TxDMA. - */ - DMA_READ_REG(INCA_IP_DMA_DMA_TXISR, v); - debug("TX status = 0x%08X\n", v); - - /* Writing to the FRDA of CHANNEL. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXFRDA0, (u32)tx_ring); - - tx_new = rx_new = 0; - - tx_hold = NUM_TX_DESC - 1; - rx_hold = NUM_RX_DESC - 1; - -#if 0 - rx_ring[rx_hold].params.field.HOLD = 1; -#endif - /* enable spanning tree forwarding, enable the CPU port */ - /* ST_PT: - * CPS (CPU port status) 0x3 (forwarding) - * LPS (LAN port status) 0x3 (forwarding) - * PPS (PC port status) 0x3 (forwarding) - */ - SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f); - -#if 0 - printf("Leaving inca_switch_init()\n"); -#endif - - return 0; -} - - -static int inca_switch_send(struct eth_device *dev, void *packet, int length) -{ - int i; - int res = -1; - u32 command; - u32 regValue; - inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_new]); - -#if 0 - printf("Entered inca_switch_send()\n"); -#endif - - if (length <= 0) { - printf ("%s: bad packet size: %d\n", dev->name, length); - goto Done; - } - - for(i = 0; tx_desc->C == 0; i++) { - if (i >= TOUT_LOOP) { - printf("%s: tx error buffer not ready\n", dev->name); - goto Done; - } - } - - if (tx_old_hold >= 0) { - ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_old_hold]))->params.field.HOLD = 1; - } - tx_old_hold = tx_hold; - - tx_desc->params.word = - (INCA_DMA_TX_SOP | INCA_DMA_TX_EOP | INCA_DMA_TX_HOLD); - - tx_desc->C = 0; - tx_desc->TxDataPtr = (u32)packet; - tx_desc->params.field.NBA = length; - - ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->params.field.HOLD = 0; - - tx_hold = tx_new; - tx_new = (tx_new + 1) % NUM_TX_DESC; - - - if (! initialized) { - command = INCA_IP_DMA_DMA_TXCCR0_INIT; - initialized = 1; - } else { - command = INCA_IP_DMA_DMA_TXCCR0_HR; - } - - DMA_READ_REG(INCA_IP_DMA_DMA_TXCCR0, regValue); - regValue |= command; -#if 0 - printf("regValue = 0x%x\n", regValue); -#endif - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue); - -#if 1 - for(i = 0; ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->C == 0; i++) { - if (i >= TOUT_LOOP) { - printf("%s: tx buffer not ready\n", dev->name); - goto Done; - } - } -#endif - res = length; -Done: -#if 0 - printf("Leaving inca_switch_send()\n"); -#endif - return res; -} - - -static int inca_switch_recv(struct eth_device *dev) -{ - int length = 0; - inca_rx_descriptor_t * rx_desc; - -#if 0 - printf("Entered inca_switch_recv()\n"); -#endif - - for (;;) { - rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_new]); - - if (rx_desc->status.field.C == 0) { - break; - } - -#if 0 - rx_ring[rx_new].params.field.HOLD = 1; -#endif - - if (! rx_desc->status.field.Eop) { - printf("Partly received packet!!!\n"); - break; - } - - length = rx_desc->status.field.NBT; - rx_desc->status.word &= - ~(INCA_DMA_RX_EOP | INCA_DMA_RX_SOP | INCA_DMA_RX_C); -#if 0 -{ - int i; - for (i=0;iparams.field.HOLD = 0; - - rx_hold = rx_new; - - rx_new = (rx_new + 1) % NUM_RX_DESC; - } - -#if 0 - printf("Leaving inca_switch_recv()\n"); -#endif - - return length; -} - - -static void inca_switch_halt(struct eth_device *dev) -{ -#if 0 - printf("Entered inca_switch_halt()\n"); -#endif - -#if 1 - initialized = 0; -#endif -#if 1 - /* Disable forwarding to the CPU port. - */ - SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf); - - /* Close RxDMA channel. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF); - - /* Close TxDMA channel. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_TXCCR0_OFF); - - -#endif -#if 0 - printf("Leaving inca_switch_halt()\n"); -#endif -} - - -static void inca_init_switch_chip(void) -{ - u32 regValue; - - /* To workaround a problem with collision counter - * (see Errata sheet). - */ - SW_WRITE_REG(INCA_IP_Switch_PC_TX_CTL, 0x00000001); - SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001); - -#if 1 - /* init MDIO configuration: - * MDS (Poll speed): 0x01 (4ms) - * PHY_LAN_ADDR: 0x06 - * PHY_PC_ADDR: 0x05 - * UEP (Use External PHY): 0x00 (Internal PHY is used) - * PS (Port Select): 0x00 (PT/UMM for LAN) - * PT (PHY Test): 0x00 (no test mode) - * UMM (Use MDIO Mode): 0x00 (state machine is disabled) - */ - SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50); - - /* init PHY: - * SL (Auto Neg. Speed for LAN) - * SP (Auto Neg. Speed for PC) - * LL (Link Status for LAN) - * LP (Link Status for PC) - * DL (Duplex Status for LAN) - * DP (Duplex Status for PC) - * PL (Auto Neg. Pause Status for LAN) - * PP (Auto Neg. Pause Status for PC) - */ - SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff); - - /* MDIO_ACC: - * RA (Request/Ack) 0x01 (Request) - * RW (Read/Write) 0x01 (Write) - * PHY_ADDR 0x05 (PC) - * REG_ADDR 0x00 (PHY_BCR: basic control register) - * PHY_DATA 0x8000 - * Reset - software reset - * LB (loop back) - normal - * SS (speed select) - 10 Mbit/s - * ANE (auto neg. enable) - enable - * PD (power down) - normal - * ISO (isolate) - normal - * RAN (restart auto neg.) - normal - * DM (duplex mode) - half duplex - * CT (collision test) - enable - */ - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000); - - /* MDIO_ACC: - * RA (Request/Ack) 0x01 (Request) - * RW (Read/Write) 0x01 (Write) - * PHY_ADDR 0x06 (LAN) - * REG_ADDR 0x00 (PHY_BCR: basic control register) - * PHY_DATA 0x8000 - * Reset - software reset - * LB (loop back) - normal - * SS (speed select) - 10 Mbit/s - * ANE (auto neg. enable) - enable - * PD (power down) - normal - * ISO (isolate) - normal - * RAN (restart auto neg.) - normal - * DM (duplex mode) - half duplex - * CT (collision test) - enable - */ - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000); - -#endif - - /* Make sure the CPU port is disabled for now. We - * don't want packets to get stacked for us until - * we enable DMA and are prepared to receive them. - */ - SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf); - - SW_READ_REG(INCA_IP_Switch_ARL_CTL, regValue); - - /* CRC GEN is enabled. - */ - regValue |= 0x00000200; - SW_WRITE_REG(INCA_IP_Switch_ARL_CTL, regValue); - - /* ADD TAG is disabled. - */ - SW_READ_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue); - regValue &= ~0x00000002; - SW_WRITE_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue); -} - - -static void inca_dma_init(void) -{ - /* Switch off all DMA channels. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF); - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR1, INCA_IP_DMA_DMA_RXCCR1_OFF); - - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF); - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR1, INCA_IP_DMA_DMA_TXCCR1_OFF); - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR2, INCA_IP_DMA_DMA_TXCCR2_OFF); - - /* Setup TX channel polling time. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXPOLL, INCA_DMA_TX_POLLING_TIME); - - /* Setup RX channel polling time. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXPOLL, INCA_DMA_RX_POLLING_TIME); - - /* ERRATA: write reset value into the DMA RX IMR register. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXIMR, 0xFFFFFFFF); - - /* Just in case: disable all transmit interrupts also. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXIMR, 0xFFFFFFFF); - - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXISR, 0xFFFFFFFF); - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXISR, 0xFFFFFFFF); -} - -#if defined(CONFIG_INCA_IP_SWITCH_AMDIX) -static int inca_amdix(void) -{ - u32 phyReg1 = 0; - u32 phyReg4 = 0; - u32 phyReg5 = 0; - u32 phyReg6 = 0; - u32 phyReg31 = 0; - u32 regEphy = 0; - int mdi_flag; - int retries; - - /* Setup GPIO pins. - */ - *INCA_IP_AUTO_MDIX_LAN_PORTS_DIR |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); - *INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); - -#if 0 - /* Wait for signal. - */ - retries = WAIT_SIGNAL_RETRIES; - while (--retries) { - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, - (0x1 << 31) | /* RA */ - (0x0 << 30) | /* Read */ - (0x6 << 21) | /* LAN */ - (17 << 16)); /* PHY_MCSR */ - do { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1); - } while (phyReg1 & (1 << 31)); - - if (phyReg1 & (1 << 1)) { - /* Signal detected */ - break; - } - } - - if (!retries) - goto Fail; -#endif - - /* Set MDI mode. - */ - *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); - mdi_flag = 1; - - /* Wait for link. - */ - retries = WAIT_LINK_RETRIES; - while (--retries) { - udelay(LINK_RETRY_DELAY * 1000); - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, - (0x1 << 31) | /* RA */ - (0x0 << 30) | /* Read */ - (0x6 << 21) | /* LAN */ - (1 << 16)); /* PHY_BSR */ - do { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1); - } while (phyReg1 & (1 << 31)); - - if (phyReg1 & (1 << 2)) { - /* Link is up */ - break; - } else if (mdi_flag) { - /* Set MDIX mode */ - *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); - mdi_flag = 0; - } else { - /* Set MDI mode */ - *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); - mdi_flag = 1; - } - } - - if (!retries) { - goto Fail; - } else { - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, - (0x1 << 31) | /* RA */ - (0x0 << 30) | /* Read */ - (0x6 << 21) | /* LAN */ - (1 << 16)); /* PHY_BSR */ - do { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1); - } while (phyReg1 & (1 << 31)); - - /* Auto-negotiation / Parallel detection complete - */ - if (phyReg1 & (1 << 5)) { - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, - (0x1 << 31) | /* RA */ - (0x0 << 30) | /* Read */ - (0x6 << 21) | /* LAN */ - (31 << 16)); /* PHY_SCSR */ - do { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg31); - } while (phyReg31 & (1 << 31)); - - switch ((phyReg31 >> 2) & 0x7) { - case INCA_SWITCH_PHY_SPEED_10H: - /* 10Base-T Half-duplex */ - regEphy = 0; - break; - case INCA_SWITCH_PHY_SPEED_10F: - /* 10Base-T Full-duplex */ - regEphy = INCA_IP_Switch_EPHY_DL; - break; - case INCA_SWITCH_PHY_SPEED_100H: - /* 100Base-TX Half-duplex */ - regEphy = INCA_IP_Switch_EPHY_SL; - break; - case INCA_SWITCH_PHY_SPEED_100F: - /* 100Base-TX Full-duplex */ - regEphy = INCA_IP_Switch_EPHY_SL | INCA_IP_Switch_EPHY_DL; - break; - } - - /* In case of Auto-negotiation, - * update the negotiated PAUSE support status - */ - if (phyReg1 & (1 << 3)) { - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, - (0x1 << 31) | /* RA */ - (0x0 << 30) | /* Read */ - (0x6 << 21) | /* LAN */ - (6 << 16)); /* MII_EXPANSION */ - do { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6); - } while (phyReg6 & (1 << 31)); - - /* We are Autoneg-able. - * Is Link partner also able to autoneg? - */ - if (phyReg6 & (1 << 0)) { - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, - (0x1 << 31) | /* RA */ - (0x0 << 30) | /* Read */ - (0x6 << 21) | /* LAN */ - (4 << 16)); /* MII_ADVERTISE */ - do { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4); - } while (phyReg4 & (1 << 31)); - - /* We advertise PAUSE capab. - * Does link partner also advertise it? - */ - if (phyReg4 & (1 << 10)) { - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, - (0x1 << 31) | /* RA */ - (0x0 << 30) | /* Read */ - (0x6 << 21) | /* LAN */ - (5 << 16)); /* MII_LPA */ - do { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5); - } while (phyReg5 & (1 << 31)); - - /* Link partner is PAUSE capab. - */ - if (phyReg5 & (1 << 10)) { - regEphy |= INCA_IP_Switch_EPHY_PL; - } - } - } - - } - - /* Link is up */ - regEphy |= INCA_IP_Switch_EPHY_LL; - - SW_WRITE_REG(INCA_IP_Switch_EPHY, regEphy); - } - } - - return 0; - -Fail: - printf("No Link on LAN port\n"); - return -1; -} -#endif /* CONFIG_INCA_IP_SWITCH_AMDIX */ -- cgit v1.2.1 From dcf1d774bf5c2612538658eac01931895b7a805f Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Fri, 21 Mar 2014 16:21:44 +0800 Subject: QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and CONFIG_SYS_QE_FW_ADDR CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address. Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address, and CONFIG_SYS_QE_FW_ADDR for QE microcode address. Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- drivers/net/fm/fm.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/net') diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index bca20b3330..400e9dd5e2 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -350,16 +350,16 @@ int fm_init_common(int index, struct ccsr_fman *reg) { int rc; #if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR) - void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR; + void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR; #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND) size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); - rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_ADDR, + rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR, &fw_length, (u_char *)addr); if (rc == -EUCLEAN) { printf("NAND read of FMAN firmware at offset 0x%x failed %d\n", - CONFIG_SYS_QE_FMAN_FW_ADDR, rc); + CONFIG_SYS_FMAN_FW_ADDR, rc); } #elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH) struct spi_flash *ucode_flash; @@ -371,7 +371,7 @@ int fm_init_common(int index, struct ccsr_fman *reg) if (!ucode_flash) printf("SF: probe for ucode failed\n"); else { - ret = spi_flash_read(ucode_flash, CONFIG_SYS_QE_FMAN_FW_ADDR, + ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR, CONFIG_SYS_QE_FMAN_FW_LENGTH, addr); if (ret) printf("SF: read for ucode failed\n"); @@ -381,7 +381,7 @@ int fm_init_common(int index, struct ccsr_fman *reg) int dev = CONFIG_SYS_MMC_ENV_DEV; void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512; - u32 blk = CONFIG_SYS_QE_FMAN_FW_ADDR / 512; + u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512; struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); if (!mmc) @@ -395,7 +395,7 @@ int fm_init_common(int index, struct ccsr_fman *reg) flush_cache((ulong)addr, cnt * 512); } #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE) - void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR; + void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR; #else void *addr = NULL; #endif -- cgit v1.2.1 From 44afbbc0f0733381fefa159cc14931d7f711356e Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Wed, 26 Mar 2014 18:13:14 +0200 Subject: net/phy: Fix PHY id for VSC8514 In the current Datasheet for VSC8514 there is a mistake, saying that the PHY id is 0x70570. The real value in the identifier registers is 0x70670. Linux PHY driver uses 0x70670 also. Signed-off-by: Codrin Ciubotariu Cc: York Sun Reviewed-by: York Sun --- drivers/net/phy/vitesse.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/net') diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index c555979661..3a55d271a5 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -296,7 +296,7 @@ static struct phy_driver VSC8574_driver = { static struct phy_driver VSC8514_driver = { .name = "Vitesse VSC8514", - .uid = 0x70570, + .uid = 0x70670, .mask = 0xffff0, .features = PHY_GBIT_FEATURES, .config = &vsc8514_config, -- cgit v1.2.1 From 2ee6c52e229e1d0d1e78c3efbc67bc8bb868fb25 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Tue, 8 Apr 2014 10:55:49 +0530 Subject: driver/net/fm/memac_phy: Initialize mdio_clock for SoCs wih FMANv3 MDIO clock needs to be initialized in u-boot code for SoCs having FMAN-v3(v3H or v3L) controller due to below reasons -On SoCs that have FMAN-v3H like B4860, default value of MDIO_CLK_DIV bits in mdio_stat(mdio_cfg) register generates mdio clock too high (much higher than 2.5MHz), violating the IEEE specs. -On SOCs that have FMAN-v3L like T1040, default value of MDIO_CLK_DIV bits is zero, so MDIO clock is disabled. So, for proper functioninig of MDIO, MDIO_CLK_DIV bits needs to be properly initialized. Also this type of initialization is generally done in PBI(pre-bootloader) phase using rcw.But for chips like T1040 which support deep-sleep, such type of initialization cannot be done in PBI phase due to the limitation that during deep-sleep resume, FMAN (MDIO) registers are not accessible in PBI phase. So, mdio clock initailization must be done as part of u-boot. This initialization code is implemented in memac_phy.c which gets compiled only for SoCs having FMANv3, so no extra compilation flag is required. Signed-off-by: Priyanka Jain Reviewed-by: York Sun --- drivers/net/fm/memac_phy.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'drivers/net') diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index 140e59b75c..2f4bc11a6c 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -133,5 +133,17 @@ int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info) bus->priv = info->regs; + /* + * On some platforms like B4860, default value of MDIO_CLK_DIV bits + * in mdio_stat(mdio_cfg) register generates MDIO clock too high + * (much higher than 2.5MHz), violating the IEEE specs. + * On other platforms like T1040, default value of MDIO_CLK_DIV bits + * is zero, so MDIO clock is disabled. + * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to + * be properly initialized. + */ + setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat, + MDIO_STAT_CLKDIV(258)); + return mdio_register(bus); } -- cgit v1.2.1 From 08ad9b068afb8842df4cd559c327f54a42811a8d Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Mon, 21 Apr 2014 10:29:24 +0800 Subject: ar8031: modify the config func of ar8031 to ar8021_config ar8031 has the same config steps with ar8021, so change its config func to ar8021_config instead of genphy_config. Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- drivers/net/phy/atheros.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/net') diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index b80980d552..abd4e5b463 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -53,7 +53,7 @@ static struct phy_driver AR8031_driver = { .uid = 0x4dd074, .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, - .config = genphy_config, + .config = ar8021_config, .startup = genphy_startup, .shutdown = genphy_shutdown, }; -- cgit v1.2.1 From c1a9fa4ba67971f45ee106250340963cef7d020a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 25 Feb 2014 10:25:38 +0100 Subject: net: zynq: Use predefined macros instead of hardcoded value MII is used by this driver. Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/net') diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 101489c994..08056a4bac 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -338,7 +338,8 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) phy_detection(dev); /* interface - look at tsec */ - phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0); + phydev = phy_connect(priv->bus, priv->phyaddr, dev, + PHY_INTERFACE_MODE_MII); phydev->supported = supported | ADVERTISED_Pause | ADVERTISED_Asym_Pause; -- cgit v1.2.1 From 2fd2489b7aa36478433ae2a1f4de9f66e0a80322 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Apr 2014 14:17:38 +0200 Subject: net: zynq: Fix sparse warnings in gem Add missing header. Warnings: drivers/net/zynq_gem.c:491:5: warning: symbol 'zynq_gem_initialize' was not declared. Should it be static? drivers/net/zynq_gem.c:542:5: warning: symbol 'zynq_gem_of_init' was not declared. Should it be static? Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/net') diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 08056a4bac..3cadd23bb4 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include -- cgit v1.2.1