From 638a05894169b07ea8f6d21b6925ca353ea6ebb7 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 11 Oct 2015 21:37:44 -0700 Subject: x86: Enable mrc cache for bayleybay and minnowmax Now that we have added MRC cache for Intel FSP and BayTrail codes, enable it for all BayTrail boards (Bayley Bay and Minnow Max). Note it turns out that FSP for Intel Atom E6xx does not produce the HOB for NV storage, so we don't have such functionality on Intel Crown Bay board. Signed-off-by: Bin Meng Acked-by: Simon Glass --- doc/README.x86 | 1 + 1 file changed, 1 insertion(+) (limited to 'doc') diff --git a/doc/README.x86 b/doc/README.x86 index a9d0e0fbfe..1271e5edea 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -190,6 +190,7 @@ Offset Description Controlling config 000000 descriptor.bin Hard-coded to 0 in ifdtool 001000 me.bin Set by the descriptor 500000 +6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE 700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE 790000 vga.bin CONFIG_VGA_BIOS_ADDR 7c0000 fsp.bin CONFIG_FSP_ADDR -- cgit v1.2.1