From cf0bbbd1ee7b7c5e40db81c6b61d82e853dd50fb Mon Sep 17 00:00:00 2001 From: Meenakshi Aggarwal Date: Thu, 23 May 2019 15:13:43 +0530 Subject: drivers: net: mc: Report extra memory to Linux MC firmware need to be aligned to 512M, so minimum 512MB DDR is reserved. But MC support to work with 128MB or 256MB DDR memory also, in this case, rest of the memory is not usable. So reporting this extra memory to Linux through dtb memory fixup. Signed-off-by: Meenakshi Aggarwal Reviewed-by: Prabhakar Kushwaha --- board/freescale/ls1088a/ls1088a.c | 31 ++++++++++++++++++++++++++++--- board/freescale/ls2080ardb/ls2080ardb.c | 32 +++++++++++++++++++++++++++++--- board/freescale/lx2160a/lx2160a.c | 31 ++++++++++++++++++++++++++++--- 3 files changed, 85 insertions(+), 9 deletions(-) (limited to 'board') diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index f0bea7327d..690adc4c77 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -739,11 +739,26 @@ void fsl_fdt_fixup_flash(void *fdt) int ft_board_setup(void *blob, bd_t *bd) { int i; - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; + u16 mc_memory_bank = 0; + + u64 *base; + u64 *size; + u64 mc_memory_base = 0; + u64 mc_memory_size = 0; + u16 total_memory_banks; ft_cpu_setup(blob, bd); + fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); + + if (mc_memory_base != 0) + mc_memory_bank++; + + total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; + + base = calloc(total_memory_banks, sizeof(u64)); + size = calloc(total_memory_banks, sizeof(u64)); + /* fixup DT for the two GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { base[i] = gd->bd->bi_dram[i].start; @@ -760,7 +775,17 @@ int ft_board_setup(void *blob, bd_t *bd) size[1] = gd->arch.resv_ram - base[1]; #endif - fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); + if (mc_memory_base != 0) { + for (i = 0; i <= total_memory_banks; i++) { + if (base[i] == 0 && size[i] == 0) { + base[i] = mc_memory_base; + size[i] = mc_memory_size; + break; + } + } + } + + fdt_fixup_memory_banks(blob, base, size, total_memory_banks); fdt_fsl_mc_fixup_iommu_map_entry(blob); diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 2b2dbbb0ce..e000b1fd51 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -410,11 +410,27 @@ void fsl_fdt_fixup_flash(void *fdt) int ft_board_setup(void *blob, bd_t *bd) { - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; + int i; + u16 mc_memory_bank = 0; + + u64 *base; + u64 *size; + u64 mc_memory_base = 0; + u64 mc_memory_size = 0; + u16 total_memory_banks; ft_cpu_setup(blob, bd); + fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); + + if (mc_memory_base != 0) + mc_memory_bank++; + + total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; + + base = calloc(total_memory_banks, sizeof(u64)); + size = calloc(total_memory_banks, sizeof(u64)); + /* fixup DT for the two GPP DDR banks */ base[0] = gd->bd->bi_dram[0].start; size[0] = gd->bd->bi_dram[0].size; @@ -431,7 +447,17 @@ int ft_board_setup(void *blob, bd_t *bd) size[1] = gd->arch.resv_ram - base[1]; #endif - fdt_fixup_memory_banks(blob, base, size, 2); + if (mc_memory_base != 0) { + for (i = 0; i <= total_memory_banks; i++) { + if (base[i] == 0 && size[i] == 0) { + base[i] = mc_memory_base; + size[i] = mc_memory_size; + break; + } + } + } + + fdt_fixup_memory_banks(blob, base, size, total_memory_banks); fdt_fsl_mc_fixup_iommu_map_entry(blob); diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index f3885fa8b7..3dfbfebedc 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -529,11 +529,26 @@ void board_quiesce_devices(void) int ft_board_setup(void *blob, bd_t *bd) { int i; - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; + u16 mc_memory_bank = 0; + + u64 *base; + u64 *size; + u64 mc_memory_base = 0; + u64 mc_memory_size = 0; + u16 total_memory_banks; ft_cpu_setup(blob, bd); + fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); + + if (mc_memory_base != 0) + mc_memory_bank++; + + total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; + + base = calloc(total_memory_banks, sizeof(u64)); + size = calloc(total_memory_banks, sizeof(u64)); + /* fixup DT for the three GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { base[i] = gd->bd->bi_dram[i].start; @@ -553,7 +568,17 @@ int ft_board_setup(void *blob, bd_t *bd) size[2] = gd->arch.resv_ram - base[2]; #endif - fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); + if (mc_memory_base != 0) { + for (i = 0; i <= total_memory_banks; i++) { + if (base[i] == 0 && size[i] == 0) { + base[i] = mc_memory_base; + size[i] = mc_memory_size; + break; + } + } + } + + fdt_fixup_memory_banks(blob, base, size, total_memory_banks); #ifdef CONFIG_USB fsl_fdt_fixup_dr_usb(blob, bd); -- cgit v1.2.1 From 0f6607f9e9d4638f5d7759c95f4c513e57e3b3dc Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Wed, 19 Jun 2019 14:39:28 +0800 Subject: common: qixis: make the qixis compatible with new soc This driver needs modification to work with new soc, like ls1028, since bitmap of RCFG is changed to RESV[7:5] LIVE[4] WDEN[3] RESV[2:1] GO[0] 000 1 0 00 0 Also the RCW location is moved to only dutcfg0. RESV[7:4] RCWSRC[3:0] 1111 configurable Following commands are functional now qixis_reset qixis_reset sd qixis_reset qspi qixis_reset emmc Signed-off-by: Ashish Kumar Signed-off-by: Yuantian Tang Reviewed-by: Prabhakar Kushwaha --- board/freescale/common/qixis.c | 45 +++++++++++++++++++++++++++++++----------- 1 file changed, 33 insertions(+), 12 deletions(-) (limited to 'board') diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index f1b98bcd2a..1f20223df4 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -21,6 +21,13 @@ #define QIXIS_LBMAP_BRDCFG_REG 0x00 #endif +#ifndef QIXIS_RCFG_CTL_RECONFIG_IDLE +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#endif +#ifndef QIXIS_RCFG_CTL_RECONFIG_START +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#endif + #ifdef CONFIG_SYS_I2C_FPGA_ADDR u8 qixis_read_i2c(unsigned int reg) { @@ -142,11 +149,13 @@ static void qixis_reset(void) QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET); } +#ifdef QIXIS_LBMAP_ALTBANK static void qixis_bank_reset(void) { QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); } +#endif static void __maybe_unused set_lbmap(int lbmap) { @@ -159,12 +168,16 @@ static void __maybe_unused set_lbmap(int lbmap) static void __maybe_unused set_rcw_src(int rcw_src) { +#ifdef CONFIG_NXP_LSCH3_2 + QIXIS_WRITE(dutcfg[0], (rcw_src & 0xff)); +#else u8 reg; reg = QIXIS_READ(dutcfg[1]); reg = (reg & ~1) | (rcw_src & 1); QIXIS_WRITE(dutcfg[1], reg); QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff); +#endif } static void qixis_dump_regs(void) @@ -210,16 +223,20 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar set_lbmap(QIXIS_LBMAP_DFLTBANK); qixis_reset(); } else if (strcmp(argv[1], "altbank") == 0) { +#ifdef QIXIS_LBMAP_ALTBANK set_lbmap(QIXIS_LBMAP_ALTBANK); qixis_bank_reset(); +#else + printf("No Altbank!\n"); +#endif } else if (strcmp(argv[1], "nand") == 0) { #ifdef QIXIS_LBMAP_NAND QIXIS_WRITE(rst_ctl, 0x30); QIXIS_WRITE(rcfg_ctl, 0); set_lbmap(QIXIS_LBMAP_NAND); set_rcw_src(QIXIS_RCW_SRC_NAND); - QIXIS_WRITE(rcfg_ctl, 0x20); - QIXIS_WRITE(rcfg_ctl, 0x21); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); #else printf("Not implemented\n"); #endif @@ -233,8 +250,8 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar set_lbmap(QIXIS_LBMAP_SD); set_rcw_src(QIXIS_RCW_SRC_SD); #endif - QIXIS_WRITE(rcfg_ctl, 0x20); - QIXIS_WRITE(rcfg_ctl, 0x21); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); #else printf("Not implemented\n"); #endif @@ -244,8 +261,8 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar QIXIS_WRITE(rcfg_ctl, 0); set_lbmap(QIXIS_LBMAP_IFC); set_rcw_src(QIXIS_RCW_SRC_IFC); - QIXIS_WRITE(rcfg_ctl, 0x20); - QIXIS_WRITE(rcfg_ctl, 0x21); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); #else printf("Not implemented\n"); #endif @@ -255,8 +272,8 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar QIXIS_WRITE(rcfg_ctl, 0); set_lbmap(QIXIS_LBMAP_EMMC); set_rcw_src(QIXIS_RCW_SRC_EMMC); - QIXIS_WRITE(rcfg_ctl, 0x20); - QIXIS_WRITE(rcfg_ctl, 0x21); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); #else printf("Not implemented\n"); #endif @@ -266,8 +283,10 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar QIXIS_WRITE(rcfg_ctl, 0); set_lbmap(QIXIS_LBMAP_SD_QSPI); set_rcw_src(QIXIS_RCW_SRC_SD); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_IDLE); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_START); #else printf("Not implemented\n"); #endif @@ -277,8 +296,10 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar QIXIS_WRITE(rcfg_ctl, 0); set_lbmap(QIXIS_LBMAP_QSPI); set_rcw_src(QIXIS_RCW_SRC_QSPI); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_IDLE); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_START); #else printf("Not implemented\n"); #endif -- cgit v1.2.1 From 0eba65d2013e5517e70cc9b3d467ba8183b54cd9 Mon Sep 17 00:00:00 2001 From: Chuanhua Han Date: Wed, 10 Jul 2019 21:00:20 +0800 Subject: boards: lx2160a: Add support of I2C driver model DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C API when DM_I2C is used. When DM_I2C_COMPAT is not enabled for compilation, a compilation error will be generated. This patch solves the problem that the i2c-related api of the lx2160a platform does not support dm. Signed-off-by: Chuanhua Han Reviewed-by: Prabhakar Kushwaha --- board/freescale/common/emc2305.c | 21 ++++++++++ board/freescale/common/qixis.c | 17 ++++++++ board/freescale/common/sys_eeprom.c | 84 +++++++++++++++++++++++++++++++++++-- board/freescale/common/vid.c | 84 +++++++++++++++++++++++++++++++++++++ board/freescale/lx2160a/lx2160a.c | 8 ++++ 5 files changed, 210 insertions(+), 4 deletions(-) (limited to 'board') diff --git a/board/freescale/common/emc2305.c b/board/freescale/common/emc2305.c index 8523084da9..b1ca051db2 100644 --- a/board/freescale/common/emc2305.c +++ b/board/freescale/common/emc2305.c @@ -24,10 +24,22 @@ void set_fan_speed(u8 data) I2C_EMC2305_FAN5}; for (index = 0; index < NUM_OF_FANS; index++) { +#ifndef CONFIG_DM_I2C if (i2c_write(I2C_EMC2305_ADDR, Fan[index], 1, &data, 1) != 0) { printf("Error: failed to change fan speed @%x\n", Fan[index]); } +#else + struct udevice *dev; + + if (i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, &dev)) + continue; + + if (dm_i2c_write(dev, Fan[index], &data, 1) != 0) { + printf("Error: failed to change fan speed @%x\n", + Fan[index]); + } +#endif } } @@ -36,6 +48,15 @@ void emc2305_init(void) u8 data; data = I2C_EMC2305_CMD; +#ifndef CONFIG_DM_I2C if (i2c_write(I2C_EMC2305_ADDR, I2C_EMC2305_CONF, 1, &data, 1) != 0) printf("Error: failed to configure EMC2305\n"); +#else + struct udevice *dev; + + if (!i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, &dev)) + if (dm_i2c_write(dev, I2C_EMC2305_CONF, &data, 1)) + printf("Error: failed to configure EMC2305\n"); +#endif + } diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 1f20223df4..716c93b2c2 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -31,13 +31,30 @@ #ifdef CONFIG_SYS_I2C_FPGA_ADDR u8 qixis_read_i2c(unsigned int reg) { +#ifndef CONFIG_DM_I2C return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg); +#else + struct udevice *dev; + + if (i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev)) + return 0xff; + + return dm_i2c_reg_read(dev, reg); +#endif } void qixis_write_i2c(unsigned int reg, u8 value) { u8 val = value; +#ifndef CONFIG_DM_I2C i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val); +#else + struct udevice *dev; + + if (!i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev)) + dm_i2c_reg_write(dev, reg, val); +#endif + } #endif diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 510d7c266b..bb655ca744 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -149,23 +149,42 @@ static int read_eeprom(void) { int ret; #ifdef CONFIG_SYS_EEPROM_BUS_NUM +#ifndef CONFIG_DM_I2C unsigned int bus; +#endif #endif if (has_been_read) return 0; #ifdef CONFIG_SYS_EEPROM_BUS_NUM +#ifndef CONFIG_DM_I2C bus = i2c_get_bus_num(); i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); #endif +#endif - ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - (void *)&e, sizeof(e)); +#ifndef CONFIG_DM_I2C + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + (void *)&e, sizeof(e)); +#else + struct udevice *dev; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev); +#else + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev); +#endif + if (!ret) + ret = dm_i2c_read(dev, 0, (void *)&e, sizeof(e)); +#endif #ifdef CONFIG_SYS_EEPROM_BUS_NUM +#ifndef CONFIG_DM_I2C i2c_set_bus_num(bus); #endif +#endif #ifdef DEBUG show_eeprom(); @@ -199,7 +218,9 @@ static int prog_eeprom(void) int i; void *p; #ifdef CONFIG_SYS_EEPROM_BUS_NUM +#ifndef CONFIG_DM_I2C unsigned int bus; +#endif #endif /* Set the reserved values to 0xFF */ @@ -211,9 +232,11 @@ static int prog_eeprom(void) #endif update_crc(); +#ifndef CONFIG_DM_I2C #ifdef CONFIG_SYS_EEPROM_BUS_NUM bus = i2c_get_bus_num(); i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); +#endif #endif /* @@ -222,8 +245,26 @@ static int prog_eeprom(void) * complete a given write. */ for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) { - ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, +#ifndef CONFIG_DM_I2C + ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, p, min((int)(sizeof(e) - i), 8)); +#else + struct udevice *dev; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#else + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#endif + if (!ret) + ret = dm_i2c_write(dev, i, p, min((int)(sizeof(e) - i), + 8)); +#endif if (ret) break; udelay(5000); /* 5ms write cycle timing */ @@ -233,14 +274,33 @@ static int prog_eeprom(void) /* Verify the write by reading back the EEPROM and comparing */ struct eeprom e2; +#ifndef CONFIG_DM_I2C ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&e2, sizeof(e2)); + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + (void *)&e2, sizeof(e2)); +#else + struct udevice *dev; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#else + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#endif + if (!ret) + ret = dm_i2c_read(dev, 0, (void *)&e2, sizeof(e2)); +#endif if (!ret && memcmp(&e, &e2, sizeof(e))) ret = -1; } +#ifndef CONFIG_DM_I2C #ifdef CONFIG_SYS_EEPROM_BUS_NUM i2c_set_bus_num(bus); +#endif #endif if (ret) { @@ -529,8 +589,24 @@ unsigned int get_cpu_board_revision(void) u8 minor; /* 0x05 Board revision, minor */ } be; +#ifndef CONFIG_DM_I2C i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&be, sizeof(be)); +#else + struct udevice *dev; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#else + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev) +#endif + if (!ret) + dm_i2c_read(dev, 0, (void *)&be, sizeof(be)); +#endif if (be.id != (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D')) return MPC85XX_CPU_BOARD_REV(0, 0); diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index b804971981..b37f3bf4f8 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -61,13 +61,23 @@ static int find_ir_chip_on_i2c(void) u8 byte; int i; const int ir_i2c_addr[] = {0x38, 0x08, 0x09}; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif /* Check all the address */ for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) { i2caddress = ir_i2c_addr[i]; +#ifndef CONFIG_DM_I2C ret = i2c_read(i2caddress, IR36021_MFR_ID_OFFSET, 1, (void *)&byte, sizeof(byte)); +#else + ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, IR36021_MFR_ID_OFFSET, + (void *)&byte, sizeof(byte)); +#endif if ((ret >= 0) && (byte == IR36021_MFR_ID)) return i2caddress; } @@ -103,11 +113,21 @@ static int read_voltage_from_INA220(int i2caddress) int i, ret, voltage_read = 0; u16 vol_mon; u8 buf[2]; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif for (i = 0; i < NUM_READINGS; i++) { +#ifndef CONFIG_DM_I2C ret = i2c_read(I2C_VOL_MONITOR_ADDR, I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&buf, 2); +#else + ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, I2C_VOL_MONITOR_BUS_V_OFFSET, + (void *)&buf, 2); +#endif if (ret) { printf("VID: failed to read core voltage\n"); return ret; @@ -136,11 +156,21 @@ static int read_voltage_from_IR(int i2caddress) int i, ret, voltage_read = 0; u16 vol_mon; u8 buf; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif for (i = 0; i < NUM_READINGS; i++) { +#ifndef CONFIG_DM_I2C ret = i2c_read(i2caddress, IR36021_LOOP1_VOUT_OFFSET, 1, (void *)&buf, 1); +#else + ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, IR36021_LOOP1_VOUT_OFFSET, + (void *)&buf, 1); +#endif if (ret) { printf("VID: failed to read vcpu\n"); return ret; @@ -179,17 +209,33 @@ static int read_voltage_from_LTC(int i2caddress) int ret, vcode = 0; u8 chan = PWM_CHANNEL0; +#ifndef CONFIG_DM_I2C /* select the PAGE 0 using PMBus commands PAGE for VDD*/ ret = i2c_write(I2C_VOL_MONITOR_ADDR, PMBUS_CMD_PAGE, 1, &chan, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, &chan, 1); +#endif if (ret) { printf("VID: failed to select VDD Page 0\n"); return ret; } +#ifndef CONFIG_DM_I2C /*read the output voltage using PMBus command READ_VOUT*/ ret = i2c_read(I2C_VOL_MONITOR_ADDR, PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); +#else + ret = dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2); + if (ret) { + printf("VID: failed to read the volatge\n"); + return ret; + } +#endif if (ret) { printf("VID: failed to read the volatge\n"); return ret; @@ -294,8 +340,18 @@ static int set_voltage_to_IR(int i2caddress, int vdd) vid = DIV_ROUND_UP(vdd - 245, 5); #endif +#ifndef CONFIG_DM_I2C ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET, 1, (void *)&vid, sizeof(vid)); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, IR36021_LOOP1_MANUAL_ID_OFFSET, + (void *)&vid, sizeof(vid)); + +#endif if (ret) { printf("VID: failed to write VID\n"); return -1; @@ -331,8 +387,17 @@ static int set_voltage_to_LTC(int i2caddress, int vdd) vdd & 0xFF, (vdd & 0xFF00) >> 8}; /* Write the desired voltage code to the regulator */ +#ifndef CONFIG_DM_I2C ret = i2c_write(I2C_VOL_MONITOR_ADDR, PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE, + (void *)&buff, 5); +#endif if (ret) { printf("VID: I2C failed to write to the volatge regulator\n"); return -1; @@ -516,14 +581,24 @@ int adjust_vdd(ulong vdd_override) } /* check IR chip work on Intel mode*/ +#ifndef CONFIG_DM_I2C ret = i2c_read(i2caddress, IR36021_INTEL_MODE_OOFSET, 1, (void *)&buf, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET, + (void *)&buf, 1); +#endif if (ret) { printf("VID: failed to read IR chip mode.\n"); ret = -1; goto exit; } + if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) { printf("VID: IR Chip is not used in Intel mode.\n"); ret = -1; @@ -688,9 +763,18 @@ int adjust_vdd(ulong vdd_override) } /* check IR chip work on Intel mode*/ +#ifndef CONFIG_DM_I2C ret = i2c_read(i2caddress, IR36021_INTEL_MODE_OOFSET, 1, (void *)&buf, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET, + (void *)&buf, 1); +#endif if (ret) { printf("VID: failed to read IR chip mode.\n"); ret = -1; diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 3dfbfebedc..163b42dda4 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -74,7 +74,15 @@ int select_i2c_ch_pca9547(u8 ch) { int ret; +#ifndef CONFIG_DM_I2C ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, 0, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; -- cgit v1.2.1 From 954cd7882857c64158de8d90660f490b0b136b7a Mon Sep 17 00:00:00 2001 From: Chuanhua Han Date: Wed, 10 Jul 2019 21:16:49 +0800 Subject: boards: ls1028a: Add support of I2C driver model DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C API when DM_I2C is used.When DM_I2C_COMPAT is not enabled for compilation, a compilation error will be generated. This patch solves the problem that the i2c-related api of the ls1028a platform does not support dm. Signed-off-by: Chuanhua Han Reviewed-by: Alex Marginean Reviewed-by: Prabhakar Kushwaha --- board/freescale/ls1028a/ls1028a.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'board') diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c index 4aa7cec9ce..1410d0f920 100644 --- a/board/freescale/ls1028a/ls1028a.c +++ b/board/freescale/ls1028a/ls1028a.c @@ -73,7 +73,15 @@ int board_init(void) #if defined(CONFIG_TARGET_LS1028ARDB) u8 val = I2C_MUX_CH_DEFAULT; +#ifndef CONFIG_DM_I2C i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1); +#else + struct udevice *dev; + + if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev)) + dm_i2c_write(dev, 0x0b, &val, 1); +#endif + #endif return 0; } -- cgit v1.2.1 From 654e4e70d4ab0219f68ed6a540faa07a9f476866 Mon Sep 17 00:00:00 2001 From: Chuanhua Han Date: Mon, 22 Jul 2019 16:36:42 +0800 Subject: boards: ls2088a: Add support of I2C driver model. DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C API when DM_I2C is used.When DM_I2C_COMPAT is not enabled for compilation, a compilation error will be generated. This patch solves the problem that the i2c-related api of the ls2088a platform does not support dm. Signed-off-by: Chuanhua Han Reviewed-by: Prabhakar Kushwaha --- board/freescale/ls2080ardb/ls2080ardb.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'board') diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index e000b1fd51..e20267f27c 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -164,7 +164,16 @@ int select_i2c_ch_pca9547(u8 ch) { int ret; +#ifndef CONFIG_DM_I2C ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, 0, &ch, 1); +#endif + if (ret) { puts("PCA: failed to select proper channel\n"); return ret; -- cgit v1.2.1 From db07c447caacd5f9003a57ef2802afa8a4c81348 Mon Sep 17 00:00:00 2001 From: Chuanhua Han Date: Fri, 26 Jul 2019 19:24:00 +0800 Subject: rtc: ds3232/ds3231: Add support to generate 32KHz output for driver module Add an implementation of the rtc_enable_32khz_output() that uses the driver model i2c APIs. Also put code related to rtc_enable_32khz_output under CONFIG_RTC_ENABLE_32KHZ_OUTPUT. Signed-off-by: Chuanhua Han Reviewed-by: Prabhakar Kushwaha --- board/freescale/ls2080aqds/ls2080aqds.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'board') diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index e9c055745f..dc239cf35c 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -225,7 +225,9 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); +#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT rtc_enable_32khz_output(); +#endif #ifdef CONFIG_FSL_CAAM sec_init(); #endif -- cgit v1.2.1 From 885ae0513a3cfc2e1fbd4452cd2e2c466423049a Mon Sep 17 00:00:00 2001 From: Chuanhua Han Date: Fri, 26 Jul 2019 19:24:01 +0800 Subject: boards: ls2088aqds: Add support of I2C driver model. Update ls2088aqds board init code to support DM_I2C. Signed-off-by: Chuanhua Han Reviewed-by: Prabhakar Kushwaha --- board/freescale/ls2080aqds/eth.c | 151 ++++++++++++++++++++++---------- board/freescale/ls2080aqds/ls2080aqds.c | 14 +++ 2 files changed, 118 insertions(+), 47 deletions(-) (limited to 'board') diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 1b4e6c65fb..6a8788c312 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -90,11 +90,16 @@ struct ls2080a_qds_mdio { struct mii_dev *realbus; }; +struct reg_pair { + uint addr; + u8 *val; +}; + static void sgmii_configure_repeater(int serdes_port) { struct mii_dev *bus; uint8_t a = 0xf; - int i, j, ret; + int i, j, k, ret; int dpmac_id = 0, dpmac, mii_bus = 0; unsigned short value; char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"}; @@ -105,10 +110,30 @@ static void sgmii_configure_repeater(int serdes_port) uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20}; + struct reg_pair reg_pair[10] = { + {6, ®_val[0]}, {4, ®_val[1]}, + {8, ®_val[2]}, {0xf, NULL}, + {0x11, NULL}, {0x16, NULL}, + {0x18, NULL}, {0x23, ®_val[3]}, + {0x2d, ®_val[4]}, {4, ®_val[5]}, + }; + int *riser_phy_addr = &xqsgii_riser_phy_addr[0]; +#ifdef CONFIG_DM_I2C + struct udevice *udev; +#endif /* Set I2c to Slot 1 */ - i2c_write(0x77, 0, 0, &a, 1); +#ifndef CONFIG_DM_I2C + ret = i2c_write(0x77, 0, 0, &a, 1); +#else + ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, 0, &a, 1); +#endif + if (ret) + goto error; for (dpmac = 0; dpmac < 8; dpmac++) { /* Check the PHY status */ @@ -121,7 +146,15 @@ static void sgmii_configure_repeater(int serdes_port) mii_bus = 1; dpmac_id = dpmac + 9; a = 0xb; - i2c_write(0x76, 0, 0, &a, 1); +#ifndef CONFIG_DM_I2C + ret = i2c_write(0x76, 0, 0, &a, 1); +#else + ret = i2c_get_chip_for_busnum(0, 0x76, 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, 0, &a, 1); +#endif + if (ret) + goto error; break; } @@ -154,29 +187,29 @@ static void sgmii_configure_repeater(int serdes_port) for (i = 0; i < 4; i++) { for (j = 0; j < 4; j++) { - a = 0x18; - i2c_write(i2c_addr[dpmac], 6, 1, &a, 1); - a = 0x38; - i2c_write(i2c_addr[dpmac], 4, 1, &a, 1); - a = 0x4; - i2c_write(i2c_addr[dpmac], 8, 1, &a, 1); - - i2c_write(i2c_addr[dpmac], 0xf, 1, - &ch_a_eq[i], 1); - i2c_write(i2c_addr[dpmac], 0x11, 1, - &ch_a_ctl2[j], 1); - - i2c_write(i2c_addr[dpmac], 0x16, 1, - &ch_b_eq[i], 1); - i2c_write(i2c_addr[dpmac], 0x18, 1, - &ch_b_ctl2[j], 1); - - a = 0x14; - i2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1); - a = 0xb5; - i2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1); - a = 0x20; - i2c_write(i2c_addr[dpmac], 4, 1, &a, 1); + reg_pair[3].val = &ch_a_eq[i]; + reg_pair[4].val = &ch_a_ctl2[j]; + reg_pair[5].val = &ch_b_eq[i]; + reg_pair[6].val = &ch_b_ctl2[j]; + + for (k = 0; k < 10; k++) { +#ifndef CONFIG_DM_I2C + ret = i2c_write(i2c_addr[dpmac], + reg_pair[k].addr, + 1, reg_pair[k].val, 1); +#else + ret = i2c_get_chip_for_busnum(0, + i2c_addr[dpmac], + 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, + reg_pair[k].addr, + reg_pair[k].val, 1); +#endif + if (ret) + goto error; + } + mdelay(100); ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], @@ -217,7 +250,7 @@ error: static void qsgmii_configure_repeater(int dpmac) { uint8_t a = 0xf; - int i, j; + int i, j, k; int i2c_phy_addr = 0; int phy_addr = 0; int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b}; @@ -227,12 +260,32 @@ static void qsgmii_configure_repeater(int dpmac) uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20}; + struct reg_pair reg_pair[10] = { + {6, ®_val[0]}, {4, ®_val[1]}, + {8, ®_val[2]}, {0xf, NULL}, + {0x11, NULL}, {0x16, NULL}, + {0x18, NULL}, {0x23, ®_val[3]}, + {0x2d, ®_val[4]}, {4, ®_val[5]}, + }; + const char *dev = "LS2080A_QDS_MDIO0"; int ret = 0; unsigned short value; +#ifdef CONFIG_DM_I2C + struct udevice *udev; +#endif /* Set I2c to Slot 1 */ - i2c_write(0x77, 0, 0, &a, 1); +#ifndef CONFIG_DM_I2C + ret = i2c_write(0x77, 0, 0, &a, 1); +#else + ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, 0, &a, 1); +#endif + if (ret) + goto error; switch (dpmac) { case 1: @@ -283,25 +336,29 @@ static void qsgmii_configure_repeater(int dpmac) for (i = 0; i < 4; i++) { for (j = 0; j < 4; j++) { - a = 0x18; - i2c_write(i2c_phy_addr, 6, 1, &a, 1); - a = 0x38; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); - a = 0x4; - i2c_write(i2c_phy_addr, 8, 1, &a, 1); - - i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1); - i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1); - - i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1); - i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1); - - a = 0x14; - i2c_write(i2c_phy_addr, 0x23, 1, &a, 1); - a = 0xb5; - i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1); - a = 0x20; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); + reg_pair[3].val = &ch_a_eq[i]; + reg_pair[4].val = &ch_a_ctl2[j]; + reg_pair[5].val = &ch_b_eq[i]; + reg_pair[6].val = &ch_b_ctl2[j]; + + for (k = 0; k < 10; k++) { +#ifndef CONFIG_DM_I2C + ret = i2c_write(i2c_phy_addr, + reg_pair[k].addr, + 1, reg_pair[k].val, 1); +#else + ret = i2c_get_chip_for_busnum(0, + i2c_phy_addr, + 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, + reg_pair[k].addr, + reg_pair[k].val, 1); +#endif + if (ret) + goto error; + } + mdelay(100); ret = miiphy_read(dev, phy_addr, 0x11, &value); if (ret > 0) diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index dc239cf35c..91c80353ed 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -161,8 +161,16 @@ unsigned long get_board_ddr_clk(void) int select_i2c_ch_pca9547(u8 ch) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, 0, &ch, 1); + +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -225,9 +233,15 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + #ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT +#ifdef CONFIG_DM_I2C + rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR); +#else rtc_enable_32khz_output(); #endif +#endif + #ifdef CONFIG_FSL_CAAM sec_init(); #endif -- cgit v1.2.1 From 5dd043a082b19c77c6177e867009a51a41e8707e Mon Sep 17 00:00:00 2001 From: Chuanhua Han Date: Tue, 23 Jul 2019 18:43:11 +0800 Subject: boards: ls1088a: Add support of I2C driver model DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C API when DM_I2C is used.When DM_I2C_COMPAT is not enabled for compilation, a compilation error will be generated. This patch solves the problem that the i2c-related api of the ls1088a platform does not support dm. Signed-off-by: Chuanhua Han Reviewed-by: Prabhakar Kushwaha --- board/freescale/ls1088a/ls1088a.c | 148 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 148 insertions(+) (limited to 'board') diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 690adc4c77..1033d44409 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -374,7 +374,15 @@ int select_i2c_ch_pca9547(u8 ch) { int ret; +#ifndef CONFIG_DM_I2C ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, 0, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -393,38 +401,89 @@ void board_retimer_init(void) /* Access to Control/Shared register */ reg = 0x0; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); +#else + struct udevice *dev; + + i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev); + dm_i2c_write(dev, 0xff, ®, 1); +#endif /* Read device revision and ID */ +#ifndef CONFIG_DM_I2C i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); +#else + dm_i2c_read(dev, 1, ®, 1); +#endif debug("Retimer version id = 0x%x\n", reg); /* Enable Broadcast. All writes target all channel register sets */ reg = 0x0c; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); +#else + dm_i2c_write(dev, 0xff, ®, 1); +#endif /* Reset Channel Registers */ +#ifndef CONFIG_DM_I2C i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); +#else + dm_i2c_read(dev, 0, ®, 1); +#endif reg |= 0x4; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); +#else + dm_i2c_write(dev, 0, ®, 1); +#endif /* Set data rate as 10.3125 Gbps */ reg = 0x90; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); +#else + dm_i2c_write(dev, 0x60, ®, 1); +#endif reg = 0xb3; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); +#else + dm_i2c_write(dev, 0x61, ®, 1); +#endif reg = 0x90; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); +#else + dm_i2c_write(dev, 0x62, ®, 1); +#endif reg = 0xb3; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); +#else + dm_i2c_write(dev, 0x63, ®, 1); +#endif reg = 0xcd; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); +#else + dm_i2c_write(dev, 0x64, ®, 1); +#endif /* Select VCO Divider to full rate (000) */ +#ifndef CONFIG_DM_I2C i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); +#else + dm_i2c_read(dev, 0x2F, ®, 1); +#endif reg &= 0x0f; reg |= 0x70; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); +#else + dm_i2c_write(dev, 0x2F, ®, 1); +#endif #ifdef CONFIG_TARGET_LS1088AQDS /* Retimer is connected to I2C1_CH5 */ @@ -432,38 +491,88 @@ void board_retimer_init(void) /* Access to Control/Shared register */ reg = 0x0; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); +#else + i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev); + dm_i2c_write(dev, 0xff, ®, 1); +#endif /* Read device revision and ID */ +#ifndef CONFIG_DM_I2C i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1); +#else + dm_i2c_read(dev, 1, ®, 1); +#endif debug("Retimer version id = 0x%x\n", reg); /* Enable Broadcast. All writes target all channel register sets */ reg = 0x0c; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); +#else + dm_i2c_write(dev, 0xff, ®, 1); +#endif /* Reset Channel Registers */ +#ifndef CONFIG_DM_I2C i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1); +#else + dm_i2c_read(dev, 0, ®, 1); +#endif reg |= 0x4; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1); +#else + dm_i2c_write(dev, 0, ®, 1); +#endif /* Set data rate as 10.3125 Gbps */ reg = 0x90; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1); +#else + dm_i2c_write(dev, 0x60, ®, 1); +#endif reg = 0xb3; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1); +#else + dm_i2c_write(dev, 0x61, ®, 1); +#endif reg = 0x90; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1); +#else + dm_i2c_write(dev, 0x62, ®, 1); +#endif reg = 0xb3; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1); +#else + dm_i2c_write(dev, 0x63, ®, 1); +#endif reg = 0xcd; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1); +#else + dm_i2c_write(dev, 0x64, ®, 1); +#endif /* Select VCO Divider to full rate (000) */ +#ifndef CONFIG_DM_I2C i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); +#else + dm_i2c_read(dev, 0x2F, ®, 1); +#endif reg &= 0x0f; reg |= 0x70; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); +#else + dm_i2c_write(dev, 0x2F, ®, 1); +#endif + #endif /*return the default channel*/ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); @@ -500,16 +609,30 @@ int get_serdes_volt(void) u8 chan = PWM_CHANNEL0; /* Select the PAGE 0 using PMBus commands PAGE for VDD */ +#ifndef CONFIG_DM_I2C ret = i2c_write(I2C_SVDD_MONITOR_ADDR, PMBUS_CMD_PAGE, 1, &chan, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, + &chan, 1); +#endif + if (ret) { printf("VID: failed to select VDD Page 0\n"); return ret; } /* Read the output voltage using PMBus command READ_VOUT */ +#ifndef CONFIG_DM_I2C ret = i2c_read(I2C_SVDD_MONITOR_ADDR, PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); +#else + dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2); +#endif if (ret) { printf("VID: failed to read the volatge\n"); return ret; @@ -525,8 +648,17 @@ int set_serdes_volt(int svdd) svdd & 0xFF, (svdd & 0xFF00) >> 8}; /* Write the desired voltage code to the SVDD regulator */ +#ifndef CONFIG_DM_I2C ret = i2c_write(I2C_SVDD_MONITOR_ADDR, PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE, + (void *)&buff, 5); +#endif if (ret) { printf("VID: I2C failed to write to the volatge regulator\n"); return -1; @@ -557,8 +689,18 @@ int set_serdes_volt(int svdd) printf("SVDD changing of RDB\n"); /* Read the BRDCFG54 via CLPD */ +#ifndef CONFIG_DM_I2C ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR, QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET, + (void *)&brdcfg4, 1); +#endif + if (ret) { printf("VID: I2C failed to read the CPLD BRDCFG4\n"); return -1; @@ -567,8 +709,14 @@ int set_serdes_volt(int svdd) brdcfg4 = brdcfg4 | 0x08; /* Write to the BRDCFG4 */ +#ifndef CONFIG_DM_I2C ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); +#else + ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET, + (void *)&brdcfg4, 1); +#endif + if (ret) { debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n"); return -1; -- cgit v1.2.1 From c8b2e364b662c76b04da2eb4a3516bf333f55279 Mon Sep 17 00:00:00 2001 From: Chuanhua Han Date: Fri, 26 Jul 2019 20:25:35 +0800 Subject: armv8: ls1088aqds: Add support of I2C driver model. Udate ls1088aqds board init code to support DM_I2C. Signed-off-by: Chuanhua Han Reviewed-by: Prabhakar Kushwaha --- board/freescale/ls1088a/eth_ls1088aqds.c | 149 +++++++++++++++++++++---------- 1 file changed, 102 insertions(+), 47 deletions(-) (limited to 'board') diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c index d4ab9791e9..237088a537 100644 --- a/board/freescale/ls1088a/eth_ls1088aqds.c +++ b/board/freescale/ls1088a/eth_ls1088aqds.c @@ -81,11 +81,16 @@ struct ls1088a_qds_mdio { struct mii_dev *realbus; }; +struct reg_pair { + uint addr; + u8 *val; +}; + static void sgmii_configure_repeater(int dpmac) { struct mii_dev *bus; uint8_t a = 0xf; - int i, j, ret; + int i, j, k, ret; unsigned short value; const char *dev = "LS1088A_QDS_MDIO2"; int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b}; @@ -97,8 +102,28 @@ static void sgmii_configure_repeater(int dpmac) uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20}; + struct reg_pair reg_pair[10] = { + {6, ®_val[0]}, {4, ®_val[1]}, + {8, ®_val[2]}, {0xf, NULL}, + {0x11, NULL}, {0x16, NULL}, + {0x18, NULL}, {0x23, ®_val[3]}, + {0x2d, ®_val[4]}, {4, ®_val[5]}, + }; +#ifdef CONFIG_DM_I2C + struct udevice *udev; +#endif + /* Set I2c to Slot 1 */ - i2c_write(0x77, 0, 0, &a, 1); +#ifndef CONFIG_DM_I2C + ret = i2c_write(0x77, 0, 0, &a, 1); +#else + ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, 0, &a, 1); +#endif + if (ret) + goto error; switch (dpmac) { case 1: @@ -144,31 +169,34 @@ static void sgmii_configure_repeater(int dpmac) return; } +#ifdef CONFIG_DM_I2C + i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev); +#endif + for (i = 0; i < 4; i++) { for (j = 0; j < 4; j++) { - a = 0x18; - i2c_write(i2c_phy_addr, 6, 1, &a, 1); - a = 0x38; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); - a = 0x4; - i2c_write(i2c_phy_addr, 8, 1, &a, 1); - - i2c_write(i2c_phy_addr, 0xf, 1, - &ch_a_eq[i], 1); - i2c_write(i2c_phy_addr, 0x11, 1, - &ch_a_ctl2[j], 1); - - i2c_write(i2c_phy_addr, 0x16, 1, - &ch_b_eq[i], 1); - i2c_write(i2c_phy_addr, 0x18, 1, - &ch_b_ctl2[j], 1); - - a = 0x14; - i2c_write(i2c_phy_addr, 0x23, 1, &a, 1); - a = 0xb5; - i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1); - a = 0x20; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); + reg_pair[3].val = &ch_a_eq[i]; + reg_pair[4].val = &ch_a_ctl2[j]; + reg_pair[5].val = &ch_b_eq[i]; + reg_pair[6].val = &ch_b_ctl2[j]; + for (k = 0; k < 10; k++) { +#ifndef CONFIG_DM_I2C + ret = i2c_write(i2c_phy_addr, + reg_pair[k].addr, + 1, reg_pair[k].val, 1); +#else + ret = i2c_get_chip_for_busnum(0, + i2c_phy_addr, + 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, + reg_pair[k].addr, + reg_pair[k].val, 1); +#endif + if (ret) + goto error; + } + mdelay(100); ret = miiphy_read(dev, phy_addr, 0x11, &value); if (ret > 0) @@ -203,7 +231,7 @@ error: static void qsgmii_configure_repeater(int dpmac) { uint8_t a = 0xf; - int i, j; + int i, j, k; int i2c_phy_addr = 0; int phy_addr = 0; int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b}; @@ -213,12 +241,32 @@ static void qsgmii_configure_repeater(int dpmac) uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20}; + struct reg_pair reg_pair[10] = { + {6, ®_val[0]}, {4, ®_val[1]}, + {8, ®_val[2]}, {0xf, NULL}, + {0x11, NULL}, {0x16, NULL}, + {0x18, NULL}, {0x23, ®_val[3]}, + {0x2d, ®_val[4]}, {4, ®_val[5]}, + }; + const char *dev = mdio_names[EMI1_SLOT1]; int ret = 0; unsigned short value; +#ifdef CONFIG_DM_I2C + struct udevice *udev; +#endif /* Set I2c to Slot 1 */ - i2c_write(0x77, 0, 0, &a, 1); +#ifndef CONFIG_DM_I2C + ret = i2c_write(0x77, 0, 0, &a, 1); +#else + ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, 0, &a, 1); +#endif + if (ret) + goto error; switch (dpmac) { case 7: @@ -252,28 +300,35 @@ static void qsgmii_configure_repeater(int dpmac) return; } +#ifdef CONFIG_DM_I2C + i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev); +#endif + for (i = 0; i < 4; i++) { for (j = 0; j < 4; j++) { - a = 0x18; - i2c_write(i2c_phy_addr, 6, 1, &a, 1); - a = 0x38; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); - a = 0x4; - i2c_write(i2c_phy_addr, 8, 1, &a, 1); - - i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1); - i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1); - - i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1); - i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1); - - a = 0x14; - i2c_write(i2c_phy_addr, 0x23, 1, &a, 1); - a = 0xb5; - i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1); - a = 0x20; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); - mdelay(100); + reg_pair[3].val = &ch_a_eq[i]; + reg_pair[4].val = &ch_a_ctl2[j]; + reg_pair[5].val = &ch_b_eq[i]; + reg_pair[6].val = &ch_b_ctl2[j]; + + for (k = 0; k < 10; k++) { +#ifndef CONFIG_DM_I2C + ret = i2c_write(i2c_phy_addr, + reg_pair[k].addr, + 1, reg_pair[k].val, 1); +#else + ret = i2c_get_chip_for_busnum(0, + i2c_addr[dpmac], + 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, + reg_pair[k].addr, + reg_pair[k].val, 1); +#endif + if (ret) + goto error; + } + ret = miiphy_read(dev, phy_addr, 0x11, &value); if (ret > 0) goto error; -- cgit v1.2.1 From 2e35d07658c885c604048f43eb7d562840843c7d Mon Sep 17 00:00:00 2001 From: Pankaj Bansal Date: Wed, 17 Jul 2019 09:34:34 +0000 Subject: boards: fsl: lx2160ardb: enable flexcan Flexcan in LX2160ARDB is controlled by FPGA register boardcfg4 bit 5. enable this bit so that flexcan is enabled in LX2160ARDB. Signed-off-by: Pankaj Bansal Reviewed-by: Prabhakar Kushwaha --- board/freescale/lx2160a/lx2160a.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'board') diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 163b42dda4..7f19a1a145 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -410,6 +410,26 @@ int config_board_mux(void) return 0; } +#elif defined(CONFIG_TARGET_LX2160ARDB) +int config_board_mux(void) +{ + u8 brdcfg; + + brdcfg = QIXIS_READ(brdcfg[4]); + /* The BRDCFG4 register controls general board configuration. + *|-------------------------------------------| + *|Field | Function | + *|-------------------------------------------| + *|5 | CAN I/O Enable (net CFG_CAN_EN_B):| + *|CAN_EN | 0= CAN transceivers are disabled. | + *| | 1= CAN transceivers are enabled. | + *|-------------------------------------------| + */ + brdcfg |= BIT_MASK(5); + QIXIS_WRITE(brdcfg[4], brdcfg); + + return 0; +} #else int config_board_mux(void) { -- cgit v1.2.1 From 1748990ab2a0e995beeed6b3856335f579bb77d9 Mon Sep 17 00:00:00 2001 From: Chuanhua Han Date: Thu, 1 Aug 2019 16:36:57 +0800 Subject: armv8: ls1088aqds: support DSPI mode by hwconfig BRDCFG4[USBOSC] and BRDCFG5[SPR] register field of Qixis device is used to control SPI and other IP signal routing. USBOSC: 0= SPI_CLK used as external USB REFCLK input driven with 24.000 MHz. SPI devices are unusable in this mode. 1= SPI_CLK used as SPI clock. SPI devices are usable in this mode. USB block is clocked from internal sources SPR[3:2]: SPI_CS / SDHC_DAT4:7 Routing (schematic net CFG_SPI_ROUTE[3:2]): 00= SDHC/eMMC 8-bit 01= SD Card Rev 2.0/3.0 10= SPI on-board memory 11= TDM Riser / SPI off-board connector. The default value is 00 if an SDCard/eMMC card is selected as the boot device. SPR[1:0]: SPI_SIN/SOUT/SCK Routing (schematic net CFG_SPI_ROUTE[1:0]): 00= SDHC Sync loop 01= TDM Riser / SPI off-board connector. 10= SPI on-board memory. 11= SPI off-board connector. By default, the SPI feature is not available, so we need to configure the above register fields to select the route to the SPI feature. Signed-off-by: Chuanhua Han Reviewed-by: Prabhakar Kushwaha --- board/freescale/ls1088a/ls1088a.c | 26 ++++++++++++++++++++++++++ board/freescale/ls1088a/ls1088a_qixis.h | 11 +++++++++++ 2 files changed, 37 insertions(+) (limited to 'board') diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 1033d44409..b851e159bc 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -591,6 +591,32 @@ int misc_init_r(void) QIXIS_WRITE(brdcfg[5], brdcfg5); } #endif + +#ifdef CONFIG_TARGET_LS1088AQDS + u8 brdcfg4, brdcfg5; + + if (hwconfig("dspi-on-board")) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_USBOSC_MASK; + brdcfg4 |= BRDCFG4_SPI; + QIXIS_WRITE(brdcfg[4], brdcfg4); + + brdcfg5 = QIXIS_READ(brdcfg[5]); + brdcfg5 &= ~BRDCFG5_SPR_MASK; + brdcfg5 |= BRDCFG5_SPI_ON_BOARD; + QIXIS_WRITE(brdcfg[5], brdcfg5); + } else if (hwconfig("dspi-off-board")) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_USBOSC_MASK; + brdcfg4 |= BRDCFG4_SPI; + QIXIS_WRITE(brdcfg[4], brdcfg4); + + brdcfg5 = QIXIS_READ(brdcfg[5]); + brdcfg5 &= ~BRDCFG5_SPR_MASK; + brdcfg5 |= BRDCFG5_SPI_OFF_BOARD; + QIXIS_WRITE(brdcfg[5], brdcfg5); + } +#endif return 0; } #endif diff --git a/board/freescale/ls1088a/ls1088a_qixis.h b/board/freescale/ls1088a/ls1088a_qixis.h index c58852617f..e3502eb1d1 100644 --- a/board/freescale/ls1088a/ls1088a_qixis.h +++ b/board/freescale/ls1088a/ls1088a_qixis.h @@ -41,4 +41,15 @@ #define BRDCFG5_SPISDHC_MASK 0x0C #define BRDCFG5_FORCE_SD 0x08 +/* Definitions of QIXIS Registers for LS1088AQDS */ + +/* BRDCFG4 */ +#define BRDCFG4_USBOSC_MASK 0x01 +#define BRDCFG4_SPI 0x01 + +/* BRDCFG5 */ +#define BRDCFG5_SPR_MASK 0x0f +#define BRDCFG5_SPI_ON_BOARD 0x0a +#define BRDCFG5_SPI_OFF_BOARD 0x0f + #endif -- cgit v1.2.1 From 5c6dc6c9a9a5f253f3928a97ca020712177884e7 Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Tue, 30 Jul 2019 17:29:58 +0300 Subject: armv8: ls1088a: add icid setup for platform devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. The ICID macros for SEC needed to be adapted because the format of the registers is different. Signed-off-by: Laurentiu Tudor Reviewed-by: Horia Geantă Reviewed-by: Prabhakar Kushwaha --- board/freescale/ls1088a/ls1088a.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'board') diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index b851e159bc..f1592982a3 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -21,6 +21,7 @@ #include #include #include +#include #include "../common/qixis.h" #include "ls1088a_qixis.h" @@ -968,6 +969,9 @@ int ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); #endif + + fdt_fixup_icid(blob); + if (is_pb_board()) fixup_ls1088ardb_pb_banner(blob); -- cgit v1.2.1 From b249fcba00e093149f8424492da155572f12d7bb Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Tue, 30 Jul 2019 17:29:59 +0300 Subject: armv8: ls1028a: add icid setup for platform devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, edma, qdma, gpu, display and sec. Signed-off-by: Laurentiu Tudor Reviewed-by: Horia Geantă Reviewed-by: Prabhakar Kushwaha --- board/freescale/ls1028a/ls1028a.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'board') diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c index 1410d0f920..095971448f 100644 --- a/board/freescale/ls1028a/ls1028a.c +++ b/board/freescale/ls1028a/ls1028a.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #ifdef CONFIG_FSL_LS_PPA @@ -143,6 +144,8 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory_banks(blob, base, size, 2); + fdt_fixup_icid(blob); + return 0; } #endif -- cgit v1.2.1