From bfc81252c0de3bfcf92c7c35bc04341fb33e4e4e Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 6 Mar 2006 13:03:37 +0100 Subject: Minor code cleanup --- board/amcc/bamboo/config.mk | 1 - board/bmw/config.mk | 1 - board/dave/PPChameleonEVB/config.mk | 1 - board/dave/PPChameleonEVB/nand.c | 2 +- board/esd/common/auto_update.c | 3 - board/esd/common/cmd_loadpci.c | 1 - board/esd/cpci2dp/cpci2dp.c | 4 +- board/esd/cpci405/config.mk | 1 - board/esd/cpci750/cpci750.c | 1 - board/esd/cpci750/pci.c | 192 ++++++++++++++++++------------------ board/esd/hh405/config.mk | 1 - board/esd/hub405/config.mk | 1 - board/mcc200/mcc200.c | 60 ----------- board/mcc200/mt48lc8m32b2-6-7.h | 18 ---- board/netstar/config.mk | 1 - board/netta2/config.mk | 1 - 16 files changed, 99 insertions(+), 190 deletions(-) (limited to 'board') diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk index b6495de692..433429bea7 100644 --- a/board/amcc/bamboo/config.mk +++ b/board/amcc/bamboo/config.mk @@ -35,4 +35,3 @@ endif # legacy nand support BOARDLIBS = drivers/nand_legacy/libnand_legacy.a - diff --git a/board/bmw/config.mk b/board/bmw/config.mk index 10b7a9f5ea..f9915496ad 100644 --- a/board/bmw/config.mk +++ b/board/bmw/config.mk @@ -30,4 +30,3 @@ TEXT_BASE = 0xFFF00000 PLATFORM_CPPFLAGS += -DEMBEDDED -DBIG_ENDIAN_HOST -DINCLUDE_5701_AX_FIX=1\ -DDBG=0 -DT3_JUMBO_RCV_RCB_ENTRY_COUNT=256\ -DTEXT_BASE=$(TEXT_BASE) - diff --git a/board/dave/PPChameleonEVB/config.mk b/board/dave/PPChameleonEVB/config.mk index 5d3df0c858..1dc635fbf0 100644 --- a/board/dave/PPChameleonEVB/config.mk +++ b/board/dave/PPChameleonEVB/config.mk @@ -32,4 +32,3 @@ BOARDLIBS = drivers/nand/libnand.a # Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) #BOARDLIBS = drivers/nand_legacy/libnand_legacy.a - diff --git a/board/dave/PPChameleonEVB/nand.c b/board/dave/PPChameleonEVB/nand.c index 61edc787fa..40a827c3e2 100644 --- a/board/dave/PPChameleonEVB/nand.c +++ b/board/dave/PPChameleonEVB/nand.c @@ -81,7 +81,7 @@ static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo) break; } - if (in32(GPIO0_IR) & rb_gpio_pin) + if (in32(GPIO0_IR) & rb_gpio_pin) return 1; return 0; } diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index 5a70176fad..cad82115cc 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -42,9 +42,6 @@ #error "must define CFG_CMD_FAT" #endif - - - extern au_image_t au_image[]; extern int N_AU_IMAGES; diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c index 3478f825c5..bf796ff9d1 100644 --- a/board/esd/common/cmd_loadpci.c +++ b/board/esd/common/cmd_loadpci.c @@ -120,4 +120,3 @@ U_BOOT_CMD( ); #endif - diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index 2800420e2a..1a27ca0911 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -36,9 +36,9 @@ int board_early_init_f (void) cntrl0Reg = mfdcr(cntrl0); mtdcr(cntrl0, cntrl0Reg | ((CFG_EEPROM_WP | CFG_PB_LED | CFG_SELF_RST | CFG_INTA_FAKE) << 5)); - /* set output pins to high */ + /* set output pins to high */ out32(GPIO0_OR, CFG_EEPROM_WP); - /* setup for output (LED=off) */ + /* setup for output (LED=off) */ out32(GPIO0_TCR, CFG_EEPROM_WP | CFG_PB_LED); /* diff --git a/board/esd/cpci405/config.mk b/board/esd/cpci405/config.mk index 320346f089..ceff4c4d1e 100644 --- a/board/esd/cpci405/config.mk +++ b/board/esd/cpci405/config.mk @@ -41,4 +41,3 @@ endif # Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) BOARDLIBS = drivers/nand_legacy/libnand_legacy.a - diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c index fd0f904cfe..dbed597173 100644 --- a/board/esd/cpci750/cpci750.c +++ b/board/esd/cpci750/cpci750.c @@ -378,7 +378,6 @@ int misc_init_r () CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[3]); - } return 0; } diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c index 37c7150423..c335ebf0bf 100644 --- a/board/esd/cpci750/pci.c +++ b/board/esd/cpci750/pci.c @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -46,8 +46,8 @@ static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { #ifdef CONFIG_USE_CPCIDVI typedef struct { - unsigned int base; - unsigned int init; + unsigned int base; + unsigned int init; } GT_CPCIDVI_ROM_T; static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0}; @@ -133,20 +133,20 @@ static const unsigned int pci_p2p_configuration[] = { /******************************************************************** * pciWriteConfigReg - Write to a PCI configuration register -* - Make sure the GT is configured as a master before writing -* to another device on the PCI. -* - The function takes care of Big/Little endian conversion. +* - Make sure the GT is configured as a master before writing +* to another device on the PCI. +* - The function takes care of Big/Little endian conversion. * * * Inputs: unsigned int regOffset: The register offset as it apears in the GT spec -* (or any other PCI device spec) -* pciDevNum: The device number needs to be addressed. +* (or any other PCI device spec) +* pciDevNum: The device number needs to be addressed. * * Configuration Address 0xCF8: * -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number * |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name +* |Enable| |Number|Number| Number | Number | | <=field Name * *********************************************************************/ void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, @@ -180,20 +180,20 @@ void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, /******************************************************************** * pciReadConfigReg - Read from a PCI0 configuration register -* - Make sure the GT is configured as a master before reading -* from another device on the PCI. -* - The function takes care of Big/Little endian conversion. +* - Make sure the GT is configured as a master before reading +* from another device on the PCI. +* - The function takes care of Big/Little endian conversion. * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec) -* pciDevNum: The device number needs to be addressed. +* spec) +* pciDevNum: The device number needs to be addressed. * RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid +* cause register to make sure the data is valid * * Configuration Address 0xCF8: * -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number * |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name +* |Enable| |Number|Number| Number | Number | | <=field Name * *********************************************************************/ unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, @@ -228,21 +228,21 @@ unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, /******************************************************************** * pciOverBridgeWriteConfigReg - Write to a PCI configuration register where -* the agent is placed on another Bus. For more -* information read P2P in the PCI spec. +* the agent is placed on another Bus. For more +* information read P2P in the PCI spec. * * Inputs: unsigned int regOffset - The register offset as it apears in the -* GT spec (or any other PCI device spec). -* unsigned int pciDevNum - The device number needs to be addressed. -* unsigned int busNum - On which bus does the Target agent connect -* to. -* unsigned int data - data to be written. +* GT spec (or any other PCI device spec). +* unsigned int pciDevNum - The device number needs to be addressed. +* unsigned int busNum - On which bus does the Target agent connect +* to. +* unsigned int data - data to be written. * * Configuration Address 0xCF8: * -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number * |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name +* |Enable| |Number|Number| Number | Number | | <=field Name * * The configuration Address is configure as type-I (bits[1:0] = '01') due to * PCI spec referring to P2P. @@ -273,23 +273,23 @@ void pciOverBridgeWriteConfigReg (PCI_HOST host, /******************************************************************** * pciOverBridgeReadConfigReg - Read from a PCIn configuration register where -* the agent target locate on another PCI bus. -* - Make sure the GT is configured as a master -* before reading from another device on the PCI. -* - The function takes care of Big/Little endian -* conversion. +* the agent target locate on another PCI bus. +* - Make sure the GT is configured as a master +* before reading from another device on the PCI. +* - The function takes care of Big/Little endian +* conversion. * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec). (configuration register offset.) -* pciDevNum: The device number needs to be addressed. -* busNum: the Bus number where the agent is place. +* spec). (configuration register offset.) +* pciDevNum: The device number needs to be addressed. +* busNum: the Bus number where the agent is place. * RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid +* cause register to make sure the data is valid * * Configuration Address 0xCF8: * -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number * |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name +* |Enable| |Number|Number| Number | Number | | <=field Name * *********************************************************************/ unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, @@ -393,7 +393,7 @@ static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) /******************************************************************** * pciGetBaseAddress - Gets the base address of a PCI. -* - If the PCI size is 0 then this base address has no meaning!!! +* - If the PCI size is 0 then this base address has no meaning!!! * * * INPUT: Bus, Region - The bus and region we ask for its base address. @@ -501,13 +501,13 @@ void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, /******************************************************************** * pciSetRegionFeatures - This function modifys one of the 8 regions with -* feature bits given as an input. -* - Be advised to check the spec before modifying them. +* feature bits given as an input. +* - Be advised to check the spec before modifying them. * Inputs: PCI_PROTECT_REGION region - one of the eight regions. -* unsigned int features - See file: pci.h there are defintion for those -* region features. -* unsigned int baseAddress - The region base Address. -* unsigned int topAddress - The region top Address. +* unsigned int features - See file: pci.h there are defintion for those +* region features. +* unsigned int baseAddress - The region base Address. +* unsigned int topAddress - The region top Address. * Returns: false if one of the parameters is erroneous true otherwise. *********************************************************************/ bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, @@ -541,7 +541,7 @@ bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, /******************************************************************** * pciDisableAccessRegion - Disable The given Region by writing MAX size -* to its low Address and MIN size to its high Address. +* to its low Address and MIN size to its high Address. * * Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. * Returns: N/A. @@ -588,12 +588,12 @@ bool pciArbiterDisable (PCI_HOST host) * pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) * * Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. -* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. -* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. -* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. -* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. -* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. -* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. +* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. +* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. +* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. +* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. +* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. +* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. * Returns: true *********************************************************************/ bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, @@ -619,17 +619,17 @@ bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, /******************************************************************** * pciParkingDisable - Park on last option disable, with this function you can -* disable the park on last mechanism for each agent. -* disabling this option for all agents results parking -* on the internal master. +* disable the park on last mechanism for each agent. +* disabling this option for all agents results parking +* on the internal master. * * Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. -* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. -* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. -* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. -* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. -* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. -* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. +* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. +* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. +* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. +* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. +* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. +* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. * Returns: true *********************************************************************/ bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, @@ -655,11 +655,11 @@ bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, /******************************************************************** * pciEnableBrokenAgentDetection - A master is said to be broken if it fails to -* respond to grant assertion within a window specified in -* the input value: 'brokenValue'. +* respond to grant assertion within a window specified in +* the input value: 'brokenValue'. * * Inputs: unsigned char brokenValue - A value which limits the Master to hold the -* grant without asserting frame. +* grant without asserting frame. * Returns: Error for illegal broken value otherwise true. *********************************************************************/ bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) @@ -678,9 +678,9 @@ bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) /******************************************************************** * pciDisableBrokenAgentDetection - This function disable the Broken agent -* Detection mechanism. -* NOTE: This operation may cause a dead lock on the -* pci0 arbitration. +* Detection mechanism. +* NOTE: This operation may cause a dead lock on the +* pci0 arbitration. * * Inputs: N/A * Returns: true. @@ -697,15 +697,15 @@ bool pciDisableBrokenAgentDetection (PCI_HOST host) /******************************************************************** * pciP2PConfig - This function set the PCI_n P2P configurate. -* For more information on the P2P read PCI spec. +* For more information on the P2P read PCI spec. * * Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower -* Boundry. -* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper -* Boundry. -* unsigned int busNum - The CPI bus number to which the PCI interface -* is connected. -* unsigned int devNum - The PCI interface's device number. +* Boundry. +* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper +* Boundry. +* unsigned int busNum - The CPI bus number to which the PCI interface +* is connected. +* unsigned int devNum - The PCI interface's device number. * * Returns: true. *********************************************************************/ @@ -723,15 +723,15 @@ bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow, /******************************************************************** * pciSetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency in the PCI_n interface. +* supports Cache Coherency in the PCI_n interface. * Inputs: region - One of the four regions. -* snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* baseAddress - Base Address of this region. -* regionLength - Region length. +* snoopType - There is four optional Types: +* 1. No Snoop. +* 2. Snoop to WT region. +* 3. Snoop to WB region. +* 4. Snoop & Invalidate to WB region. +* baseAddress - Base Address of this region. +* regionLength - Region length. * Returns: false if one of the parameters is wrong otherwise return true. *********************************************************************/ bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, @@ -754,7 +754,7 @@ bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, GT_REG_WRITE (snoopXtopAddress, 0); return true; } - baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ + baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ data = (baseAddress >> 20) | snoopType << 12; GT_REG_WRITE (snoopXbaseAddress, data); snoopHigh = (snoopHigh & 0xfff00000) >> 20; @@ -827,7 +827,7 @@ static void gt_setup_ide (struct pci_controller *hose, static void gt_setup_cpcidvi (struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *entry) { - u32 bar_value, pci_response; + u32 bar_value, pci_response; pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response); pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); @@ -843,30 +843,30 @@ static void gt_setup_cpcidvi (struct pci_controller *hose, unsigned char gt_cpcidvi_in8(unsigned int offset) { - unsigned char data; + unsigned char data; if (gt_cpcidvi_rom.init == 0) { - return(0); - } - data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base); - return(data); + return(0); + } + data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base); + return(data); } void gt_cpcidvi_out8(unsigned int offset, unsigned char data) { - unsigned int off; - + unsigned int off; + if (gt_cpcidvi_rom.init == 0) { - return; - } + return; + } off = data; off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base; - in8(off); - return; + in8(off); + return; } #endif -/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ +/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ /* and is curently not called *. */ #if 0 static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) diff --git a/board/esd/hh405/config.mk b/board/esd/hh405/config.mk index ca1f57572b..798a3fa413 100644 --- a/board/esd/hh405/config.mk +++ b/board/esd/hh405/config.mk @@ -32,4 +32,3 @@ TEXT_BASE = 0xFFF80000 # Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) BOARDLIBS = drivers/nand_legacy/libnand_legacy.a - diff --git a/board/esd/hub405/config.mk b/board/esd/hub405/config.mk index 22ff1226bc..4c60c3566d 100644 --- a/board/esd/hub405/config.mk +++ b/board/esd/hub405/config.mk @@ -29,4 +29,3 @@ TEXT_BASE = 0xFFFC0000 # Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) BOARDLIBS = drivers/nand_legacy/libnand_legacy.a - diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c index acc0e06862..d1c99fdd85 100644 --- a/board/mcc200/mcc200.c +++ b/board/mcc200/mcc200.c @@ -28,19 +28,12 @@ #include #include -//###CHD: es gibt eigentlich kein DDR bei uns -> weg damit!; dto. PCI! -#if defined(CONFIG_MPC5200_DDR) -#include "mt46v16m16-75.h" -#else -//#include "mt48lc16m16a2-75.h" #include "mt48lc8m32b2-6-7.h" -#endif extern flash_info_t flash_info[]; /* FLASH chips info */ ulong flash_get_size (ulong base, int banknum); -//###CHD: wenn RAMBOOT gehen wuerde, .... #ifndef CFG_RAMBOOT static void sdram_start (int hi_addr) { @@ -88,7 +81,6 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -#if defined(CONFIG_MPC5200) long int initdram (int board_type) { ulong dramsize = 0; @@ -190,58 +182,6 @@ long int initdram (int board_type) return dramsize + dramsize2; } -//###CHD: sowas gibt es bei usn nicht! -#elif defined(CONFIG_MGT5100) - -long int initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CFG_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; - __asm__ volatile ("sync"); - - /* find RAM size */ - sdram_start(0); - test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CFG_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CFG_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif - int checkboard (void) { puts ("Board: MCC200\n"); diff --git a/board/mcc200/mt48lc8m32b2-6-7.h b/board/mcc200/mt48lc8m32b2-6-7.h index 6c2b2b3b36..73dcd5c0a3 100644 --- a/board/mcc200/mt48lc8m32b2-6-7.h +++ b/board/mcc200/mt48lc8m32b2-6-7.h @@ -4,27 +4,9 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ -//#define SDRAM_MODE 0x00cc0000 // CL-3 BURST-8 -> Mode Register—MBAR + 0x0100 -//#define SDRAM_CONTROL 0x501f0000 // Control Register—MBAR + 0x0104 -//#define SDRAM_CONFIG1 0xe2329000 // Delays between commands -> Configuration Register 1—MBAR + 0x0108 -//#define SDRAM_CONFIG2 0x46e70000 // Delays between commands -> Configuration Register 2—MBAR + 0x010C -//Christian -//#define SDRAM_MODE 0x00cd0000 // CL-3 BURST-8 -> Mode Register—MBAR + 0x0100 -//#define SDRAM_CONTROL 0x501f0000 // Control Register—MBAR + 0x0104 -//#define SDRAM_CONFIG1 0xd2322900 // Delays between commands -> Configuration Register 1—MBAR + 0x0108 -//#define SDRAM_CONFIG2 0x8ad70000 // Delays between commands -> Configuration Register 2—MBAR + 0x010C - -//###CHD: ordentliche Doku dazu! CAS=2, etc. -//STefan #define SDRAM_MODE 0x008d0000 // CL-3 BURST-8 -> Mode Register—MBAR + 0x0100 #define SDRAM_CONTROL 0x504f0000 // Control Register—MBAR + 0x0104 #define SDRAM_CONFIG1 0xc2222900 // Delays between commands -> Configuration Register 1—MBAR + 0x0108 #define SDRAM_CONFIG2 0x88c70000 // Delays between commands -> Configuration Register 2—MBAR + 0x010C - - -#else -#error CONFIG_MPC5200 not defined, please set parameters for your sdram controller in mt48lc8m32b2.h -#endif diff --git a/board/netstar/config.mk b/board/netstar/config.mk index 2e3921b101..50d647add0 100644 --- a/board/netstar/config.mk +++ b/board/netstar/config.mk @@ -12,4 +12,3 @@ TEXT_BASE = 0x13FC0000 # Compile the new NAND code BOARDLIBS = drivers/nand/libnand.a - diff --git a/board/netta2/config.mk b/board/netta2/config.mk index 4b636ed88d..de179c2d65 100644 --- a/board/netta2/config.mk +++ b/board/netta2/config.mk @@ -29,4 +29,3 @@ TEXT_BASE = 0x40000000 # Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) BOARDLIBS = drivers/nand_legacy/libnand_legacy.a - -- cgit v1.2.1