From f2ff834365296151b24bf8617f1f6dd070bdce9e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 17 Aug 2015 16:11:03 +0800 Subject: imx: mx6: ddr init MMDC according to ddr_type To i.MX6, DDR3 and LPDDR2 is supported, so rename function mx6_dram_cfg to mx6_ddr3_cfg and the original mx6_dram_cfg function only is a wrapper. The new reimplemented function mx6_dram_cfg only invokes mx6_ddr3_cfg when ddr_type is for DDR3. Later we can use ddr_type to initialize MMDC for LPDDR2. Initialize ddr_type for different boards which enable SPL. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Tim Harvey Cc: Stefan Roese Cc: Fabio Estevam Reviewed-by: Stefan Roese --- board/barco/platinum/spl_picon.c | 1 + board/barco/platinum/spl_titanium.c | 1 + 2 files changed, 2 insertions(+) (limited to 'board/barco/platinum') diff --git a/board/barco/platinum/spl_picon.c b/board/barco/platinum/spl_picon.c index f421c2108c..098542fbd2 100644 --- a/board/barco/platinum/spl_picon.c +++ b/board/barco/platinum/spl_picon.c @@ -137,6 +137,7 @@ static void spl_dram_init(int width) .bi_on = 1, /* Bank interleaving enabled */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, }; mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); diff --git a/board/barco/platinum/spl_titanium.c b/board/barco/platinum/spl_titanium.c index 26fe26ba2b..a3a42551b0 100644 --- a/board/barco/platinum/spl_titanium.c +++ b/board/barco/platinum/spl_titanium.c @@ -140,6 +140,7 @@ static void spl_dram_init(int width) .bi_on = 1, /* Bank interleaving enabled */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, }; mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); -- cgit v1.2.1