From cb686454c74c20617a91276083c41b19f7d118ad Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Mon, 24 Apr 2017 18:45:21 +0300
Subject: phy: marvell: Replace PHY_TYPE_KR with PHY_TYPE_SFI

Use correct naming as done in the latest Marvell U-Boot version as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
---
 arch/arm/dts/armada-8040-db.dts    |  8 ++++----
 arch/arm/dts/armada-8040-mcbin.dts | 10 +++++-----
 2 files changed, 9 insertions(+), 9 deletions(-)

(limited to 'arch/arm')

diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts
index 1fcb9f4963..fa589956ad 100644
--- a/arch/arm/dts/armada-8040-db.dts
+++ b/arch/arm/dts/armada-8040-db.dts
@@ -113,7 +113,7 @@
 	/* Serdes Configuration:
 	 *	Lane 0: PCIe0 (x1)
 	 *	Lane 1: SATA0
-	 *	Lane 2: KR (10G)
+	 *	Lane 2: SFI (10G)
 	 *	Lane 3: SATA1
 	 *	Lane 4: USB3_HOST1
 	 *	Lane 5: PCIe2 (x1)
@@ -125,7 +125,7 @@
 		phy-type = <PHY_TYPE_SATA0>;
 	};
 	phy2 {
-		phy-type = <PHY_TYPE_KR>;
+		phy-type = <PHY_TYPE_SFI>;
 	};
 	phy3 {
 		phy-type = <PHY_TYPE_SATA1>;
@@ -205,7 +205,7 @@
 	/* Serdes Configuration:
 	 *	Lane 0: PCIe0 (x1)
 	 *	Lane 1: SATA0
-	 *	Lane 2: KR (10G)
+	 *	Lane 2: SFI (10G)
 	 *	Lane 3: SATA1
 	 *	Lane 4: PCIe1 (x1)
 	 *	Lane 5: PCIe2 (x1)
@@ -217,7 +217,7 @@
 		phy-type = <PHY_TYPE_SATA0>;
 	};
 	phy2 {
-		phy-type = <PHY_TYPE_KR>;
+		phy-type = <PHY_TYPE_SFI>;
 	};
 	phy3 {
 		phy-type = <PHY_TYPE_SATA1>;
diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts
index e42b092b25..dde495ae4f 100644
--- a/arch/arm/dts/armada-8040-mcbin.dts
+++ b/arch/arm/dts/armada-8040-mcbin.dts
@@ -99,7 +99,7 @@
 	 * [54] 2.5G SFP LOS
 	 * [55] Micro SD card detect
 	 * [56-61] Micro SD
-	 * [62] CP1 KR SFP FAULT
+	 * [62] CP1 SFI SFP FAULT
 	 */
 		/*   0    1    2    3    4    5    6    7    8    9 */
 	pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
@@ -163,7 +163,7 @@
 	 * Lane 1: PCIe0 (x4)
 	 * Lane 2: PCIe0 (x4)
 	 * Lane 3: PCIe0 (x4)
-	 * Lane 4: KR (10G)
+	 * Lane 4: SFI (10G)
 	 * Lane 5: SATA1
 	 */
 	phy0 {
@@ -179,7 +179,7 @@
 		phy-type = <PHY_TYPE_PEX0>;
 	};
 	phy4 {
-		phy-type = <PHY_TYPE_KR>;
+		phy-type = <PHY_TYPE_SFI>;
 	};
 	phy5 {
 		phy-type = <PHY_TYPE_SATA1>;
@@ -268,7 +268,7 @@
 	 * Lane 1: SATA 0
 	 * Lane 2: USB HOST 0
 	 * Lane 3: SATA1
-	 * Lane 4: KR (10G)
+	 * Lane 4: SFI (10G)
 	 * Lane 5: SGMII3
 	 */
 	phy0 {
@@ -285,7 +285,7 @@
 		phy-type = <PHY_TYPE_SATA1>;
 	};
 	phy4 {
-		phy-type = <PHY_TYPE_KR>;
+		phy-type = <PHY_TYPE_SFI>;
 	};
 	phy5 {
 		phy-type = <PHY_TYPE_SGMII3>;
-- 
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