From 83605d37b00168d4960a752cff898d09d3062015 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 26 Jul 2017 18:23:05 +0200 Subject: mx6: Add support for Phytec pfla02 (NAND) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for Phytec pfla02, equipped with NAND. CPU: Freescale i.MX6Q rev1.5 996 MHz (running at 792 MHz) CPU: Automotive temperature grade (-40C to 125C) at 31C Reset cause: POR I2C: ready DRAM: 1 GiB NAND: 2048 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 SF: Detected n25q128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 Signed-off-by: Stefano Babic CC: Stefan Christ CC: Stefan Müller-Klieser CC: Christian Hemp --- arch/arm/mach-imx/mx6/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/mach-imx/mx6') diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index bb2ce33132..3ffdea20a1 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -331,6 +331,11 @@ config TARGET_PCM058 select BOARD_LATE_INIT select SUPPORT_SPL +config TARGET_PFLA02 + bool "Phytec PFLA02 (PhyFlex) i.MX6 Quad" + select BOARD_LATE_INIT + select SUPPORT_SPL + config TARGET_SECOMX6 bool "secomx6 boards" @@ -428,6 +433,7 @@ source "board/freescale/mx6ul_14x14_evk/Kconfig" source "board/freescale/mx6ullevk/Kconfig" source "board/grinn/liteboard/Kconfig" source "board/phytec/pcm058/Kconfig" +source "board/phytec/pfla02/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/kosagi/novena/Kconfig" source "board/samtec/vining_2000/Kconfig" -- cgit v1.2.1 From ff3a5fc46d492fd46d392c73f4c58cb3060d4fd6 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Wed, 2 Aug 2017 16:05:12 +0200 Subject: imx6: clock: correct comment for PLL_VIDEO This appear to be a copy-paste error, clean it up. Signed-off-by: Anatolij Gustschin Reviewed-by: Stefano Babic --- arch/arm/mach-imx/mx6/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-imx/mx6') diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index 1f2739e864..0e019c4262 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -19,7 +19,7 @@ enum pll_clocks { PLL_USBOTG, /* OTG USB PLL */ PLL_ENET, /* ENET PLL */ PLL_AUDIO, /* AUDIO PLL */ - PLL_VIDEO, /* AUDIO PLL */ + PLL_VIDEO, /* VIDEO PLL */ }; struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; -- cgit v1.2.1 From 44e670532dd9e29bc25f136db8b00c49bef42c4d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?S=C3=A9bastien=20Szymanski?= Date: Wed, 2 Aug 2017 17:05:26 +0200 Subject: imx: imx6ul: correct get_cpu_speed_grade_hz on 696MHz SoCs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Return the correct value when the speed grade is 696MHz. Signed-off-by: Sébastien Szymanski --- arch/arm/mach-imx/mx6/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-imx/mx6') diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index af316735ee..760745656f 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -130,7 +130,7 @@ u32 get_cpu_speed_grade_hz(void) if (val == OCOTP_CFG3_SPEED_528MHZ) return 528000000; else if (val == OCOTP_CFG3_SPEED_696MHZ) - return 69600000; + return 696000000; else return 0; } -- cgit v1.2.1 From 0c7c6fb7641646c45630235ea906200981f4fe80 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?S=C3=A9bastien=20Szymanski?= Date: Wed, 2 Aug 2017 17:05:27 +0200 Subject: imx: imx6ull: correct get_cpu_speed_grade_hz MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit i.MX6ULL has different speed grades than i.MX6UL. Signed-off-by: Sébastien Szymanski --- arch/arm/mach-imx/mx6/soc.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-imx/mx6') diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index 760745656f..c15b9cb8e2 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -114,6 +114,12 @@ u32 get_cpu_rev(void) #define OCOTP_CFG3_SPEED_528MHZ 1 #define OCOTP_CFG3_SPEED_696MHZ 2 +/* + * For i.MX6ULL + */ +#define OCOTP_CFG3_SPEED_792MHZ 2 +#define OCOTP_CFG3_SPEED_900MHZ 3 + u32 get_cpu_speed_grade_hz(void) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; @@ -126,7 +132,7 @@ u32 get_cpu_speed_grade_hz(void) val >>= OCOTP_CFG3_SPEED_SHIFT; val &= 0x3; - if (is_mx6ul() || is_mx6ull()) { + if (is_mx6ul()) { if (val == OCOTP_CFG3_SPEED_528MHZ) return 528000000; else if (val == OCOTP_CFG3_SPEED_696MHZ) @@ -135,6 +141,17 @@ u32 get_cpu_speed_grade_hz(void) return 0; } + if (is_mx6ull()) { + if (val == OCOTP_CFG3_SPEED_528MHZ) + return 528000000; + else if (val == OCOTP_CFG3_SPEED_792MHZ) + return 792000000; + else if (val == OCOTP_CFG3_SPEED_900MHZ) + return 900000000; + else + return 0; + } + switch (val) { /* Valid for IMX6DQ */ case OCOTP_CFG3_SPEED_1P2GHZ: -- cgit v1.2.1 From 91435cd40d3060d74fe59a7847b666cd24eecf78 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 8 Aug 2017 13:34:51 +0800 Subject: ARM: i.MX6: exclude the ARM errata from i.MX6 UP system The ARM errata 751472, 794072, 761320 only applied to the following configuration: This erratum affects configurations with either: - One processor if the ACP is present - Two or more processors i.MX6 family does not have the ACP and thus only the MPCore system will be impacted, which are the i.MX6DQ, i.MX6DL, and i.MX6QP. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam --- arch/arm/mach-imx/mx6/Kconfig | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-imx/mx6') diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 3ffdea20a1..40f3e64814 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -1,24 +1,31 @@ if ARCH_MX6 +config MX6_SMP + select ARM_ERRATA_751472 + select ARM_ERRATA_761320 + select ARM_ERRATA_794072 + bool + config MX6 + select ARM_ERRATA_743622 if !MX6UL bool default y - select ARM_ERRATA_743622 if !MX6UL - select ARM_ERRATA_751472 if !MX6UL - select ARM_ERRATA_761320 if !MX6UL - select ARM_ERRATA_794072 if !MX6UL imply CMD_FUSE config MX6D + select MX6_SMP bool config MX6DL + select MX6_SMP bool config MX6Q + select MX6_SMP bool config MX6QDL + select MX6_SMP bool config MX6S -- cgit v1.2.1 From 3d3598d0f62570e26bc206e1a9b0ceafe00343e1 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 8 Aug 2017 13:34:53 +0800 Subject: imx: mx6: select ARM_ERRATA_845369 Select ARM_ERRATA_845369 for i.MX6DQ/DL/QP. Signed-off-by: Peng Fan Reviewed-by: Stefano Babic --- arch/arm/mach-imx/mx6/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mach-imx/mx6') diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 40f3e64814..d1990602f8 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -4,6 +4,7 @@ config MX6_SMP select ARM_ERRATA_751472 select ARM_ERRATA_761320 select ARM_ERRATA_794072 + select ARM_ERRATA_845369 bool config MX6 -- cgit v1.2.1 From 79a57b5ae158e4d561b016e4e0aeef03c2d1d457 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 8 Aug 2017 16:21:35 +0800 Subject: imx: mx6: soc: fix mx6sll settings There is not LDO_SOC/PU/ARM/MMDC1 on i.MX6SLL, also no need to gate/ungate all PFDs to make PFD working. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam --- arch/arm/mach-imx/mx6/soc.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-imx/mx6') diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index c15b9cb8e2..e87a21513e 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -251,6 +251,10 @@ static int set_ldo_voltage(enum ldo_reg ldo, u32 mv) u32 val, step, old, reg = readl(&anatop->reg_core); u8 shift; + /* No LDO_SOC/PU/ARM */ + if (is_mx6sll()) + return 0; + if (mv < 725) val = 0x00; /* Power gated off */ else if (mv > 1450) @@ -310,7 +314,7 @@ static void clear_mmdc_ch_mask(void) reg = readl(&mxc_ccm->ccdr); /* Clear MMDC channel mask */ - if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) + if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll()) reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); else reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); @@ -512,6 +516,10 @@ uint mmc_get_env_part(struct mmc *mmc) int board_postclk_init(void) { + /* NO LDO SOC on i.MX6SLL */ + if (is_mx6sll()) + return 0; + set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */ return 0; @@ -593,7 +601,7 @@ void s_init(void) u32 mask528; u32 reg, periph1, periph2; - if (is_mx6sx() || is_mx6ul() || is_mx6ull()) + if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll()) return; /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs -- cgit v1.2.1 From 7236297aee8c0ef1b2e6c806725486b24ef16dc1 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 8 Aug 2017 16:21:38 +0800 Subject: imx: mx6sx: select OSC as uart's clk parent As M4 is sourcing UART clk from OSC, to make UART work when M4 is enabled, need to select OSC as clk parent, 24M OSC is enough for debug UART in uboot. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam --- arch/arm/mach-imx/mx6/soc.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/mach-imx/mx6') diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index e87a21513e..48eaa84921 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -379,6 +379,8 @@ static void set_preclk_from_osc(void) int arch_cpu_init(void) { + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + init_aips(); /* Need to clear MMDC_CHx_MASK to make warm reset work. */ @@ -448,6 +450,9 @@ int arch_cpu_init(void) imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ + if (is_mx6sx()) + setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL); + init_src(); return 0; -- cgit v1.2.1 From 9402cafb2398bbb3ecba356c692ec9cb89b59d60 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 8 Aug 2017 16:21:39 +0800 Subject: imx: mx6sl: simplify code using setbits_le32 Simplify code by removing set_preclk_from_osc with directly setbits_le32. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam --- arch/arm/mach-imx/mx6/soc.c | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) (limited to 'arch/arm/mach-imx/mx6') diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index 48eaa84921..9ede1f5435 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -365,18 +365,6 @@ static void init_bandgap(void) } } -#ifdef CONFIG_MX6SL -static void set_preclk_from_osc(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - u32 reg; - - reg = readl(&mxc_ccm->cscmr1); - reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK; - writel(reg, &mxc_ccm->cscmr1); -} -#endif - int arch_cpu_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -444,9 +432,8 @@ int arch_cpu_init(void) } /* Set perclk to source from OSC 24MHz */ -#if defined(CONFIG_MX6SL) - set_preclk_from_osc(); -#endif + if (is_mx6sl()) + setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK); imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ -- cgit v1.2.1