From e4fce34e7a5f484de2ca557fd43a198fd14894b7 Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Mon, 21 Nov 2011 23:34:01 +0000 Subject: start.S: remove omap3 specific code from start.S Cc: Tom Rini Cc: Albert Aribaud Signed-off-by: Aneesh V Acked-by: Tom Rini --- arch/arm/include/asm/arch-omap3/omap3.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include/asm/arch-omap3') diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h index 02eb865dc1..2b5e9aeae1 100644 --- a/arch/arm/include/asm/arch-omap3/omap3.h +++ b/arch/arm/include/asm/arch-omap3/omap3.h @@ -153,6 +153,7 @@ struct gpio { #define SRAM_OFFSET2 0x0000F800 #define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \ SRAM_OFFSET2) +#define SRAM_CLK_CODE (SRAM_VECT_CODE + 64) #define OMAP3_PUBLIC_SRAM_BASE 0x40208000 /* Works for GP & EMU */ #define OMAP3_PUBLIC_SRAM_END 0x40210000 -- cgit v1.2.1 From b9e65a797bea224c786e3dcd936a9ffc08d24aef Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 28 Nov 2011 06:37:35 +0000 Subject: AM35xx: add EMAC support AM35xx has DaVinci-compatible EMAC. Signed-off-by: Ilya Yanok --- arch/arm/include/asm/arch-omap3/am35x_def.h | 3 ++ arch/arm/include/asm/arch-omap3/emac_defs.h | 56 +++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) create mode 100644 arch/arm/include/asm/arch-omap3/emac_defs.h (limited to 'arch/arm/include/asm/arch-omap3') diff --git a/arch/arm/include/asm/arch-omap3/am35x_def.h b/arch/arm/include/asm/arch-omap3/am35x_def.h index 81942a8063..bbaf1bc97b 100644 --- a/arch/arm/include/asm/arch-omap3/am35x_def.h +++ b/arch/arm/include/asm/arch-omap3/am35x_def.h @@ -32,6 +32,9 @@ #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ +/* IP_SW_RESET bits */ +#define CPGMACSS_SW_RST (1 << 1) /* reset CPGMAC */ + /* General register mappings of system control module */ #define AM35X_SCM_GEN_BASE 0x48002270 struct am35x_scm_general { diff --git a/arch/arm/include/asm/arch-omap3/emac_defs.h b/arch/arm/include/asm/arch-omap3/emac_defs.h new file mode 100644 index 0000000000..8506c555d5 --- /dev/null +++ b/arch/arm/include/asm/arch-omap3/emac_defs.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Based on: + * + * ---------------------------------------------------------------------------- + * + * dm644x_emac.h + * + * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM + * + * Copyright (C) 2005 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + + * Modifications: + * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot. + * + */ + +#ifndef _AM3517_EMAC_H_ +#define _AM3517_EMAC_H_ + +#define EMAC_BASE_ADDR 0x5C010000 +#define EMAC_WRAPPER_BASE_ADDR 0x5C000000 +#define EMAC_WRAPPER_RAM_ADDR 0x5C020000 +#define EMAC_MDIO_BASE_ADDR 0x5C030000 +#define EMAC_HW_RAM_ADDR 0x01E20000 + +#define EMAC_MDIO_BUS_FREQ 166000000 /* 166 MHZ check */ +#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 2.0 MHz */ + +/* SOFTRESET macro definition interferes with emac_regs structure definition */ +#undef SOFTRESET + +typedef volatile unsigned int dv_reg; +typedef volatile unsigned int *dv_reg_p; + +#define DAVINCI_EMAC_VERSION2 + +#endif /* _AM3517_EMAC_H_ */ -- cgit v1.2.1 From ad2a7909a1430321224ea25c808494b4df8d1140 Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 28 Nov 2011 06:37:36 +0000 Subject: AM3517: move AM3517 specific mux defines to generic header AM3517 specific CONTROL_PADCONF_* defines moved from board-specific files to Signed-off-by: Ilya Yanok --- arch/arm/include/asm/arch-omap3/mux.h | 41 +++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'arch/arm/include/asm/arch-omap3') diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h index 0c01c73165..6daef49e97 100644 --- a/arch/arm/include/asm/arch-omap3/mux.h +++ b/arch/arm/include/asm/arch-omap3/mux.h @@ -404,6 +404,47 @@ #define CONTROL_PADCONF_SDRC_CKE0 0x0262 #define CONTROL_PADCONF_SDRC_CKE1 0x0264 +/* AM3517 specific mux configuration */ +#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 +/* CCDC */ +#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 +#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 +#define CONTROL_PADCONF_CCDC_HD 0x01E8 +#define CONTROL_PADCONF_CCDC_VD 0x01EA +#define CONTROL_PADCONF_CCDC_WEN 0x01EC +#define CONTROL_PADCONF_CCDC_DATA0 0x01EE +#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 +#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 +#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 +#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 +#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 +#define CONTROL_PADCONF_CCDC_DATA6 0x01FA +#define CONTROL_PADCONF_CCDC_DATA7 0x01FC +/* RMII */ +#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE +#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 +#define CONTROL_PADCONF_RMII_RXD0 0x0202 +#define CONTROL_PADCONF_RMII_RXD1 0x0204 +#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 +#define CONTROL_PADCONF_RMII_RXER 0x0208 +#define CONTROL_PADCONF_RMII_TXD0 0x020A +#define CONTROL_PADCONF_RMII_TXD1 0x020C +#define CONTROL_PADCONF_RMII_TXEN 0x020E +#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 +#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 +/* CAN */ +#define CONTROL_PADCONF_HECC1_TXD 0x0214 +#define CONTROL_PADCONF_HECC1_RXD 0x0216 + +#define CONTROL_PADCONF_SYS_BOOT7 0x0218 +#define CONTROL_PADCONF_SDRC_DQS0N 0x021A +#define CONTROL_PADCONF_SDRC_DQS1N 0x021C +#define CONTROL_PADCONF_SDRC_DQS2N 0x021E +#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 +#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 +#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 +#define CONTROL_PADCONF_SYS_BOOT8 0x0226 + #define MUX_VAL(OFFSET,VALUE)\ writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); -- cgit v1.2.1 From b7eb9e7895bf481d979d58d5d7a53033c3ad9a8f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:47:58 +0000 Subject: omap3: mem: Comment enable_gpmc_cs_config more Expand the "enable the config" comment to explain what the bit shifts are and define out two of the magic numbers. Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-omap3/mem.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/include/asm/arch-omap3') diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index db6a696f49..abf4e82a39 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -259,6 +259,10 @@ enum { #define GPMC_SIZE_32M 0xE #define GPMC_SIZE_16M 0xF +#define GPMC_BASEADDR_MASK 0x3F + +#define GPMC_CS_ENABLE 0x1 + #define SMNAND_GPMC_CONFIG1 0x00000800 #define SMNAND_GPMC_CONFIG2 0x00141400 #define SMNAND_GPMC_CONFIG3 0x00141400 -- cgit v1.2.1 From 50e7ff0369fc2720eb72feb50cce41d54dd1b2d8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:48:02 +0000 Subject: OMAP3: Remove get_mem_type prototype This function doesn't exist for omap3 Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-omap3/sys_proto.h | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/include/asm/arch-omap3') diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 995e7cb57e..9e644103ee 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -49,7 +49,6 @@ void set_muxconf_regs(void); u32 get_cpu_family(void); u32 get_cpu_rev(void); u32 get_sku_id(void); -u32 get_mem_type(void); u32 get_sysboot_value(void); u32 is_gpmc_muxed(void); u32 get_gpmc0_type(void); -- cgit v1.2.1 From 14ca3dee80718b5f8fd06e39e78a4e7757826bbf Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:48:03 +0000 Subject: omap3: mem: Add MCFG helper macro This adds an MCFG macro to calculate the correct value, similar to the ACTIMA/ACTIMB macros and adds a comment that all of the potential values here are documented in the TRM. Then we convert the Micron value to use this macro. Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-omap3/mem.h | 46 +++++++++++++++++++++++------------ 1 file changed, 30 insertions(+), 16 deletions(-) (limited to 'arch/arm/include/asm/arch-omap3') diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index abf4e82a39..12ff3b0831 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -39,6 +39,12 @@ enum { #define EARLY_INIT 1 +/* + * For a full explanation of these registers and values please see + * the Technical Reference Manual (TRM) for any of the processors in + * this family. + */ + /* Slower full frequency range default timings for x32 operation*/ #define SDRC_SHARING 0x00000100 #define SDRC_MR_0_SDR 0x00000031 @@ -86,6 +92,27 @@ enum { ACTIM_CTRLB_TXP(b) | \ ACTIM_CTRLB_TXSR(d) +/* + * Values used in the MCFG register. Only values we use today + * are defined and the rest can be found in the TRM. Unless otherwise + * noted all fields are one bit. + */ +#define V_MCFG_RAMTYPE_DDR (0x1) +#define V_MCFG_DEEPPD_EN (0x1 << 3) +#define V_MCFG_B32NOT16_32 (0x1 << 4) +#define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */ +#define V_MCFG_RAMSIZE(a) ((((a)/(1024*1024))/2) << 8) /* 8:17 */ +#define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19) +#define V_MCFG_CASWIDTH_10B (0x5 << 20) /* 20:22 */ +#define V_MCFG_RASWIDTH(a) ((a) << 24) /* 24:26 */ + +/* Macro to construct MCFG */ +#define MCFG(a, b) \ + V_MCFG_RASWIDTH(b) | V_MCFG_CASWIDTH_10B | \ + V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(a) | \ + V_MCFG_BANKALLOCATION_RBC | \ + V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR + /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */ #define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */ /* 15/6 + 18/6 = 5.5 -> 6 */ @@ -138,21 +165,8 @@ enum { ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \ MICRON_TXP_165, MICRON_XSR_165) -#define MICRON_RAMTYPE 0x1 -#define MICRON_DDRTYPE 0x0 -#define MICRON_DEEPPD 0x1 -#define MICRON_B32NOT16 0x1 -#define MICRON_BANKALLOCATION 0x2 -#define MICRON_RAMSIZE ((PHYS_SDRAM_1_SIZE/(1024*1024))/2) -#define MICRON_ADDRMUXLEGACY 0x1 -#define MICRON_CASWIDTH 0x5 -#define MICRON_RASWIDTH 0x2 -#define MICRON_LOCKSTATUS 0x0 -#define MICRON_V_MCFG ((MICRON_LOCKSTATUS << 30) | (MICRON_RASWIDTH << 24) | \ - (MICRON_CASWIDTH << 20) | (MICRON_ADDRMUXLEGACY << 19) | \ - (MICRON_RAMSIZE << 8) | (MICRON_BANKALLOCATION << 6) | \ - (MICRON_B32NOT16 << 4) | (MICRON_DEEPPD << 3) | \ - (MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE)) +#define MICRON_RASWIDTH 0x2 +#define MICRON_V_MCFG(size) MCFG((size), MICRON_RASWIDTH) #define MICRON_ARCV 2030 #define MICRON_ARE 0x1 @@ -199,7 +213,7 @@ enum { #ifdef CONFIG_OMAP3_MICRON_DDR #define V_ACTIMA_165 MICRON_V_ACTIMA_165 #define V_ACTIMB_165 MICRON_V_ACTIMB_165 -#define V_MCFG MICRON_V_MCFG +#define V_MCFG MICRON_V_MCFG(PHYS_SDRAM_1_SIZE) #define V_RFR_CTRL MICRON_V_RFR_CTRL #define V_MR MICRON_V_MR #endif -- cgit v1.2.1 From 1be1433b834aaf7aef7c92275f92d4729f6bd62e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:48:04 +0000 Subject: OMAP3: Add optimal SDRC autorefresh control values This adds the optimal SDRC autorefresh control register values for 100Mhz, 133MHz, 165MHz and 200MHz clocks. We switch to using this to provide the default 165MHz value. Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-omap3/mem.h | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) (limited to 'arch/arm/include/asm/arch-omap3') diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 12ff3b0831..912c73765f 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -49,6 +49,16 @@ enum { #define SDRC_SHARING 0x00000100 #define SDRC_MR_0_SDR 0x00000031 +/* + * SDRC autorefresh control values. This register consists of autorefresh + * enable at bits 0:1 and an autorefresh counter value in bits 8:23. The + * counter is a result of ( tREFI / tCK ) - 50. + */ +#define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01 +#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */ +#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ +#define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */ + #define DLL_OFFSET 0 #define DLL_WRITEDDRCLKX2DIS 1 #define DLL_ENADLL 1 @@ -168,10 +178,6 @@ enum { #define MICRON_RASWIDTH 0x2 #define MICRON_V_MCFG(size) MCFG((size), MICRON_RASWIDTH) -#define MICRON_ARCV 2030 -#define MICRON_ARE 0x1 -#define MICRON_V_RFR_CTRL ((MICRON_ARCV << 8) | (MICRON_ARE)) - #define MICRON_BL 0x2 #define MICRON_SIL 0x0 #define MICRON_CASL 0x3 @@ -214,7 +220,7 @@ enum { #define V_ACTIMA_165 MICRON_V_ACTIMA_165 #define V_ACTIMB_165 MICRON_V_ACTIMB_165 #define V_MCFG MICRON_V_MCFG(PHYS_SDRAM_1_SIZE) -#define V_RFR_CTRL MICRON_V_RFR_CTRL +#define V_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz #define V_MR MICRON_V_MR #endif -- cgit v1.2.1 From fc41ba1e2b4271bef197bfbf89d49458368319ce Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:48:05 +0000 Subject: OMAP3: Suffix all Micron memory timing parts with their speed Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-omap3/mem.h | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) (limited to 'arch/arm/include/asm/arch-omap3') diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 912c73765f..4f996d9eb3 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -175,15 +175,16 @@ enum { ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \ MICRON_TXP_165, MICRON_XSR_165) -#define MICRON_RASWIDTH 0x2 -#define MICRON_V_MCFG(size) MCFG((size), MICRON_RASWIDTH) +#define MICRON_RASWIDTH_165 0x2 +#define MICRON_V_MCFG_165(size) MCFG((size), MICRON_RASWIDTH_165) -#define MICRON_BL 0x2 -#define MICRON_SIL 0x0 -#define MICRON_CASL 0x3 -#define MICRON_WBST 0x0 -#define MICRON_V_MR ((MICRON_WBST << 9) | (MICRON_CASL << 4) | \ - (MICRON_SIL << 3) | (MICRON_BL)) +#define MICRON_BL_165 0x2 +#define MICRON_SIL_165 0x0 +#define MICRON_CASL_165 0x3 +#define MICRON_WBST_165 0x0 +#define MICRON_V_MR_165 ((MICRON_WBST_165 << 9) | \ + (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \ + (MICRON_BL_165)) /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */ #define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */ @@ -219,9 +220,9 @@ enum { #ifdef CONFIG_OMAP3_MICRON_DDR #define V_ACTIMA_165 MICRON_V_ACTIMA_165 #define V_ACTIMB_165 MICRON_V_ACTIMB_165 -#define V_MCFG MICRON_V_MCFG(PHYS_SDRAM_1_SIZE) +#define V_MCFG MICRON_V_MCFG_165(PHYS_SDRAM_1_SIZE) #define V_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz -#define V_MR MICRON_V_MR +#define V_MR MICRON_V_MR_165 #endif #ifdef CONFIG_OMAP3_NUMONYX_DDR -- cgit v1.2.1 From 9ae0d550741db45e933dc73e7135d1861e3a9b62 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:48:06 +0000 Subject: OMAP3 SPL: Rework memory initalization and devkit8000 support This changes to making the board be responsible for providing the memory initialization timings in SPL and converts the devkit8000 to this framework. In SPL we try and initialize both CS0 and CS1. Cc: Frederik Kriewitz Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-omap3/mem.h | 26 -------------------------- arch/arm/include/asm/arch-omap3/sys_proto.h | 2 ++ 2 files changed, 2 insertions(+), 26 deletions(-) (limited to 'arch/arm/include/asm/arch-omap3') diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 4f996d9eb3..09f5872389 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -212,32 +212,6 @@ enum { ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \ NUMONYX_TXP_165, NUMONYX_XSR_165) -#ifdef CONFIG_OMAP3_INFINEON_DDR -#define V_ACTIMA_165 INFINEON_V_ACTIMA_165 -#define V_ACTIMB_165 INFINEON_V_ACTIMB_165 -#endif - -#ifdef CONFIG_OMAP3_MICRON_DDR -#define V_ACTIMA_165 MICRON_V_ACTIMA_165 -#define V_ACTIMB_165 MICRON_V_ACTIMB_165 -#define V_MCFG MICRON_V_MCFG_165(PHYS_SDRAM_1_SIZE) -#define V_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz -#define V_MR MICRON_V_MR_165 -#endif - -#ifdef CONFIG_OMAP3_NUMONYX_DDR -#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165 -#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165 -#endif - -#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165) -#error "Please choose the right DDR type in config header" -#endif - -#if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL)) -#error "Please choose the right DDR type in config header" -#endif - /* * GPMC settings - * Definitions is as per the following format diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 9e644103ee..80e167b0c9 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -38,6 +38,8 @@ void per_clocks_enable(void); void memif_init(void); void sdrc_init(void); void do_sdrc_init(u32, u32); +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr); void emif4_init(void); void gpmc_init(void); void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, -- cgit v1.2.1 From 4e647e12074c11a5bcfc5291c44c3b52531795fa Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:48:07 +0000 Subject: OMAP3 SPL: Add identify_nand_chip function A number of boards are populated with a PoP chip for both DDR and NAND memory. Other boards may simply use this as an easy way to identify board revs. So we provide a function that can be called early to reset the NAND chip and return the result of NAND_CMD_READID. All of this code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND. Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-omap3/sys_proto.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include/asm/arch-omap3') diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 80e167b0c9..e5031d5022 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -40,6 +40,7 @@ void sdrc_init(void); void do_sdrc_init(u32, u32); void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, u32 *mr); +void identify_nand_chip(int *mfr, int *id); void emif4_init(void); void gpmc_init(void); void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, -- cgit v1.2.1 From 75c57a3570ec0904c14394db08ef436a8b49dda4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:48:08 +0000 Subject: OMAP3: Add SPL support to Beagleboard This introduces 200MHz Micron parts timing information based on x-loader to and Numonyx MCFG calculation. The memory init logic is also based on what x-loader does in these cases. Note that while previously u-boot would be flashed in with SW ECC in this case it now must be flashed with HW ECC. We also change CONFIG_SYS_TEXT_BASE to 0x80100000. Cc: Dirk Behme Beagleboard rev C5, xM rev A: Tested-by: Tom Rini Beagleboard xM rev C: Tested-by: Matt Ranostay Beagleboard rev B7, C2, xM rev B: Tested-by: Matt Porter Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-omap3/mem.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm/include/asm/arch-omap3') diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 09f5872389..4ea5f74f48 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -186,6 +186,32 @@ enum { (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \ (MICRON_BL_165)) +/* Micron part (200MHz optimized) 5 ns */ +#define MICRON_TDAL_200 6 +#define MICRON_TDPL_200 3 +#define MICRON_TRRD_200 2 +#define MICRON_TRCD_200 3 +#define MICRON_TRP_200 3 +#define MICRON_TRAS_200 8 +#define MICRON_TRC_200 11 +#define MICRON_TRFC_200 15 +#define MICRON_V_ACTIMA_200 \ + ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200, \ + MICRON_TRAS_200, MICRON_TRP_200, \ + MICRON_TRCD_200, MICRON_TRRD_200, \ + MICRON_TDPL_200, MICRON_TDAL_200) + +#define MICRON_TWTR_200 2 +#define MICRON_TCKE_200 4 +#define MICRON_TXP_200 2 +#define MICRON_XSR_200 23 +#define MICRON_V_ACTIMB_200 \ + ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200, \ + MICRON_TXP_200, MICRON_XSR_200) + +#define MICRON_RASWIDTH_200 0x3 +#define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200) + /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */ #define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */ /* 15/6 + 18/6 = 5.5 -> 6 */ @@ -212,6 +238,9 @@ enum { ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \ NUMONYX_TXP_165, NUMONYX_XSR_165) +#define NUMONYX_RASWIDTH_165 0x4 +#define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165) + /* * GPMC settings - * Definitions is as per the following format -- cgit v1.2.1 From 673283f3fc2583a56b3be995cd341159428734ba Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Nov 2011 12:48:09 +0000 Subject: OMAP3: Add SPL support to omap3_evm Add Hynix 200MHz timing information to . This also changes CONFIG_SYS_TEXT_BASE to 0x80100000. Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-omap3/mem.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm/include/asm/arch-omap3') diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 4ea5f74f48..5fd02d4dfc 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -123,6 +123,32 @@ enum { V_MCFG_BANKALLOCATION_RBC | \ V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR +/* Hynix part of AM/DM37xEVM (200MHz optimized) */ +#define HYNIX_TDAL_200 6 +#define HYNIX_TDPL_200 3 +#define HYNIX_TRRD_200 2 +#define HYNIX_TRCD_200 4 +#define HYNIX_TRP_200 3 +#define HYNIX_TRAS_200 8 +#define HYNIX_TRC_200 11 +#define HYNIX_TRFC_200 18 +#define HYNIX_V_ACTIMA_200 \ + ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \ + HYNIX_TRAS_200, HYNIX_TRP_200, \ + HYNIX_TRCD_200, HYNIX_TRRD_200, \ + HYNIX_TDPL_200, HYNIX_TDAL_200) + +#define HYNIX_TWTR_200 2 +#define HYNIX_TCKE_200 1 +#define HYNIX_TXP_200 1 +#define HYNIX_XSR_200 28 +#define HYNIX_V_ACTIMB_200 \ + ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \ + HYNIX_TXP_200, HYNIX_XSR_200) + +#define HYNIX_RASWIDTH_200 0x3 +#define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200) + /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */ #define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */ /* 15/6 + 18/6 = 5.5 -> 6 */ -- cgit v1.2.1