From 8f5d468721ef3931e4c6f9c6555348f26acdec19 Mon Sep 17 00:00:00 2001 From: "Hadli, Manjunath" Date: Mon, 6 Feb 2012 00:30:44 +0000 Subject: davinci: add support for printing clock frequency add support for printing various clock frequency info found in SOC such as ARM core frequency, DSP core frequency and DDR frequency as part of bdinfo command. Signed-off-by: Manjunath Hadli Cc: Tom Rini --- arch/arm/cpu/arm926ejs/davinci/cpu.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm/cpu/arm926ejs') diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c index 1735555226..b3c9fb7b69 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c @@ -25,6 +25,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + /* offsets from PLL controller base */ #define PLLC_PLLCTL 0x100 #define PLLC_PLLM 0x110 @@ -187,6 +189,36 @@ unsigned int davinci_clk_get(unsigned int div) #endif #endif /* !CONFIG_SOC_DA8XX */ +int set_cpu_clk_info(void) +{ +#ifdef CONFIG_SOC_DA8XX + gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; + /* DDR PHY uses an x2 input clock */ + gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000; +#else + + unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE; +#if defined(CONFIG_SOC_DM365) + pllbase = DAVINCI_PLL_CNTRL1_BASE; +#endif + gd->bd->bi_arm_freq = pll_sysclk_mhz(pllbase, ARM_PLLDIV); + +#ifdef DSP_PLLDIV + gd->bd->bi_dsp_freq = + pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV); +#else + gd->bd->bi_dsp_freq = 0; +#endif + + pllbase = DAVINCI_PLL_CNTRL1_BASE; +#if defined(CONFIG_SOC_DM365) + pllbase = DAVINCI_PLL_CNTRL0_BASE; +#endif + gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2; +#endif + return 0; +} + /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() -- cgit v1.2.1