From 942ecc8bd81a7802fc3b82057da6a146909c0016 Mon Sep 17 00:00:00 2001 From: Sriram Dash Date: Tue, 6 Feb 2018 11:26:30 +0530 Subject: drivers: i2c: mxc: Update SYS_I2C_MXC_I2C support in Kconfig NXP layerscape platforms like ls1088a, ls2088a uses MXC I2C Controller. -Remove dependency of MX6 for the same. Update related configs to use Kconfig file. -Add SYS_I2C_MXC_I2C1,_I2C2,_I2C3,_I2C4 in Kconfig -Add CONFIG_SYS_MXC_I2C1_SPEED,_I2C2_,_I2C3_,_I2C4_ in Kconfig -Add CONFIG_SYS_MXC_I2C1_SLAVE,_I2C2_,_I2C3_,_I2C4_ in Kconfig Signed-off-by: Sriram Dash Signed-off-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 23 ++++++++ drivers/i2c/Kconfig | 89 +++++++++++++++++++++++++++++-- include/configs/ls1012a_common.h | 3 -- include/configs/ls1043a_common.h | 5 -- include/configs/ls1046a_common.h | 5 -- include/configs/ls1088a_common.h | 5 -- include/configs/ls2080a_common.h | 5 -- include/configs/ls2080a_emu.h | 3 -- include/configs/ls2080a_simu.h | 3 -- 9 files changed, 109 insertions(+), 32 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 7b59dc9a7c..c4a96d48ba 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -14,6 +14,9 @@ config ARCH_LS1012A select SYS_FSL_ERRATUM_A009008 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 imply PANIC_HANG config ARCH_LS1043A @@ -41,6 +44,11 @@ config ARCH_LS1043A select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 imply SCSI imply SCSI_AHCI imply CMD_PCI @@ -70,6 +78,11 @@ config ARCH_LS1046A select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 imply SCSI imply SCSI_AHCI @@ -102,6 +115,11 @@ config ARCH_LS1088A select FSL_TZASC_1 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 imply SCSI imply PANIC_HANG @@ -144,6 +162,11 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A009203 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 imply PANIC_HANG config FSL_LSCH2 diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 932abd3059..cc9fa96ac5 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -149,13 +149,96 @@ config SYS_I2C_MESON both 7-bit and 10-bit addresses. config SYS_I2C_MXC - bool "NXP i.MX I2C driver" - depends on MX6 + bool "NXP MXC I2C driver" help - Add support for the NXP i.MX I2C driver. This supports upto for bus + Add support for the NXP I2C driver. This supports upto for bus channels and operating on standard mode upto 100 kbits/s and fast mode upto 400 kbits/s. +if SYS_I2C_MXC +config SYS_I2C_MXC_I2C1 + bool "NXP MXC I2C1" + help + Add support for NXP MXC I2C Controller 1. + Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A + +config SYS_I2C_MXC_I2C2 + bool "NXP MXC I2C2" + help + Add support for NXP MXC I2C Controller 2. + Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A + +config SYS_I2C_MXC_I2C3 + bool "NXP MXC I2C3" + help + Add support for NXP MXC I2C Controller 3. + Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A + +config SYS_I2C_MXC_I2C4 + bool "NXP MXC I2C4" + help + Add support for NXP MXC I2C Controller 4. + Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A +endif + +if SYS_I2C_MXC_I2C1 +config SYS_MXC_I2C1_SPEED + int "I2C Channel 1 speed" + default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU + default 100000 + help + MXC I2C Channel 1 speed + +config SYS_MXC_I2C1_SLAVE + int "I2C1 Slave" + default 0 + help + MXC I2C1 Slave +endif + +if SYS_I2C_MXC_I2C2 +config SYS_MXC_I2C2_SPEED + int "I2C Channel 2 speed" + default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU + default 100000 + help + MXC I2C Channel 2 speed + +config SYS_MXC_I2C2_SLAVE + int "I2C2 Slave" + default 0 + help + MXC I2C2 Slave +endif + +if SYS_I2C_MXC_I2C3 +config SYS_MXC_I2C3_SPEED + int "I2C Channel 3 speed" + default 100000 + help + MXC I2C Channel 3 speed + +config SYS_MXC_I2C3_SLAVE + int "I2C3 Slave" + default 0 + help + MXC I2C3 Slave +endif + +if SYS_I2C_MXC_I2C4 +config SYS_MXC_I2C4_SPEED + int "I2C Channel 4 speed" + default 100000 + help + MXC I2C Channel 4 speed + +config SYS_MXC_I2C4_SLAVE + int "I2C4 Slave" + default 0 + help + MXC I2C4 Slave +endif + config SYS_I2C_OMAP24XX bool "TI OMAP2+ I2C driver" depends on ARCH_OMAP2PLUS diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 46b3566adf..73cd049f28 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -77,9 +77,6 @@ /* I2C */ #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 4c96186289..9e1b81a564 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -148,11 +148,6 @@ /* I2C */ #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 -#define CONFIG_SYS_I2C_MXC_I2C2 -#define CONFIG_SYS_I2C_MXC_I2C3 -#define CONFIG_SYS_I2C_MXC_I2C4 /* PCIe */ #ifndef SPL_NO_PCIE diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index b5af4b053b..2494d9dc94 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -126,11 +126,6 @@ /* I2C */ #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 -#define CONFIG_SYS_I2C_MXC_I2C2 -#define CONFIG_SYS_I2C_MXC_I2C3 -#define CONFIG_SYS_I2C_MXC_I2C4 /* PCIe */ #define CONFIG_PCIE1 /* PCIE controller 1 */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index a3a393e472..393ce4ff9d 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -67,11 +67,6 @@ /* I2C */ #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index edf954dadd..3e05b2788a 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -77,11 +77,6 @@ /* I2C */ #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 diff --git a/include/configs/ls2080a_emu.h b/include/configs/ls2080a_emu.h index 6b34edfbf1..c2fdc4daf6 100644 --- a/include/configs/ls2080a_emu.h +++ b/include/configs/ls2080a_emu.h @@ -12,9 +12,6 @@ #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 133333333 -#define CONFIG_SYS_MXC_I2C1_SPEED 40000000 -#define CONFIG_SYS_MXC_I2C2_SPEED 40000000 - #define CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */ #define SPD_EEPROM_ADDRESS1 0x51 diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h index dad1090f84..103ebec79e 100644 --- a/include/configs/ls2080a_simu.h +++ b/include/configs/ls2080a_simu.h @@ -12,9 +12,6 @@ #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 133333333 -#define CONFIG_SYS_MXC_I2C1_SPEED 40000000 -#define CONFIG_SYS_MXC_I2C2_SPEED 40000000 - #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR -- cgit v1.2.1 From fa452192cbebf127234bdd537044e3fc581dccc4 Mon Sep 17 00:00:00 2001 From: Sriram Dash Date: Tue, 6 Feb 2018 11:26:31 +0530 Subject: drivers: i2c: mxc: Update support to 8 I2C controllers Existing driver supports upto 4 I2C controllers. But some of future NXPs SoCs like lx2160a has eight I2C controllers. Update MXC driver to support upto 8 I2C controllers Signed-off-by: Sriram Dash Signed-off-by: Priyanka Jain --- drivers/i2c/Kconfig | 80 +++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/i2c/mxc_i2c.c | 56 ++++++++++++++++++++++++++++++++++++ 2 files changed, 136 insertions(+) diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index cc9fa96ac5..286ae487ca 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -179,6 +179,30 @@ config SYS_I2C_MXC_I2C4 help Add support for NXP MXC I2C Controller 4. Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A + +config SYS_I2C_MXC_I2C5 + bool "NXP MXC I2C5" + help + Add support for NXP MXC I2C Controller 5. + Required for SoCs which have I2C MXC controller 5 eg LX2160A + +config SYS_I2C_MXC_I2C6 + bool "NXP MXC I2C6" + help + Add support for NXP MXC I2C Controller 6. + Required for SoCs which have I2C MXC controller 6 eg LX2160A + +config SYS_I2C_MXC_I2C7 + bool "NXP MXC I2C7" + help + Add support for NXP MXC I2C Controller 7. + Required for SoCs which have I2C MXC controller 7 eg LX2160A + +config SYS_I2C_MXC_I2C8 + bool "NXP MXC I2C8" + help + Add support for NXP MXC I2C Controller 8. + Required for SoCs which have I2C MXC controller 8 eg LX2160A endif if SYS_I2C_MXC_I2C1 @@ -239,6 +263,62 @@ config SYS_MXC_I2C4_SLAVE MXC I2C4 Slave endif +if SYS_I2C_MXC_I2C5 +config SYS_MXC_I2C5_SPEED + int "I2C Channel 5 speed" + default 100000 + help + MXC I2C Channel 5 speed + +config SYS_MXC_I2C5_SLAVE + int "I2C5 Slave" + default 0 + help + MXC I2C5 Slave +endif + +if SYS_I2C_MXC_I2C6 +config SYS_MXC_I2C6_SPEED + int "I2C Channel 6 speed" + default 100000 + help + MXC I2C Channel 6 speed + +config SYS_MXC_I2C6_SLAVE + int "I2C6 Slave" + default 0 + help + MXC I2C6 Slave +endif + +if SYS_I2C_MXC_I2C7 +config SYS_MXC_I2C7_SPEED + int "I2C Channel 7 speed" + default 100000 + help + MXC I2C Channel 7 speed + +config SYS_MXC_I2C7_SLAVE + int "I2C7 Slave" + default 0 + help + MXC I2C7 Slave +endif + +if SYS_I2C_MXC_I2C8 +config SYS_MXC_I2C8_SPEED + int "I2C Channel 8 speed" + default 100000 + help + MXC I2C Channel 8 speed + +config SYS_MXC_I2C8_SLAVE + int "I2C8 Slave" + default 0 + help + MXC I2C8 Slave +endif + config SYS_I2C_OMAP24XX bool "TI OMAP2+ I2C driver" depends on ARCH_OMAP2PLUS diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 79228c2757..a17c1eceae 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -589,6 +589,22 @@ static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr, #define I2C4_BASE_ADDR 0 #endif +#if !defined(I2C5_BASE_ADDR) +#define I2C5_BASE_ADDR 0 +#endif + +#if !defined(I2C6_BASE_ADDR) +#define I2C6_BASE_ADDR 0 +#endif + +#if !defined(I2C7_BASE_ADDR) +#define I2C7_BASE_ADDR 0 +#endif + +#if !defined(I2C8_BASE_ADDR) +#define I2C8_BASE_ADDR 0 +#endif + static struct mxc_i2c_bus mxc_i2c_buses[] = { #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \ defined(CONFIG_FSL_LAYERSCAPE) @@ -596,11 +612,19 @@ static struct mxc_i2c_bus mxc_i2c_buses[] = { { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG }, { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG }, { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG }, + { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG }, + { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG }, + { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG }, + { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG }, #else { 0, I2C1_BASE_ADDR, 0 }, { 1, I2C2_BASE_ADDR, 0 }, { 2, I2C3_BASE_ADDR, 0 }, { 3, I2C4_BASE_ADDR, 0 }, + { 4, I2C5_BASE_ADDR, 0 }, + { 5, I2C6_BASE_ADDR, 0 }, + { 6, I2C7_BASE_ADDR, 0 }, + { 7, I2C8_BASE_ADDR, 0 }, #endif }; @@ -738,6 +762,38 @@ U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe, CONFIG_SYS_MXC_I2C4_SLAVE, 3) #endif +#ifdef CONFIG_SYS_I2C_MXC_I2C5 +U_BOOT_I2C_ADAP_COMPLETE(mxc4, mxc_i2c_init, mxc_i2c_probe, + mxc_i2c_read, mxc_i2c_write, + mxc_i2c_set_bus_speed, + CONFIG_SYS_MXC_I2C5_SPEED, + CONFIG_SYS_MXC_I2C5_SLAVE, 4) +#endif + +#ifdef CONFIG_SYS_I2C_MXC_I2C6 +U_BOOT_I2C_ADAP_COMPLETE(mxc5, mxc_i2c_init, mxc_i2c_probe, + mxc_i2c_read, mxc_i2c_write, + mxc_i2c_set_bus_speed, + CONFIG_SYS_MXC_I2C6_SPEED, + CONFIG_SYS_MXC_I2C6_SLAVE, 5) +#endif + +#ifdef CONFIG_SYS_I2C_MXC_I2C7 +U_BOOT_I2C_ADAP_COMPLETE(mxc6, mxc_i2c_init, mxc_i2c_probe, + mxc_i2c_read, mxc_i2c_write, + mxc_i2c_set_bus_speed, + CONFIG_SYS_MXC_I2C7_SPEED, + CONFIG_SYS_MXC_I2C7_SLAVE, 6) +#endif + +#ifdef CONFIG_SYS_I2C_MXC_I2C8 +U_BOOT_I2C_ADAP_COMPLETE(mxc7, mxc_i2c_init, mxc_i2c_probe, + mxc_i2c_read, mxc_i2c_write, + mxc_i2c_set_bus_speed, + CONFIG_SYS_MXC_I2C8_SPEED, + CONFIG_SYS_MXC_I2C8_SLAVE, 7) +#endif + #else static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) -- cgit v1.2.1 From 7adafc146fd80d3665df2a37b9e1f84f514084b3 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Thu, 11 Jan 2018 15:14:17 +0100 Subject: imx: fix CAAM base for i.MX6UL HW accelerated "hash sha256 ..." command doesn't work on i.MX6UL, we get "CAAM was not setup properly or it is faulty" error message. This is due to wrong CAAM base 0x02100000, on i.MX6UL the CAAM base address is 0x02140000. Fix it. Note: with this patch applied the "hash sha256" commant still has some issues on i.MX6UL ("Invalid KEY Command" or other errors). With data cache off the "hash sha256" command works as expected. Signed-off-by: Anatolij Gustschin Reviewed-by: Fabio Estevam --- arch/arm/include/asm/arch-mx6/imx-regs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 8513406a8e..095eb74195 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -232,7 +232,11 @@ #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) #define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000) #define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000) +#if defined(CONFIG_MX6UL) +#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) +#else #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) +#endif #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) #define CONFIG_SYS_FSL_SEC_OFFSET 0 -- cgit v1.2.1 From d8b3ec4d1a2c08ee325da8b61bcc4a3f804be2b4 Mon Sep 17 00:00:00 2001 From: Nandor Han Date: Thu, 15 Feb 2018 11:41:21 +0100 Subject: board: ge: ppd: Fix environment variable location This fixes environment variable location to avoid overlapping with U-Boot itself. Also more space for environment variables has been reserved to prevent future issues. Signed-off-by: Nandor Han Signed-off-by: Sebastian Reichel --- include/configs/mx53ppd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index ed8ac48e01..00132d1743 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -199,8 +199,8 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* FLASH and environment organization */ -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_OFFSET (12 * 64 * 1024) +#define CONFIG_ENV_SIZE (10 * 1024) #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 -- cgit v1.2.1 From e73edcf18c6751ef5e4809615d37520376d9a06e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=B6rg=20Krause?= Date: Sun, 25 Feb 2018 18:12:47 +0100 Subject: ARM: dts: imx6ul: add wdog3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The i.MX6UL has a WDOG3 located at start address 0x021E0000 in the AIPS-2 memory region [1]. [1] i.MX 6UltraLite Applications Processor Reference Manual, Rev. 1, 04/2016, Table-2-3 AIPS-2 memory map, p. 166 Signed-off-by: Jörg Krause --- arch/arm/dts/imx6ul.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi index 7affab866f..b63f5a53ac 100644 --- a/arch/arm/dts/imx6ul.dtsi +++ b/arch/arm/dts/imx6ul.dtsi @@ -881,6 +881,14 @@ status = "disabled"; }; + wdog3: wdog@021e4000 { + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; + reg = <0x021e4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_WDOG3>; + status = "disabled"; + }; + uart2: serial@021e8000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; -- cgit v1.2.1 From 7906ed4fdd70bb88ea8e6f47c404949a957f0890 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=B6rg=20Krause?= Date: Sun, 25 Feb 2018 18:12:48 +0100 Subject: ARM: dts: imx6ull: add wdog3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The i.MX6ULL has a WDOG3 located at start address 0x021E0000 in the AIPS-2 memory region [1]. [1] i.MX 6ULL Applications Processor Reference Manual, Rev. 1, 11/2017, Table 2-3. AIPS-2 memory map, p. 178 Signed-off-by: Jörg Krause --- arch/arm/dts/imx6ull.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi index 28b8422f31..f8ec649460 100644 --- a/arch/arm/dts/imx6ull.dtsi +++ b/arch/arm/dts/imx6ull.dtsi @@ -1026,6 +1026,14 @@ status = "disabled"; }; + wdog3: wdog@021e4000 { + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; + reg = <0x021e4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_WDOG3>; + status = "disabled"; + }; + uart2: serial@021e8000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; -- cgit v1.2.1 From dad75e241c0a62b48ad40f4edbf81aecbbce8fd7 Mon Sep 17 00:00:00 2001 From: Eran Matityahu Date: Wed, 28 Feb 2018 09:51:34 +0200 Subject: mx7_common: Fix SPL compilation with secure boot support enabled The SPL MISC driver support must be enabled, so that the driver can use OTP fuse to check if HAB is enabled. Signed-off-by: Eran Matityahu --- include/configs/mx7_common.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index defb38c5b3..6ebf2e1c68 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -59,6 +59,9 @@ /* Secure boot (HAB) support */ #ifdef CONFIG_SECURE_BOOT #define CONFIG_CSF_SIZE 0x2000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#endif #endif #endif -- cgit v1.2.1 From 0004b7aa8a5edac7a17208cc5551d19b7f6f59a1 Mon Sep 17 00:00:00 2001 From: Eran Matityahu Date: Wed, 28 Feb 2018 09:51:50 +0200 Subject: Makefile: Build firmware-ivt image type for HAB verification also for mx7 Create u-boot-ivt.img and u-boot-ivt.img.log when building U-Boot with SPL and Secure Boot enabled for imx7 (like it is done for imx6). See commit d21bd69b6e95ca7824941e7f527871cd5c63c7f7 for more info. Signed-off-by: Eran Matityahu --- Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Makefile b/Makefile index c6819d5742..6eb30a3c66 100644 --- a/Makefile +++ b/Makefile @@ -781,8 +781,12 @@ ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin ifeq ($(CONFIG_MX6)$(CONFIG_SECURE_BOOT), yy) ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot-ivt.img else +ifeq ($(CONFIG_MX7)$(CONFIG_SECURE_BOOT), yy) +ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot-ivt.img +else ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img endif +endif ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb ifeq ($(CONFIG_SPL_FRAMEWORK),y) -- cgit v1.2.1 From 03858f8ec6032ec74dadfae6c3849302d8f29a9b Mon Sep 17 00:00:00 2001 From: Eran Matityahu Date: Tue, 6 Mar 2018 16:37:35 +0200 Subject: imx7: Add src_base structure define macro Add src_base structure global define macro, similarly to imx6 Signed-off-by: Eran Matityahu --- arch/arm/include/asm/arch-mx7/imx-regs.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index 3726f02af5..0cdb508d12 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -264,6 +264,8 @@ struct src { u32 ddrc_rcr; }; +#define src_base ((struct src *)SRC_BASE_ADDR) + #define SRC_M4_REG_OFFSET 0xC #define SRC_M4C_NON_SCLR_RST_OFFSET 0 #define SRC_M4C_NON_SCLR_RST_MASK BIT(0) -- cgit v1.2.1 From 0fe69adc8feacf69aabe44b779737079827d79b4 Mon Sep 17 00:00:00 2001 From: Eran Matityahu Date: Tue, 6 Mar 2018 16:38:00 +0200 Subject: imx7: spl: Check for Serial Downloader in spl_boot_device Similarly to imx6, before reading the boot device, first check bmode to see if the serial downloader has been selected explicitly, then check whether the serial downloader has been activated due to unbootable primary boot devices (e.g. empty eMMC). If the serial downloader is activated, return BOOT_DEVICE_BOARD. This allows SPL with SDP support to wait for the U-Boot image to be loaded via the serial download protocol using imx_usb_loader. Signed-off-by: Eran Matityahu --- arch/arm/mach-imx/spl.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index b2521b2101..6fc24630ba 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -101,6 +101,29 @@ u32 spl_boot_device(void) /* Translate iMX7/MX8M boot device to the SPL boot device enumeration */ u32 spl_boot_device(void) { +#if defined(CONFIG_MX7) + unsigned int bmode = readl(&src_base->sbmr2); + + /* + * Check for BMODE if serial downloader is enabled + * BOOT_MODE - see IMX7DRM Table 6-24 + */ + if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */ + return BOOT_DEVICE_BOARD; + + /* + * The above method does not detect that the boot ROM used + * serial downloader in case the boot ROM decided to use the + * serial downloader as a fall back (primary boot source failed). + * + * Infer that the boot ROM used the USB serial downloader by + * checking whether the USB PHY is currently active... This + * assumes that SPL did not (yet) initialize the USB PHY... + */ + if (is_boot_from_usb()) + return BOOT_DEVICE_BOARD; +#endif + enum boot_device boot_device_spl = get_boot_device(); switch (boot_device_spl) { -- cgit v1.2.1 From 8761e98141e2ea03d1abaf175f81af4be44ea060 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 8 Mar 2018 23:00:22 +0100 Subject: wandboard: remove superfluous include No definition provided by input.h is used in the board file. Signed-off-by: Heinrich Schuchardt Reviewed-by: Fabio Estevam --- board/wandboard/wandboard.c | 1 - 1 file changed, 1 deletion(-) diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 1e7c11e670..b7c6c6cb18 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include -- cgit v1.2.1 From 06587617337785709e59c7fbcfa1ec870a7945eb Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Fri, 23 Mar 2018 12:08:02 +0100 Subject: Makefile: always preserve output for images that can contain HAB Blocks The current makefile logic disables creation of the SPL.log/u-boot-ivt.img.log etc. files when V=1 is given on the command line, the rationale presumably being that the user wants and gets the information on the console. However, from general principles, I don't think a higher V= level should affect which build artifacts get generated (and certainly shouldn't produce fewer). Concretely, it's also a problem that when doing a V=1 build in a terminal, the relevant HAB blocks lines easily drown in all the other V=1 output. Moreover, build systems such as Yocto by default pass V=1, so in that case the information gets hidden away in the do_compile log file, making it nigh impossible to create a recipe for creating signed U-boot images - I don't want to disable V=1, because having verbose output in the log file is valuable when things go wrong, but OTOH trying to go digging in the do_compile log file (and getting exactly the right lines) is not pleasant to even think about. So change the logic so that for V=0, the mkimage output is redirected to MKIMAGEOUTPUT (which is also the current behaviour), while for any other value of V, we _additionally_ write the information to make's stdout, whatever that might be. Signed-off-by: Rasmus Villemoes Tested-by: Breno Lima --- Makefile | 4 ++-- scripts/Makefile.lib | 2 +- scripts/Makefile.spl | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 6eb30a3c66..f67ad69de2 100644 --- a/Makefile +++ b/Makefile @@ -844,11 +844,11 @@ MKIMAGEOUTPUT ?= /dev/null quiet_cmd_mkimage = MKIMAGE $@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ - $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT)) + >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT)) quiet_cmd_mkfitimage = MKIMAGE $@ cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ \ - $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT)) + >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT)) quiet_cmd_cat = CAT $@ cmd_cat = cat $(filter-out $(PHONY), $^) > $@ diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 8f21653136..c6b3f69064 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -521,7 +521,7 @@ cmd_xzmisc = (cat $(filter-out FORCE,$^) | \ MKIMAGEOUTPUT ?= /dev/null quiet_cmd_mkimage = MKIMAGE $@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ - $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT)) + >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT)) # fdtgrep # --------------------------------------------------------------------------- diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 2993ade41e..7f2908d799 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -144,7 +144,7 @@ MKIMAGEOUTPUT ?= /dev/null quiet_cmd_mkimage = MKIMAGE $@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ - $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT)) + >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT)) MKIMAGEFLAGS_MLO = -T omapimage -a $(CONFIG_SPL_TEXT_BASE) -- cgit v1.2.1 From 8519c9c98ad60e9eb6f655bfa8214f53407d86fb Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Fri, 23 Mar 2018 12:08:03 +0100 Subject: tools/imximage: use 0x prefix in HAB Blocks line The u-boot-ivt.img.log file contains 0x prefixes in the HAB Blocks line, while the SPL.log does not. For consistency, and to make it easier to extract and put into a .csf file for use with NXP's code signing tool, add 0x prefixes here. Signed-off-by: Rasmus Villemoes Reviewed-by: Fabio Estevam Tested-by: Breno Lima --- doc/README.mxc_hab | 14 +++++++------- tools/imximage.c | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/doc/README.mxc_hab b/doc/README.mxc_hab index 75390a505e..a40ebf3e84 100644 --- a/doc/README.mxc_hab +++ b/doc/README.mxc_hab @@ -33,12 +33,12 @@ Image Ver: 2 (i.MX53/6 compatible) Data Size: 327680 Bytes = 320.00 kB = 0.31 MB Load Address: 177ff420 Entry Point: 17800000 -HAB Blocks: 177ff400 00000000 0004dc00 - ^^^^^^^^ ^^^^^^^^ ^^^^^^^^ - | | | - | | -------- (1) - | | - | ------------------- (2) +HAB Blocks: 0x177ff400 0x00000000 0x0004dc00 + ^^^^^^^^^^ ^^^^^^^^^^ ^^^^^^^^^^ + | | | + | | ----- (1) + | | + | ---------------- (2) | --------------------------- (3) @@ -78,7 +78,7 @@ Example Output of the SPL (imximage) creation: Data Size: 61440 Bytes = 60.00 kB = 0.06 MB Load Address: 00907420 Entry Point: 00908000 - HAB Blocks: 00907400 00000000 0000cc00 + HAB Blocks: 0x00907400 0x00000000 0x0000cc00 Example Output of the u-boot-ivt.img (firmware_ivt) creation: Image Name: U-Boot 2016.11-rc1-31589-g2a4411 diff --git a/tools/imximage.c b/tools/imximage.c index ed9d935903..6dabb13520 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -516,7 +516,7 @@ static void print_hdr_v2(struct imx_header *imx_hdr) offs = (char *)&hdr_v2->data.dcd_table - (char *)hdr_v2; - printf("HAB Blocks: %08x %08x %08x\n", + printf("HAB Blocks: 0x%08x 0x%08x 0x%08x\n", (uint32_t)fhdr_v2->self, 0, hdr_v2->boot_data.size - imximage_ivt_offset - imximage_csf_size); -- cgit v1.2.1 From 14eeb683a862bf64e6b6383b888c42bbe2a50e7b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 30 Mar 2018 03:04:43 +0200 Subject: ARM: mx6: ddr: Add write leveling correction code When the DDR calibration is enabled, a situation may happen that it will fail on a few select boards out of a whole production lot. In particular, after the first write leveling stage, the MPWLDECTRLx registers will contain a value 0x1nn , for nn usually being 0x7f or slightly lower. What this means is that the HW write leveling detected that the DQS rising edge on one or more bundles arrives slightly _after_ CLK and therefore when the DDR DRAM samples CLK on the DQS rising edge, the CLK signal is already high (cfr. AN4467 rev2 Figure 7 on page 18). The HW write leveling then ends up adding almost an entire cycle (thus the 0x17f) to the DQS delay, which indeed aligns it, but also triggers subsequent calibration failure in DQS gating due to this massive offset. There are two observations here: - If the MPWLDECTRLx value is corrected from 0x17f to 0x0 , then the DQS gating passes, the entire calibration passes as well and the DRAM is perfectly stable even under massive load. - When using the NXP DRAM calibrator for iMX6/7, the value 0x17f or so in MPWLDECTRx register is not there, but it is replaced by 0x0 as one would expect. Someone from NXP finally explains why, quoting [1]: " Having said all that, the DDR Stress Test does something that we do not advertise to the users. The Stress Test iself looks at the values of the MPWLDECTRL0/1 fields before reporting results, and if it sees any filed with a value greater than 200/256 delay (reported as half-cycle = 0x1 and ABS_OFFSET > 0x48), the DDR Stress test will reset the Write Leveling delay for this lane to 0x000 and not report it in the log. The reason that the DDR Stress test does this is because a delay of more than 78% a clock cycle means that the DQS edge is arriving within the JEDEC tolerence of 25% of the clock edge. In most cases, DQS is arriving < 5% tCK of the SDCLK edge in the early case, and it does not make sense to delay the DQS strobe almost a full clock cycle and add extra latency to each Write burst just to make the two edges align exactly. In this case, we are guilty of making a decision for the customer without telling them we are doing it so that we don't have to provide the above explanation to every customer. They don't need to know it. " This patch adds the correction described above, that is if the MPWLDECTRx value is over 0x148, the value is corrected back to 0x0. [1] https://community.nxp.com/thread/456246 Signed-off-by: Marek Vasut Cc: Stefano Babic Reviewed-by: Fabio Estevam Reviewed-by: Eric Nelson Reviewed-by: Stefano Babic --- arch/arm/mach-imx/mx6/ddr.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c index 43b77cfa41..6e5e40dd1a 100644 --- a/arch/arm/mach-imx/mx6/ddr.c +++ b/arch/arm/mach-imx/mx6/ddr.c @@ -85,6 +85,23 @@ static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl) writel(val_ctrl, reg_ctrl); } +static void correct_mpwldectr_result(void *reg) +{ + /* Limit is 200/256 of CK, which is WL_HC_DELx | 0x48. */ + const unsigned int limit = 0x148; + u32 val = readl(reg); + u32 old = val; + + if ((val & 0x17f) > limit) + val &= 0xffff << 16; + + if (((val >> 16) & 0x17f) > limit) + val &= 0xffff; + + if (old != val) + writel(val, reg); +} + int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo) { struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; @@ -176,6 +193,13 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo) errors |= 4; } + correct_mpwldectr_result(&mmdc0->mpwldectrl0); + correct_mpwldectr_result(&mmdc0->mpwldectrl1); + if (sysinfo->dsize == 2) { + correct_mpwldectr_result(&mmdc1->mpwldectrl0); + correct_mpwldectr_result(&mmdc1->mpwldectrl1); + } + /* * User should issue MRS command to exit write leveling mode * through Load Mode Register command -- cgit v1.2.1 From ca83182226d2300722ebbb44e8f291678606b568 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Mon, 26 Mar 2018 15:27:32 +0100 Subject: imx: mx7: Fix CONFIG_SERIAL_TAG compilation Currently when we define CONFIG_SERIAL_TAG we will barf with a failure to define "struct tag_serialnr". This structure is defined in , this patch includes to fix. Signed-off-by: Bryan O'Donoghue Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic Reviewed-by: Fabio Estevam --- arch/arm/mach-imx/mx7/soc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index d349676b81..1602585564 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -18,6 +18,7 @@ #include #include #include +#include #if defined(CONFIG_IMX_THERMAL) static const struct imx_thermal_plat imx7_thermal_plat = { -- cgit v1.2.1 From 1ab1ffded4f1363080324d96a12fd76c90175be2 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Mon, 26 Mar 2018 15:27:33 +0100 Subject: imx: mx7: Add comment to describe OTP TESTER registers The tester registers provide a unique chip-level identifier which get_board_serial() returns in a "struct tag_serialnr". This patch documents the properties of the registers; in summary. 31:0 OCOTP_TESTER0 (most significant) - FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID OCOTP_TESTER1 (least significant) 31:24 - The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID 23:16 - The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID 15:11 - The wafer number of the wafer on which the device was fabricated/SJC CHALLENGE/ Unique ID 10:0 - FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID The 64 bits of data generate a unique serial number per-chip. Signed-off-by: Bryan O'Donoghue Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic Reviewed-by: Fabio Estevam --- arch/arm/mach-imx/mx7/soc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 1602585564..fb92a26e45 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -202,6 +202,27 @@ int arch_misc_init(void) #endif #ifdef CONFIG_SERIAL_TAG +/* + * OCOTP_TESTER + * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016 + * OCOTP_TESTER describes a unique ID based on silicon wafer + * and die X/Y position + * + * OCOTOP_TESTER offset 0x410 + * 31:0 fuse 0 + * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID + * + * OCOTP_TESTER1 offset 0x420 + * 31:24 fuse 1 + * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID + * 23:16 fuse 1 + * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID + * 15:11 fuse 1 + * The wafer number of the wafer on which the device was fabricated/SJC + * CHALLENGE/ Unique ID + * 10:0 fuse 1 + * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID + */ void get_board_serial(struct tag_serialnr *serialnr) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; -- cgit v1.2.1 From 852cc548b3fdf6d5b46e2a96f876d14608ccdcf4 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Mon, 26 Mar 2018 15:27:34 +0100 Subject: warp7: Set u-boot serial# based on OTP value u-boot has a standard "serial#" environment variable that is suitable for storing the iSerial number we will supply via the USB device descriptor. serial# is automatically picked up by the disk subsystem in u-boot - thus providing a handy unique identifier in /dev/disk/by-id as detailed below. Storing the hardware serial identifier in serial# means we can change the serial# if we want before USB enumeration - thus making iSerial automatic via OTP but overridable if necessary. This patch reads the defined OTP fuse and sets environment variable "serial#" to the value read. With this patch in place the USB mass storage device will appear in /dev/disk/by-id with a unique name based on the OTP value. For example /dev/disk/by-id/usb-Linux_UMS_disk_0_WaRP7-0xf42400d3000001d4-0:0 Signed-off-by: Bryan O'Donoghue Cc: Fabio Estevam Cc: Rui Miguel Silva Cc: Ryan Harkin Reviewed-by: Fabio Estevam --- board/warp7/warp7.c | 14 ++++++++++++++ include/configs/warp7.h | 3 +++ 2 files changed, 17 insertions(+) diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c index d422d63df5..327f656c44 100644 --- a/board/warp7/warp7.c +++ b/board/warp7/warp7.c @@ -23,6 +23,8 @@ #include #include #include "../freescale/common/pfuze.h" +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -186,6 +188,10 @@ int board_usb_phy_mode(int port) int board_late_init(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; +#ifdef CONFIG_SERIAL_TAG + struct tag_serialnr serialnr; + char serial_string[0x20]; +#endif imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); @@ -197,5 +203,13 @@ int board_late_init(void) */ clrsetbits_le16(&wdog->wcr, 0, 0x10); +#ifdef CONFIG_SERIAL_TAG + /* Set serial# standard environment variable based on OTP settings */ + get_board_serial(&serialnr); + snprintf(serial_string, sizeof(serial_string), "WaRP7-0x%08x%08x", + serialnr.low, serialnr.high); + env_set("serial#", serial_string); +#endif + return 0; } diff --git a/include/configs/warp7.h b/include/configs/warp7.h index fe96988be7..0c3b605de3 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -24,6 +24,9 @@ #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +/* Switch on SERIAL_TAG */ +#define CONFIG_SERIAL_TAG + #define CONFIG_DFU_ENV_SETTINGS \ "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \ -- cgit v1.2.1 From f4d8fccd3884ea8f76503966b14d0c25129e23eb Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Mon, 26 Mar 2018 15:36:45 +0100 Subject: imximage: Encase majority of header in __ASSEMBLY__ declaration Subsequent patches will want to include imageimage.h but in doing so include it on an assembly compile path causing a range of compile errors. Fix the errors pre-emptively by encasing the majority of the declarations in imximage.h inside an ifdef __ASSEMBLY__ block. Signed-off-by: Bryan O'Donoghue Cc: Utkarsh Gupta Cc: Breno Lima Cc: Fabio Estevam Signed-off-by: Bryan O'Donoghue Tested-by: Breno Lima --- include/imximage.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/imximage.h b/include/imximage.h index de1ea8ff14..553b852367 100644 --- a/include/imximage.h +++ b/include/imximage.h @@ -56,6 +56,7 @@ #define DCD_CHECK_BITS_SET_PARAM 0x14 #define DCD_CHECK_BITS_CLR_PARAM 0x04 +#ifndef __ASSEMBLY__ enum imximage_cmd { CMD_INVALID, CMD_IMAGE_VERSION, @@ -197,4 +198,5 @@ typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr, typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len, uint32_t entry_point, uint32_t flash_offset); +#endif /* __ASSEMBLY__ */ #endif /* _IMXIMAGE_H_ */ -- cgit v1.2.1 From 49e6242673615225a434df5bfad60a4720a7d88c Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Mon, 26 Mar 2018 15:36:46 +0100 Subject: imx: hab: Provide hab_auth_img_or_fail command This patch adds hab_auth_img_or_fail() a command line function that encapsulates a common usage of authenticate and failover, namely if authenticate image fails, then drop to BootROM USB recovery mode. For secure-boot systems, this type of locked down behavior is important to ensure no unsigned images can be run. It's possible to script this logic but, when done over and over again the environment starts get very complex and repetitive, reducing that script repetition down to a command line function makes sense. Signed-off-by: Bryan O'Donoghue Cc: Utkarsh Gupta Cc: Breno Lima Cc: Fabio Estevam Signed-off-by: Bryan O'Donoghue Tested-by: Breno Lima --- arch/arm/mach-imx/hab.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index c3fc699d02..7eefab5d73 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -341,6 +341,31 @@ static int do_hab_failsafe(cmd_tbl_t *cmdtp, int flag, int argc, return 0; } +static int do_authenticate_image_or_failover(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + int ret = CMD_RET_FAILURE; + + if (argc != 4) { + ret = CMD_RET_USAGE; + goto error; + } + + if (!imx_hab_is_enabled()) { + printf("error: secure boot disabled\n"); + goto error; + } + + if (do_authenticate_image(NULL, flag, argc, argv) != CMD_RET_SUCCESS) { + fprintf(stderr, "authentication fail -> %s %s %s %s\n", + argv[0], argv[1], argv[2], argv[3]); + do_hab_failsafe(0, 0, 1, NULL); + }; + ret = CMD_RET_SUCCESS; +error: + return ret; +} + U_BOOT_CMD( hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status, "display HAB status", @@ -362,6 +387,16 @@ U_BOOT_CMD( "" ); +U_BOOT_CMD( + hab_auth_img_or_fail, 4, 0, + do_authenticate_image_or_failover, + "authenticate image via HAB on failure drop to USB BootROM mode", + "addr length ivt_offset\n" + "addr - image hex address\n" + "length - image hex length\n" + "ivt_offset - hex offset of IVT in the image" + ); + #endif /* !defined(CONFIG_SPL_BUILD) */ /* Get CSF Header length */ -- cgit v1.2.1 From 7a0ce1f7977b0ef8d853fee73238d0b3b34fbfed Mon Sep 17 00:00:00 2001 From: Ken Lin Date: Fri, 30 Mar 2018 09:11:42 +0800 Subject: arm: imx: Add Winbond SPI-NOR support for Advantech DMS-BA16 board Windbond's been in the AVL list and need to enable the support Signed-off-by: Ken Lin --- configs/dms-ba16-1g_defconfig | 1 + configs/dms-ba16_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/dms-ba16-1g_defconfig b/configs/dms-ba16-1g_defconfig index 40b317093f..8008916234 100644 --- a/configs/dms-ba16-1g_defconfig +++ b/configs/dms-ba16-1g_defconfig @@ -32,6 +32,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DWC_AHSATA=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHYLIB=y CONFIG_MXC_SPI=y CONFIG_USB=y diff --git a/configs/dms-ba16_defconfig b/configs/dms-ba16_defconfig index 3519c5275c..7803052642 100644 --- a/configs/dms-ba16_defconfig +++ b/configs/dms-ba16_defconfig @@ -31,6 +31,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DWC_AHSATA=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHYLIB=y CONFIG_MXC_SPI=y CONFIG_USB=y -- cgit v1.2.1 From 6c0e6b45f9bd4fdc795f4aec72dd13fd6fc6f617 Mon Sep 17 00:00:00 2001 From: Ian Ray Date: Wed, 4 Apr 2018 10:50:17 +0200 Subject: board: ge: bx50v3: enable backlight on demand Enable display backlight only if a message needs to be displayed. The kernel re-initializes the backlight, which results in some unwanted artifacts. Signed-off-by: Ian Ray Signed-off-by: Sebastian Reichel --- board/ge/bx50v3/bx50v3.c | 45 ++++++++++++++++++++++++++++----------------- include/configs/ge_bx50v3.h | 1 + 2 files changed, 29 insertions(+), 17 deletions(-) diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index c7a29185bf..46321ae666 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -786,23 +786,6 @@ int board_late_init(void) add_board_boot_modes(board_boot_modes); #endif -#ifdef CONFIG_VIDEO_IPUV3 - /* We need at least 200ms between power on and backlight on - * as per specifications from CHI MEI */ - mdelay(250); - - /* enable backlight PWM 1 */ - pwm_init(0, 0, 0); - - /* duty cycle 5000000ns, period: 5000000ns */ - pwm_config(0, 5000000, 5000000); - - /* Backlight Power */ - gpio_direction_output(LVDS_BACKLIGHT_GP, 1); - - pwm_enable(0); -#endif - /* board specific pmic init */ pmic_init(); @@ -843,3 +826,31 @@ int checkboard(void) printf("BOARD: %s\n", CONFIG_BOARD_NAME); return 0; } + +static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ +#ifdef CONFIG_VIDEO_IPUV3 + /* We need at least 200ms between power on and backlight on + * as per specifications from CHI MEI */ + mdelay(250); + + /* enable backlight PWM 1 */ + pwm_init(0, 0, 0); + + /* duty cycle 5000000ns, period: 5000000ns */ + pwm_config(0, 5000000, 5000000); + + /* Backlight Power */ + gpio_direction_output(LVDS_BACKLIGHT_GP, 1); + + pwm_enable(0); +#endif + + return 0; +} + +U_BOOT_CMD( + bx50_backlight_enable, 1, 1, do_backlight_enable, + "enable Bx50 backlight", + "" +); diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index cbfe30d536..925507fe81 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -128,6 +128,7 @@ "swappartitions=" \ "setexpr partnum 3 - ${partnum}\0" \ "failbootcmd=" \ + "bx50_backlight_enable; " \ "msg=\"Monitor failed to start. Try again, or contact GE Service for support.\"; " \ "echo $msg; " \ "setenv stdout vga; " \ -- cgit v1.2.1 From dd4671cb3f12a6e24eec8b76cbcb09a35bd30738 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 5 Apr 2018 09:04:38 +0200 Subject: imx: board: Add support for the K+P's kp_imx6q_tpc board This commit provides support for Kieback & Peter GmbH IMX6Q based TPC board. U-boot console output: U-Boot SPL 2018.05-rc1-00005-g631e2d01fd (Apr 04 2018 - 21:16:24 +0200) Trying to boot from MMC1 U-Boot 2018.05-rc1-00005-g631e2d01fd (Apr 04 2018 - 21:16:24 +0200) CPU: Freescale i.MX6Q rev1.5 996 MHz (running at 792 MHz) CPU: Extended Commercial temperature grade (-20C to 105C) at 37C Reset cause: POR Board: K+P KP_IMX6Q_TPC i.MX6Q Watchdog enabled I2C: ready DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: FEC [PRIME] Autoboot in 3 seconds --- arch/arm/mach-imx/mx6/Kconfig | 11 + board/k+p/kp_imx6q_tpc/Kconfig | 12 ++ board/k+p/kp_imx6q_tpc/MAINTAINERS | 6 + board/k+p/kp_imx6q_tpc/Makefile | 11 + board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c | 302 ++++++++++++++++++++++++++ board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c | 338 ++++++++++++++++++++++++++++++ configs/kp_imx6q_tpc_defconfig | 42 ++++ include/configs/kp_imx6q_tpc.h | 141 +++++++++++++ 8 files changed, 863 insertions(+) create mode 100644 board/k+p/kp_imx6q_tpc/Kconfig create mode 100644 board/k+p/kp_imx6q_tpc/MAINTAINERS create mode 100644 board/k+p/kp_imx6q_tpc/Makefile create mode 100644 board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c create mode 100644 board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c create mode 100644 configs/kp_imx6q_tpc_defconfig create mode 100644 include/configs/kp_imx6q_tpc.h diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index d4ce38db8d..aa6f5facbf 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -387,6 +387,16 @@ config TARGET_TBS2910 config TARGET_TITANIUM bool "titanium" +config TARGET_KP_IMX6Q_TPC + bool "K+P KP_IMX6Q_TPC i.MX6 Quad" + select MX6QDL + select BOARD_LATE_INIT + select BOARD_EARLY_INIT_F + select SUPPORT_SPL + select DM + select DM_THERMAL + imply CMD_SPL + config TARGET_TQMA6 bool "TQ Systems TQMa6 board" select BOARD_LATE_INIT @@ -493,6 +503,7 @@ source "board/tbs/tbs2910/Kconfig" source "board/tqc/tqma6/Kconfig" source "board/toradex/apalis_imx6/Kconfig" source "board/toradex/colibri_imx6/Kconfig" +source "board/k+p/kp_imx6q_tpc/Kconfig" source "board/udoo/Kconfig" source "board/udoo/neo/Kconfig" source "board/wandboard/Kconfig" diff --git a/board/k+p/kp_imx6q_tpc/Kconfig b/board/k+p/kp_imx6q_tpc/Kconfig new file mode 100644 index 0000000000..62e34978ec --- /dev/null +++ b/board/k+p/kp_imx6q_tpc/Kconfig @@ -0,0 +1,12 @@ +if TARGET_KP_IMX6Q_TPC + +config SYS_BOARD + default "kp_imx6q_tpc" + +config SYS_VENDOR + default "k+p" + +config SYS_CONFIG_NAME + default "kp_imx6q_tpc" + +endif diff --git a/board/k+p/kp_imx6q_tpc/MAINTAINERS b/board/k+p/kp_imx6q_tpc/MAINTAINERS new file mode 100644 index 0000000000..6c4c8dd28e --- /dev/null +++ b/board/k+p/kp_imx6q_tpc/MAINTAINERS @@ -0,0 +1,6 @@ +KP_IMX6Q_TPC BOARD +M: Lukasz Majewski +S: Maintained +F: board/k+p/kp_imx6q_tpc/ +F: include/configs/kp_imx6q_tpc.h +F: configs/kp_imx6q_tpc_defconfig diff --git a/board/k+p/kp_imx6q_tpc/Makefile b/board/k+p/kp_imx6q_tpc/Makefile new file mode 100644 index 0000000000..51cbd3e843 --- /dev/null +++ b/board/k+p/kp_imx6q_tpc/Makefile @@ -0,0 +1,11 @@ +# +# Copyright (C) 2018 Lukasz Majewski +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y := kp_imx6q_tpc_spl.o +else +obj-y := kp_imx6q_tpc.o +endif diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c new file mode 100644 index 0000000000..9a5b88029f --- /dev/null +++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c @@ -0,0 +1,302 @@ +/* + * K+P iMX6Q KP_IMX6Q_TPC board configuration + * + * Copyright (C) 2018 Lukasz Majewski + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ENET_PAD_CTRL \ + (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS) + +#define I2C_PAD_CTRL \ + (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL | PC, + .gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 | PC, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA | PC, + .gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 | PC, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const enet_pads[] = { + IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | + MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | + MUX_PAD_CTRL(ENET_PAD_CTRL)), + /* AR8031 PHY Reset */ + IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static void eth_phy_reset(void) +{ + /* Reset AR8031 PHY */ + gpio_direction_output(IMX_GPIO_NR(1, 25), 0); + mdelay(10); + gpio_set_value(IMX_GPIO_NR(1, 25), 1); + udelay(100); +} + +static int setup_fec_clock(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* set gpr1[21] to select anatop clock */ + clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21); + + return enable_fec_anatop_clock(0, ENET_50MHZ); +} + +int board_eth_init(bd_t *bis) +{ + SETUP_IOMUX_PADS(enet_pads); + setup_fec_clock(); + eth_phy_reset(); + + return cpu_eth_init(bis); +} + +static int ar8031_phy_fixup(struct phy_device *phydev) +{ + unsigned short val; + + /* To enable AR8031 output a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + ar8031_phy_fixup(phydev); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC + +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) +static struct fsl_esdhc_cfg usdhc_cfg[] = { + { USDHC2_BASE_ADDR }, + { USDHC4_BASE_ADDR }, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + return !gpio_get_value(USDHC2_CD_GPIO); + case USDHC4_BASE_ADDR: + return 1; /* eMMC/uSDHC4 is always present */ + } + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 micro SD + * mmc2 eMMC + */ + gpio_direction_input(USDHC2_CD_GPIO); + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +static void setup_usb(void) +{ + /* + * Set daisy chain for otg_pin_id on MX6Q. + * For MX6DL, this bit is reserved. + */ + imx_iomux_set_gpr_register(1, 13, 1, 0); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return USB_INIT_DEVICE; +} + +int board_ehci_power(int port, int on) +{ + switch (port) { + case 0: + break; + case 1: + gpio_direction_output(IMX_GPIO_NR(3, 31), !!on); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } + + return 0; +} +#endif + +int board_early_init_f(void) +{ +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + + return 0; +} + +int board_init(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* Enable eim_slow clocks */ + setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info1); + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + /* 8 bit bus width */ + {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + env_set("boardname", "kp-tpc"); + env_set("boardsoc", "imx6q"); + return 0; +} + +int checkboard(void) +{ + puts("Board: K+P KP_IMX6Q_TPC i.MX6Q\n"); + return 0; +} diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c new file mode 100644 index 0000000000..3fdfea7546 --- /dev/null +++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c @@ -0,0 +1,338 @@ +/* + * K+P iMX6Q KP_IMX6Q_TPC board configuration + * + * Copyright (C) 2018 Lukasz Majewski + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define UART_PAD_CTRL \ + (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL \ + (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +DECLARE_GLOBAL_DATA_PTR; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +/* onboard microSD */ +static iomux_v3_cfg_t const usdhc2_pads[] = { + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +/* eMMC */ +static iomux_v3_cfg_t const usdhc4_pads[] = { + IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + +/* SD */ +static void setup_iomux_sd(void) +{ + SETUP_IOMUX_PADS(usdhc2_pads); + SETUP_IOMUX_PADS(usdhc4_pads); +} + +/* UART */ +static iomux_v3_cfg_t const uart1_pads[] = { + IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +/* USB */ +static iomux_v3_cfg_t const usb_pads[] = { + IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static void setup_iomux_usb(void) +{ + SETUP_IOMUX_PADS(usb_pads); +} + +/* DDR3 */ +static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_sdclk_0 = 0x00000030, + .dram_sdclk_1 = 0x00000030, + .dram_cas = 0x00000030, + .dram_ras = 0x00000030, + .dram_reset = 0x00000030, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x00000030, + .dram_sdodt1 = 0x00000030, + + .dram_sdqs0 = 0x00000018, + .dram_sdqs1 = 0x00000018, + .dram_sdqs2 = 0x00000018, + .dram_sdqs3 = 0x00000018, + .dram_sdqs4 = 0x00000018, + .dram_sdqs5 = 0x00000018, + .dram_sdqs6 = 0x00000018, + .dram_sdqs7 = 0x00000018, + + .dram_dqm0 = 0x00000018, + .dram_dqm1 = 0x00000018, + .dram_dqm2 = 0x00000018, + .dram_dqm3 = 0x00000018, + .dram_dqm4 = 0x00000018, + .dram_dqm5 = 0x00000018, + .dram_dqm6 = 0x00000018, + .dram_dqm7 = 0x00000018, +}; + +static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000018, + .grp_b1ds = 0x00000018, + .grp_b2ds = 0x00000018, + .grp_b3ds = 0x00000018, + .grp_b4ds = 0x00000018, + .grp_b5ds = 0x00000018, + .grp_b6ds = 0x00000018, + .grp_b7ds = 0x00000018, +}; + +static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = { + .p0_mpwldectrl0 = 0x001F001F, + .p0_mpwldectrl1 = 0x001F001F, + .p1_mpwldectrl0 = 0x001F001F, + .p1_mpwldectrl1 = 0x001F001F, + .p0_mpdgctrl0 = 0x43270338, + .p0_mpdgctrl1 = 0x03200314, + .p1_mpdgctrl0 = 0x431A032F, + .p1_mpdgctrl1 = 0x03200263, + .p0_mprddlctl = 0x4B434748, + .p1_mprddlctl = 0x4445404C, + .p0_mpwrdlctl = 0x38444542, + .p1_mpwrdlctl = 0x4935493A, +}; + +/* MT41K256M16 (4Gb density) */ +static const struct mx6_ddr3_cfg mt41k256m16 = { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +#ifdef CONFIG_MX6_DDRCAL +static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo) +{ + struct mx6_mmdc_calibration calibration = {0}; + + mmdc_read_calibration(sysinfo, &calibration); + + debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0); + debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1); + debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl); + debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl); + debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0); + debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1); + debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0); + debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1); + debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl); + debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl); + debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0); + debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1); +} + +static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo) +{ + int ret; + + /* Perform DDR DRAM calibration */ + udelay(100); + ret = mmdc_do_write_level_calibration(sysinfo); + if (ret) { + printf("DDR: Write level calibration error [%d]\n", ret); + return; + } + + ret = mmdc_do_dqs_calibration(sysinfo); + if (ret) { + printf("DDR: DQS calibration error [%d]\n", ret); + return; + } + + spl_dram_print_cal(sysinfo); +} +#endif /* CONFIG_MX6_DDRCAL */ + +static void spl_dram_init(void) +{ + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = 2, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .pd_fast_exit = 1, /* enable precharge power-down fast exit */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ + }; + + mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k256m16); + +#ifdef CONFIG_MX6_DDRCAL + spl_dram_perform_cal(&sysinfo); +#endif +} + +struct fsl_esdhc_cfg usdhc_cfg[] = { + {USDHC2_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = 1; /* eMMC/uSDHC4 is always present */ + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bd) +{ + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned int reg = readl(&psrc->sbmr1) >> 11; + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD1 + * 0x3 SD4 + */ + + switch (reg & 0x3) { + case 0x1: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 0x3: + SETUP_IOMUX_PADS(usdhc4_pads); + usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + } + + return fsl_esdhc_initialize(bd, &usdhc_cfg[0]); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* setup GP timer */ + timer_init(); + + setup_iomux_sd(); + setup_iomux_uart(); + setup_iomux_usb(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig new file mode 100644 index 0000000000..d2c6e2e6ba --- /dev/null +++ b/configs/kp_imx6q_tpc_defconfig @@ -0,0 +1,42 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x17800000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_MX6_DDRCAL=y +CONFIG_TARGET_KP_IMX6Q_TPC=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SPL=y +CONFIG_SPL_RAW_IMAGE_SUPPORT=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR="." +# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_ENV_IS_IN_MMC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h new file mode 100644 index 0000000000..fae2faec2f --- /dev/null +++ b/include/configs/kp_imx6q_tpc.h @@ -0,0 +1,141 @@ +/* + * K+P iMX6Q KP_IMX6Q_TPC board configuration + * + * Copyright (C) 2018 Lukasz Majewski + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __KP_IMX6Q_TPC_IMX6_CONFIG_H_ +#define __KP_IMX6Q_TPC_IMX6_CONFIG_H_ + +#include + +#include "mx6_common.h" + +/* SPL */ +#include "imx6_spl.h" /* common IMX6 SPL configuration */ + +/* Miscellaneous configurable options */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_BOUNCE_BUFFER + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M) + +/* FEC ethernet */ +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_ARP_TIMEOUT 200UL + +/* Fuses */ +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* 0 = SDHC2, 1 = SDHC4 (eMMC) */ + +/* UART */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ +#endif + +/* Watchdog */ +#define CONFIG_HW_WATCHDOG +#define CONFIG_IMX_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200\0" \ + "fdt_addr=0x18000000\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "kernel_addr_r=0x10008000\0" \ + "fdt_addr_r=0x13000000\0" \ + "ramdisk_addr_r=0x18000000\0" \ + "scriptaddr=0x14000000\0" \ + "kernel_file=fitImage\0"\ + "rdinit=/sbin/init\0" \ + "addinitrd=setenv bootargs ${bootargs} rdinit=${rdinit} ${debug} \0" \ + "fit_config=mx6q_tpc70_conf\0" \ + "upd_image=st.4k\0" \ + "updargs=setenv bootargs console=${console} ${smp}"\ + "rdinit=${rdinit} ${debug} ${displayargs}\0" \ + "loadusb=usb start; " \ + "fatload usb 0 ${loadaddr} ${upd_image}\0" \ + "usbupd=echo Booting update from usb ...; " \ + "setenv bootargs; " \ + "run updargs; " \ + "run loadusb; " \ + "bootm ${loadaddr}#${fit_config}\0" \ + BOOTENV + +#define CONFIG_BOOTCOMMAND "run usbupd; run distro_bootcmd" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) + +#include +#endif + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment */ +#define CONFIG_ENV_SIZE (SZ_8K) +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT + +#endif /* __KP_IMX6Q_TPC_IMX6_CONFIG_H_ */ -- cgit v1.2.1 From b04ff9bf0f52b0fc94c24510bfd2b340ff47733d Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 5 Apr 2018 09:04:39 +0200 Subject: boot: script: The boot.scr file for K+P's boards By using this file one can avoid cluttering .h file with u-boot HUSH commands necessary for booting target device. With such approach the commands are stored only in one place and can be reused if needed. Signed-off-by: Lukasz Majewski Reviewed-by: Stefano Babic --- board/k+p/bootscripts/tpcboot.cmd | 96 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 board/k+p/bootscripts/tpcboot.cmd diff --git a/board/k+p/bootscripts/tpcboot.cmd b/board/k+p/bootscripts/tpcboot.cmd new file mode 100644 index 0000000000..f6d59a1186 --- /dev/null +++ b/board/k+p/bootscripts/tpcboot.cmd @@ -0,0 +1,96 @@ +# +# Copyright (C) 2018 +# Lukasz Majewski, DENX Software Engineering, lukma@denx.de +# +# +# This is an example file to generate boot.scr - a boot script for U-Boot +# Generate boot.scr: +# ./tools/mkimage -c none -A arm -T script -d tpcboot.cmd boot.scr +# +# SPDX-License-Identifier: GPL-2.0+ + + +# Input envs (to be set in environment) +# Mandatory: +# kernel_file = "fitImage" +# boardname = "XXXX" // set automatically in u-boot +# boardsoc = "imx6q" // set automatically in u-boot +# +# Optional: +# bootcmd_force = "nfs" "tftp_kernel" +# If not set - eMMC/SD boot + +# Generic setup +setenv mmcroot "/dev/mmcblk${devnum}p2 rootwait rw" +setenv displayargs "" +setenv mmcargs "setenv bootargs console=${console} ${smp} root=${mmcroot} \ + ${displayargs}" +setenv boot_fitImage " + setenv fdt_conf 'conf@${boardsoc}-${boardname}.dtb'; + setenv itbcfg "\"#\${fdt_conf}\""; + print itbcfg; + bootm '${loadaddr}${itbcfg}';" + +#------------------------------------------------------------ +# +# Provide default 'bootcmd' command +#------------------------------------------------------------ +setenv bootcmd " +if test -e ${devtype} ${devnum}:${distro_bootpart} ${kernel_file}; then + echo Found kernel image: ${kernel_file}; + if load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} \ + ${kernel_file}; then + run mmcargs; + run boot_fitImage; + fi; +fi;" + +#------------------------------------------------------------ +# +# Provide 'boot_tftp_kernel' command +#------------------------------------------------------------ +setenv download_kernel "tftpboot ${loadaddr} ${kernel_file}" + +setenv boot_tftp_kernel " +if run download_kernel; then + run mmcargs; + run boot_fitImage; +fi" + +#------------------------------------------------------------ +# +# Provide 'boot_nfs' command +#------------------------------------------------------------ +setenv rootpath "/srv/tftp/KP/rootfs" +setenv nfsargs "setenv bootargs root=/dev/nfs rw \ + nfsroot=${serverip}:${rootpath},nolock,nfsvers=3" +setenv addip "setenv bootargs ${bootargs} \ + ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:\ + ${hostname}:eth0:on" + +setenv boot_nfs " +if run download_kernel; then + run nfsargs; + run addip; + setenv bootargs ${bootargs} console=${console}; + + run boot_fitImage; +fi" + +#------------------------------------------------------------ +# +# Set correct boot flow +#------------------------------------------------------------ + +setenv bcmd " +if test ! -n ${bootcmd_force}; then + run bootcmd; +fi; +if test ${bootcmd_force} = nfs; then + run boot_nfs; +else if test ${bootcmd_force} = tftp_kernel; then + run boot_tftp_kernel; + fi; +fi" + +run bcmd -- cgit v1.2.1 From 723f8359c144eb29f0fb07291f9a2294bd2a3fd6 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 5 Apr 2018 19:46:06 +0100 Subject: imx: mx7: snvs: Add an SNVS init routine Working with HAB on the i.MX7 we've encountered a case where a board that successfully authenticates u-boot when booting Linux via OPTEE subsequently fails to properly bring up the RTC. The RTC registers live in the low-power block of the Secure Non-Volatile Storage (SNVS) block. The root cause of the error has been traced to the HAB handing off the SNVS-RTC in a state where HPCOMR::NPSWA_EN = 0 in other words where the Non-Privileged Software Access Enable bit is zero. In ordinary circumstances this is OK since we typically do not run in TZ mode, however when we boot via HAB and enablng TrustZone, it is required to set HPCOMR::NPSWA_EN = 1 in order for the upstream Linux driver to have sufficient permissions to manipulate the SNVS-LP block. On our reference board it is the difference between Linux doing this: root@imx7s-warp-mbl:~# dmesg | grep rtc snvs_rtc_enable read 0x00000000 from SNVS_LPLR @ 0x00000034 snvs_rtc_enable read 0x00000021 from SNVS_LPCR @ 0x00000038 snvs_rtc_enable read 0x00000000 from SNVS_HPLR @ 0x00000000 snvs_rtc_enable read 0x80002100 from SNVS_HPCOMR @ 0x00000004 snvs_rtc 30370000.snvs:snvs-rtc-lp: rtc core: registered 30370000.snvs:snvs-rtc-lp as rtc0 snvs_rtc 30370000.snvs:snvs-rtc-lp: setting system clock to2018-04-01 00:51:04 UTC (1522543864) and doing this: root@imx7s-warp-mbl:~# dmesg | grep rtc snvs_rtc_enable read 0x00000000 from SNVS_LPLR @ 0x00000034 snvs_rtc_enable read 0x00000020 from SNVS_LPCR @ 0x00000038 snvs_rtc_enable read 0x00000001 from SNVS_HPLR @ 0x00000000 snvs_rtc_enable read 0x00002020 from SNVS_HPCOMR @ 0x00000004 snvs_rtc 30370000.snvs:snvs-rtc-lp: failed to enable rtc -110 snvs_rtc: probe of 30370000.snvs:snvs-rtc-lp failed with error -110 hctosys: unable to open rtc device (rtc0) Note bit 1 of LPCR is not set in the second case and is set in the first case and that bit 31 of HPCOMR is set in the second case but not in the first. Setting NPSWA_EN in HPCOMR allows us to boot through enabling TrustZone and continue onto the kernel. The kernel then has the necessary permissions to set LPCR::SRTC_ENV (RTC enable in the LP command register) whereas in contrast - in the failing case the non-privileged kernel cannot do so. This patch adds a simple init_snvs() call which sets the permission-bit called from soc.c for the i.MX7. It may be possible, safe and desirable to perform this on other i.MX processors but for now this is only tested on i.MX7 as working. Signed-off-by: Bryan O'Donoghue --- arch/arm/include/asm/mach-imx/sys_proto.h | 1 + arch/arm/mach-imx/mx7/Makefile | 2 +- arch/arm/mach-imx/mx7/snvs.c | 22 ++++++++++++++++++++++ arch/arm/mach-imx/mx7/soc.c | 2 ++ 4 files changed, 26 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-imx/mx7/snvs.c diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 96795e1814..aa51c0d786 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -107,6 +107,7 @@ void set_chipselect_size(int const); void init_aips(void); void init_src(void); +void init_snvs(void); void imx_wdog_disable_powerdown(void); int board_mmc_get_env_dev(int devno); diff --git a/arch/arm/mach-imx/mx7/Makefile b/arch/arm/mach-imx/mx7/Makefile index ce289c1415..e6bef6acee 100644 --- a/arch/arm/mach-imx/mx7/Makefile +++ b/arch/arm/mach-imx/mx7/Makefile @@ -5,7 +5,7 @@ # # -obj-y := soc.o clock.o clock_slice.o ddr.o +obj-y := soc.o clock.o clock_slice.o ddr.o snvs.o ifdef CONFIG_ARMV7_PSCI obj-y += psci-mx7.o psci.o diff --git a/arch/arm/mach-imx/mx7/snvs.c b/arch/arm/mach-imx/mx7/snvs.c new file mode 100644 index 0000000000..7e649b8513 --- /dev/null +++ b/arch/arm/mach-imx/mx7/snvs.c @@ -0,0 +1,22 @@ +/* + * Copyright 2018 Linaro + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define SNVS_HPCOMR 0x04 +#define SNVS_HPCOMR_NPSWA_EN BIT(31) + +void init_snvs(void) +{ + u32 val; + + /* Ensure SNVS HPCOMR sets NPSWA_EN to allow unpriv access to SNVS LP */ + val = readl(SNVS_BASE_ADDR + SNVS_HPCOMR); + val |= SNVS_HPCOMR_NPSWA_EN; + writel(val, SNVS_BASE_ADDR + SNVS_HPCOMR); +} diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index fb92a26e45..3ceeeffd99 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -180,6 +180,8 @@ int arch_cpu_init(void) isolate_resource(); #endif + init_snvs(); + return 0; } -- cgit v1.2.1 From ebca6013c086356419a462dc1adbef858a5ada67 Mon Sep 17 00:00:00 2001 From: Vanessa Maegima Date: Fri, 6 Apr 2018 16:54:41 -0300 Subject: pico-imx7d: Replace fatload command Replace fatload with the fs generic loading interface ('load' command). Signed-off-by: Vanessa Maegima Reviewed-by: Fabio Estevam --- configs/pico-imx7d_defconfig | 1 + include/configs/pico-imx7d.h | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index edfe7257bd..b85486db4e 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -22,6 +22,7 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y CONFIG_PHYLIB=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index ee48363590..a81548cb00 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -50,8 +50,8 @@ "finduuid=part uuid mmc 0:2 uuid\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=PARTUUID=${uuid} rootwait rw\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run finduuid; " \ "run mmcargs; " \ -- cgit v1.2.1 From bcca8aa9ee43be0f0bf7c14ce34cfbbd891c373e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 6 Apr 2018 16:27:54 -0400 Subject: imx31_phycore: Delete This platform has been marked as orphaned since September 2013, remove. Signed-off-by: Tom Rini --- arch/arm/Kconfig | 12 --- board/imx31_phycore/Kconfig | 12 --- board/imx31_phycore/MAINTAINERS | 11 --- board/imx31_phycore/Makefile | 9 --- board/imx31_phycore/imx31_phycore.c | 154 ----------------------------------- board/imx31_phycore/lowlevel_init.S | 88 -------------------- configs/imx31_phycore_defconfig | 19 ----- configs/imx31_phycore_eet_defconfig | 25 ------ drivers/video/Makefile | 1 - drivers/video/s6e63d6.c | 60 -------------- include/configs/imx31_phycore.h | 156 ------------------------------------ include/s6e63d6.h | 21 ----- 12 files changed, 568 deletions(-) delete mode 100644 board/imx31_phycore/Kconfig delete mode 100644 board/imx31_phycore/MAINTAINERS delete mode 100644 board/imx31_phycore/Makefile delete mode 100644 board/imx31_phycore/imx31_phycore.c delete mode 100644 board/imx31_phycore/lowlevel_init.S delete mode 100644 configs/imx31_phycore_defconfig delete mode 100644 configs/imx31_phycore_eet_defconfig delete mode 100644 drivers/video/s6e63d6.c delete mode 100644 include/configs/imx31_phycore.h delete mode 100644 include/s6e63d6.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2c52ff025a..056dacc16f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -444,17 +444,6 @@ config TARGET_X600 select SUPPORT_SPL select PL011_SERIAL -config TARGET_IMX31_PHYCORE - bool "Support imx31_phycore_eet" - select CPU_ARM1136 - select BOARD_EARLY_INIT_F - -config TARGET_IMX31_PHYCORE_EET - bool "Support imx31_phycore_eet" - select BOARD_LATE_INIT - select CPU_ARM1136 - select BOARD_EARLY_INIT_F - config TARGET_MX31ADS bool "Support mx31ads" select CPU_ARM1136 @@ -1317,7 +1306,6 @@ source "board/gumstix/pepper/Kconfig" source "board/h2200/Kconfig" source "board/hisilicon/hikey/Kconfig" source "board/hisilicon/poplar/Kconfig" -source "board/imx31_phycore/Kconfig" source "board/isee/igep003x/Kconfig" source "board/phytec/pcm051/Kconfig" source "board/silica/pengwyn/Kconfig" diff --git a/board/imx31_phycore/Kconfig b/board/imx31_phycore/Kconfig deleted file mode 100644 index e897ee1c3a..0000000000 --- a/board/imx31_phycore/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_IMX31_PHYCORE || TARGET_IMX31_PHYCORE_EET - -config SYS_BOARD - default "imx31_phycore" - -config SYS_SOC - default "mx31" - -config SYS_CONFIG_NAME - default "imx31_phycore" - -endif diff --git a/board/imx31_phycore/MAINTAINERS b/board/imx31_phycore/MAINTAINERS deleted file mode 100644 index 41f6cae81b..0000000000 --- a/board/imx31_phycore/MAINTAINERS +++ /dev/null @@ -1,11 +0,0 @@ -IMX31_PHYCORE BOARD -#M: - -S: Maintained -F: board/imx31_phycore/ -F: include/configs/imx31_phycore.h -F: configs/imx31_phycore_defconfig - -IMX31_PHYCORE_EET BOARD -#M: (resigned) Guennadi Liakhovetski -S: Orphan (since 2013-09) -F: configs/imx31_phycore_eet_defconfig diff --git a/board/imx31_phycore/Makefile b/board/imx31_phycore/Makefile deleted file mode 100644 index e781c13936..0000000000 --- a/board/imx31_phycore/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := imx31_phycore.o -obj-y += lowlevel_init.o diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c deleted file mode 100644 index 653246615f..0000000000 --- a/board/imx31_phycore/imx31_phycore.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - return 0; -} - -int board_init(void) -{ - - gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */ - gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ - - return 0; -} - -int board_early_init_f(void) -{ - /* CS0: Nor Flash */ - static const struct mxc_weimcs cs0 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) - }; - - /* CS1: Network Controller */ - static const struct mxc_weimcs cs1 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) - }; - - /* CS4: SRAM */ - static const struct mxc_weimcs cs4 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) - }; - - mxc_setup_weimcs(0, &cs0); - mxc_setup_weimcs(1, &cs1); - mxc_setup_weimcs(4, &cs4); - - /* setup pins for UART1 */ - mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); - mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); - mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); - mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); - - /* setup pins for I2C2 (for EEPROM, RTC) */ - mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL); - mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA); - - return 0; -} - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ -#ifdef CONFIG_S6E63D6 - struct s6e63d6 data = { - /* - * See comment in mxc_spi.c::decode_cs() for .cs field format. - * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect - * 2 of the SPI controller #1, since it is unused. - */ - .cs = 2 | (57 << 8), - .bus = 0, - .id = 0, - }; - int ret; - - /* SPI1 */ - mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK); - mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B); - mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI); - mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO); - mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B); - mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B); - mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B); - - /* start SPI1 clock */ - __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2); - - /* GPIO 57 */ - /* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */ - mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO)); - - /* SPI1 CS2 is free */ - ret = s6e63d6_init(&data); - if (ret) - return ret; - - /* - * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC - * OLED display connected to a S6E63D6 SPI display controller in the - * 18 bit RGB mode - */ - s6e63d6_index(&data, 2); - s6e63d6_param(&data, 0x0182); - s6e63d6_index(&data, 3); - s6e63d6_param(&data, 0x8130); - s6e63d6_index(&data, 0x10); - s6e63d6_param(&data, 0x0000); - s6e63d6_index(&data, 5); - s6e63d6_param(&data, 0x0001); - s6e63d6_index(&data, 0x22); -#endif - return 0; -} -#endif - -int checkboard (void) -{ - printf("Board: Phytec phyCore i.MX31\n"); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/board/imx31_phycore/lowlevel_init.S b/board/imx31_phycore/lowlevel_init.S deleted file mode 100644 index 6ea3878ef9..0000000000 --- a/board/imx31_phycore/lowlevel_init.S +++ /dev/null @@ -1,88 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -.macro REG reg, val - ldr r2, =\reg - ldr r3, =\val - str r3, [r2] -.endm - -.macro REG8 reg, val - ldr r2, =\reg - ldr r3, =\val - strb r3, [r2] -.endm - -.macro DELAY loops - ldr r2, =\loops -1: - subs r2, r2, #1 - nop - bcs 1b -.endm - -.globl lowlevel_init -lowlevel_init: - - REG IPU_CONF, IPU_CONF_DI_EN - REG CCM_CCMR, 0x074B0BF5 - - DELAY 0x40000 - - REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE - REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS - - REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0) - - REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd) - - REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1) - - REG 0x43FAC26C, 0 /* SDCLK */ - REG 0x43FAC270, 0 /* CAS */ - REG 0x43FAC274, 0 /* RAS */ - REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */ - REG 0x43FAC284, 0 /* DQM3 */ - REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ - REG 0x43FAC28C, 0 - REG 0x43FAC290, 0 - REG 0x43FAC294, 0 - REG 0x43FAC298, 0 - REG 0x43FAC29C, 0 - REG 0x43FAC2A0, 0 - REG 0x43FAC2A4, 0 - REG 0x43FAC2A8, 0 - REG 0x43FAC2AC, 0 - REG 0x43FAC2B0, 0 - REG 0x43FAC2B4, 0 - REG 0x43FAC2B8, 0 - REG 0x43FAC2BC, 0 - REG 0x43FAC2C0, 0 - REG 0x43FAC2C4, 0 - REG 0x43FAC2C8, 0 - REG 0x43FAC2CC, 0 - REG 0x43FAC2D0, 0 - REG 0x43FAC2D4, 0 - REG 0x43FAC2D8, 0 - REG 0x43FAC2DC, 0 - REG 0xB8001010, 0x00000004 - REG 0xB8001004, 0x006ac73a - REG 0xB8001000, 0x92100000 - REG 0x80000f00, 0x12344321 - REG 0xB8001000, 0xa2100000 - REG 0x80000000, 0x12344321 - REG 0x80000000, 0x12344321 - REG 0xB8001000, 0xb2100000 - REG8 0x80000033, 0xda - REG8 0x81000000, 0xff - REG 0xB8001000, 0x82226080 - REG 0x80000000, 0xDEADBEEF - REG 0xB8001010, 0x0000000c - - mov pc, lr diff --git a/configs/imx31_phycore_defconfig b/configs/imx31_phycore_defconfig deleted file mode 100644 index bd5717bb89..0000000000 --- a/configs/imx31_phycore_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_IMX31_PHYCORE=y -CONFIG_SYS_TEXT_BASE=0xA0000000 -CONFIG_BOOTDELAY=3 -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="uboot> " -CONFIG_CMD_IMLS=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_PING=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=physmap-flash.0:128k(uboot)ro,1536k(kernel),-(root)" -CONFIG_ENV_IS_IN_EEPROM=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_NETDEVICES=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0xa8000000 -CONFIG_SMC911X_32_BIT=y diff --git a/configs/imx31_phycore_eet_defconfig b/configs/imx31_phycore_eet_defconfig deleted file mode 100644 index 7be4f899a8..0000000000 --- a/configs/imx31_phycore_eet_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_IMX31_PHYCORE_EET=y -CONFIG_SYS_TEXT_BASE=0xA0000000 -CONFIG_BOOTDELAY=3 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=physmap-flash.0:128k(uboot)ro,1536k(kernel),-(root)" -CONFIG_ENV_IS_IN_EEPROM=y -CONFIG_MXC_GPIO=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_NETDEVICES=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0xa8000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_MXC_SPI=y -CONFIG_VIDEO=y diff --git a/drivers/video/Makefile b/drivers/video/Makefile index dfafe08fc5..ab897e145c 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -30,7 +30,6 @@ obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o obj-$(CONFIG_PXA_LCD) += pxa_lcd.o obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o obj-$(CONFIG_S6E8AX0) += s6e8ax0.o -obj-$(CONFIG_S6E63D6) += s6e63d6.o obj-$(CONFIG_LD9040) += ld9040.o obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o diff --git a/drivers/video/s6e63d6.c b/drivers/video/s6e63d6.c deleted file mode 100644 index f077260d76..0000000000 --- a/drivers/video/s6e63d6.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2009 - * Guennadi Liakhovetski, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include - -/* - * Each transfer is performed as: - * 1. chip-select active - * 2. send 8-bit start code - * 3. send 16-bit data - * 4. chip-select inactive - */ -static int send_word(struct s6e63d6 *data, u8 rs, u16 word) -{ - /* - * The start byte looks like (binary): - * 01110 - * RS is 0 for index or 1 for data, and R/W is 0 for write. - */ - u32 buf8 = 0x70 | data->id | (rs & 2); - u32 buf16 = cpu_to_le16(word); - u32 buf_in; - int err; - - err = spi_xfer(data->slave, 8, &buf8, &buf_in, SPI_XFER_BEGIN); - if (err) - return err; - - return spi_xfer(data->slave, 16, &buf16, &buf_in, SPI_XFER_END); -} - -/* Index and param differ in Register Select bit */ -int s6e63d6_index(struct s6e63d6 *data, u8 idx) -{ - return send_word(data, 0, idx); -} - -int s6e63d6_param(struct s6e63d6 *data, u16 param) -{ - return send_word(data, 2, param); -} - -int s6e63d6_init(struct s6e63d6 *data) -{ - if (data->id != 0 && data->id != 4) { - printf("s6e63d6: invalid ID %u\n", data->id); - return 1; - } - - data->slave = spi_setup_slave(data->bus, data->cs, 100000, SPI_MODE_3); - if (!data->slave) - return 1; - - return 0; -} diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h deleted file mode 100644 index 3b5eb4fa6c..0000000000 --- a/include/configs/imx31_phycore.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments. - * Richard Woodruff - * Kshitij Gupta - * - * Configuration settings for the phyCORE-i.MX31 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* High Level Configuration Options */ -#define CONFIG_MX31 /* This is a mx31 */ -#define CONFIG_MX31_CLK32 32000 - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) - -/* - * Hardware drivers - */ - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 - -/*********************************************************** - * Command definition - ***********************************************************/ - -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.23.168 -#define CONFIG_SERVERIP 192.168.23.2 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \ - "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ - "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ - "bootargs_flash=setenv bootargs $(bootargs) " \ - "root=/dev/mtdblock2 rootfstype=jffs2\0" \ - "bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \ - "bootcmd=run bootcmd_net\0" \ - "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;" \ - "tftpboot 0x80000000 $(uimage);bootm\0" \ - "bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;" \ - "bootm 0x80000000\0" \ - "unlock=yes\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "prg_uboot=tftpboot 0x80000000 $(uboot);" \ - "protect off 0xa0000000 +0x20000;" \ - "erase 0xa0000000 +0x20000;" \ - "cp.b 0x80000000 0xa0000000 $(filesize)\0" \ - "prg_kernel=tftpboot 0x80000000 $(uimage);" \ - "erase 0xa0040000 +0x180000;" \ - "cp.b 0x80000000 0xa0040000 $(filesize)\0" \ - "prg_jffs2=tftpboot 0x80000000 $(jffs2);" \ - "erase 0xa01c0000 0xa1ffffff;" \ - "cp.b 0x80000000 0xa01c0000 $(filesize)\0" \ - "videomode=video=ctfb:x:240,y:320,depth:16,mode:0," \ - "pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1," \ - "sync:1241513985,vmode:0\0" - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x10000 - -#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */ - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE 0xa0000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max # of sectors/chip */ -/* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_ENV_OFFSET 0x00 /* env. starts here */ -#define CONFIG_ENV_SIZE 4096 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10 ms delay */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* byte addr. lenght */ - -/* - * CFI FLASH driver setup - */ -#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/mtd/cfi_flash.c */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */ - -/* - * Timeout for Flash Erase and Flash Write - * timeout values are in ticks - */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) - -/* - * JFFS2 partitions - */ -#define CONFIG_JFFS2_DEV "nor0" - -/* EET platform additions */ -#ifdef CONFIG_TARGET_IMX31_PHYCORE_EET -#define CONFIG_HARD_SPI - -#define CONFIG_S6E63D6 - -#define CONFIG_VIDEO_MX3 -#define CONFIG_VIDEO_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_BMP_16BPP -#endif - -#endif /* __CONFIG_H */ diff --git a/include/s6e63d6.h b/include/s6e63d6.h deleted file mode 100644 index aa583eed1b..0000000000 --- a/include/s6e63d6.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2009 - * Guennadi Liakhovetski, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _S6E63D6_H_ -#define _S6E63D6_H_ - -struct s6e63d6 { - unsigned int bus; - unsigned int cs; - unsigned int id; - struct spi_slave *slave; -}; - -extern int s6e63d6_init(struct s6e63d6 *data); -extern int s6e63d6_index(struct s6e63d6 *data, u8 idx); -extern int s6e63d6_param(struct s6e63d6 *data, u16 param); - -#endif -- cgit v1.2.1 From 448fc44fb87cb678594541c6695f49debb5c1be3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 6 Apr 2018 16:27:55 -0400 Subject: mx31ads: Delete This platform has been marked as orphaned since September 2013, remove. Signed-off-by: Tom Rini --- arch/arm/Kconfig | 6 - board/freescale/mx31ads/Kconfig | 15 -- board/freescale/mx31ads/MAINTAINERS | 6 - board/freescale/mx31ads/Makefile | 8 - board/freescale/mx31ads/lowlevel_init.S | 268 -------------------------------- board/freescale/mx31ads/mx31ads.c | 114 -------------- board/freescale/mx31ads/u-boot.lds | 110 ------------- configs/mx31ads_defconfig | 15 -- include/configs/mx31ads.h | 145 ----------------- 9 files changed, 687 deletions(-) delete mode 100644 board/freescale/mx31ads/Kconfig delete mode 100644 board/freescale/mx31ads/MAINTAINERS delete mode 100644 board/freescale/mx31ads/Makefile delete mode 100644 board/freescale/mx31ads/lowlevel_init.S delete mode 100644 board/freescale/mx31ads/mx31ads.c delete mode 100644 board/freescale/mx31ads/u-boot.lds delete mode 100644 configs/mx31ads_defconfig delete mode 100644 include/configs/mx31ads.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 056dacc16f..49bcf99520 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -444,11 +444,6 @@ config TARGET_X600 select SUPPORT_SPL select PL011_SERIAL -config TARGET_MX31ADS - bool "Support mx31ads" - select CPU_ARM1136 - select BOARD_EARLY_INIT_F - config TARGET_MX31PDK bool "Support mx31pdk" select BOARD_LATE_INIT @@ -1296,7 +1291,6 @@ source "board/freescale/ls1046ardb/Kconfig" source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/ls1012ardb/Kconfig" source "board/freescale/ls1012afrdm/Kconfig" -source "board/freescale/mx31ads/Kconfig" source "board/freescale/mx31pdk/Kconfig" source "board/freescale/mx35pdk/Kconfig" source "board/freescale/s32v234evb/Kconfig" diff --git a/board/freescale/mx31ads/Kconfig b/board/freescale/mx31ads/Kconfig deleted file mode 100644 index eeeb6f490f..0000000000 --- a/board/freescale/mx31ads/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX31ADS - -config SYS_BOARD - default "mx31ads" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "mx31" - -config SYS_CONFIG_NAME - default "mx31ads" - -endif diff --git a/board/freescale/mx31ads/MAINTAINERS b/board/freescale/mx31ads/MAINTAINERS deleted file mode 100644 index 5f6ec268c7..0000000000 --- a/board/freescale/mx31ads/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX31ADS BOARD -#M: (resigned) Guennadi Liakhovetski -S: Orphan (since 2013-09) -F: board/freescale/mx31ads/ -F: include/configs/mx31ads.h -F: configs/mx31ads_defconfig diff --git a/board/freescale/mx31ads/Makefile b/board/freescale/mx31ads/Makefile deleted file mode 100644 index 5e1440d596..0000000000 --- a/board/freescale/mx31ads/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (C) 2008, Guennadi Liakhovetski -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mx31ads.o -obj-y += lowlevel_init.o diff --git a/board/freescale/mx31ads/lowlevel_init.S b/board/freescale/mx31ads/lowlevel_init.S deleted file mode 100644 index fcb5549d77..0000000000 --- a/board/freescale/mx31ads/lowlevel_init.S +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Copyright (C) 2008, Guennadi Liakhovetski - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -.macro REG reg, val - ldr r2, =\reg - ldr r3, =\val - str r3, [r2] -.endm - -.macro REG8 reg, val - ldr r2, =\reg - ldr r3, =\val - strb r3, [r2] -.endm - -.macro DELAY loops - ldr r2, =\loops -1: - subs r2, r2, #1 - nop - bcs 1b -.endm - -/* RedBoot: AIPS setup - Only setup MPROTx registers. - * The PACR default values are good.*/ -.macro init_aips - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - ldr r0, =0x43F00000 - ldr r1, =0x77777777 - str r1, [r0, #0x00] - str r1, [r0, #0x04] - ldr r0, =0x53F00000 - str r1, [r0, #0x00] - str r1, [r0, #0x04] - - /* - * Clear the on and off peripheral modules Supervisor Protect bit - * for SDMA to access them. Did not change the AIPS control registers - * (offset 0x20) access type - */ - ldr r0, =0x43F00000 - ldr r1, =0x0 - str r1, [r0, #0x40] - str r1, [r0, #0x44] - str r1, [r0, #0x48] - str r1, [r0, #0x4C] - ldr r1, [r0, #0x50] - and r1, r1, #0x00FFFFFF - str r1, [r0, #0x50] - - ldr r0, =0x53F00000 - ldr r1, =0x0 - str r1, [r0, #0x40] - str r1, [r0, #0x44] - str r1, [r0, #0x48] - str r1, [r0, #0x4C] - ldr r1, [r0, #0x50] - and r1, r1, #0x00FFFFFF - str r1, [r0, #0x50] -.endm /* init_aips */ - -/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */ -.macro init_max - ldr r0, =0x43F04000 - /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ - ldr r1, =0x00302154 - str r1, [r0, #0x000] /* for S0 */ - str r1, [r0, #0x100] /* for S1 */ - str r1, [r0, #0x200] /* for S2 */ - str r1, [r0, #0x300] /* for S3 */ - str r1, [r0, #0x400] /* for S4 */ - /* SGPCR - always park on last master */ - ldr r1, =0x10 - str r1, [r0, #0x010] /* for S0 */ - str r1, [r0, #0x110] /* for S1 */ - str r1, [r0, #0x210] /* for S2 */ - str r1, [r0, #0x310] /* for S3 */ - str r1, [r0, #0x410] /* for S4 */ - /* MGPCR - restore default values */ - ldr r1, =0x0 - str r1, [r0, #0x800] /* for M0 */ - str r1, [r0, #0x900] /* for M1 */ - str r1, [r0, #0xA00] /* for M2 */ - str r1, [r0, #0xB00] /* for M3 */ - str r1, [r0, #0xC00] /* for M4 */ - str r1, [r0, #0xD00] /* for M5 */ -.endm /* init_max */ - -/* RedBoot: M3IF setup */ -.macro init_m3if - /* Configure M3IF registers */ - ldr r1, =0xB8003000 - /* - * M3IF Control Register (M3IFCTL) - * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 - * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 - * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 - * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 - * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 - * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 - * ------------ - * 0x00000040 - */ - ldr r0, =0x00000040 - str r0, [r1] /* M3IF control reg */ -.endm /* init_m3if */ - -/* RedBoot: To support 133MHz DDR */ -.macro init_drive_strength - /* - * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits - * in SW_PAD_CTL registers - */ - - /* SDCLK */ - ldr r1, =0x43FAC200 - ldr r0, [r1, #0x6C] - bic r0, r0, #(1 << 12) - str r0, [r1, #0x6C] - - /* CAS */ - ldr r0, [r1, #0x70] - bic r0, r0, #(1 << 22) - str r0, [r1, #0x70] - - /* RAS */ - ldr r0, [r1, #0x74] - bic r0, r0, #(1 << 2) - str r0, [r1, #0x74] - - /* CS2 (CSD0) */ - ldr r0, [r1, #0x7C] - bic r0, r0, #(1 << 22) - str r0, [r1, #0x7C] - - /* DQM3 */ - ldr r0, [r1, #0x84] - bic r0, r0, #(1 << 22) - str r0, [r1, #0x84] - - /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ - ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */ -pad_loop: - ldr r0, [r1, #0x88] - bic r0, r0, #(1 << 22) - bic r0, r0, #(1 << 12) - bic r0, r0, #(1 << 2) - str r0, [r1, #0x88] - add r1, r1, #4 - subs r2, r2, #0x1 - bne pad_loop -.endm /* init_drive_strength */ - -/* CPLD on CS4 setup */ -.macro init_cs4 - ldr r0, =WEIM_BASE - ldr r1, =0x0000D843 - str r1, [r0, #0x40] - ldr r1, =0x22252521 - str r1, [r0, #0x44] - ldr r1, =0x22220A00 - str r1, [r0, #0x48] -.endm /* init_cs4 */ - -.globl lowlevel_init -lowlevel_init: - - /* Redboot initializes very early AIPS, what for? - * Then it also initializes Multi-Layer AHB Crossbar Switch, - * M3IF */ - /* Also setup the Peripheral Port Remap register inside the core */ - ldr r0, =0x40000015 /* start from AIPS 2GB region */ - mcr p15, 0, r0, c15, c2, 4 - - init_aips - - init_max - - init_m3if - - init_drive_strength - - init_cs4 - - /* Image Processing Unit: */ - /* Too early to switch display on? */ - REG IPU_CONF, IPU_CONF_DI_EN /* Switch on Display Interface */ - /* Clock Control Module: */ - REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */ - - DELAY 0x40000 - - REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */ - REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS /* Switch to MCU PLL */ - - /* PBC CPLD on CS4 */ - mov r1, #CS4_BASE - ldrh r1, [r1, #0x2] - /* Is 27MHz switch set? */ - ands r1, r1, #0x10 - - /* 532-133-66.5 */ - ldr r0, =CCM_BASE - ldr r1, =0xFF871D58 - /* PDR0 */ - str r1, [r0, #0x4] - ldreq r1, MPCTL_PARAM_532 - ldrne r1, MPCTL_PARAM_532_27 - /* MPCTL */ - str r1, [r0, #0x10] - - /* Set UPLL=240MHz, USB=60MHz */ - ldr r1, =0x49FCFE7F - /* PDR1 */ - str r1, [r0, #0x8] - ldreq r1, UPCTL_PARAM_240 - ldrne r1, UPCTL_PARAM_240_27 - /* UPCTL */ - str r1, [r0, #0x14] - /* default CLKO to 1/8 of the ARM core */ - mov r1, #0x000002C0 - add r1, r1, #0x00000006 - /* COSR */ - str r1, [r0, #0x1c] - - /* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */ -/* REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/ - - /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */ -/* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/ - /* Default: 1, 4, 12, 1 */ - REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) - - /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */ - REG 0xB8001010, 0x00000004 - REG 0xB8001004, 0x006ac73a - REG 0xB8001000, 0x92100000 - REG 0x80000f00, 0x12344321 - REG 0xB8001000, 0xa2100000 - REG 0x80000000, 0x12344321 - REG 0x80000000, 0x12344321 - REG 0xB8001000, 0xb2100000 - REG8 0x80000033, 0xda - REG8 0x81000000, 0xff - REG 0xB8001000, 0x82226080 - REG 0x80000000, 0xDEADBEEF - REG 0xB8001010, 0x0000000c - - mov pc, lr - -MPCTL_PARAM_532: - .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0)) -MPCTL_PARAM_532_27: - .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0)) -UPCTL_PARAM_240: - .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0)) -UPCTL_PARAM_240_27: - .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0)) diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c deleted file mode 100644 index ad89cb021d..0000000000 --- a/board/freescale/mx31ads/mx31ads.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (C) 2008, Guennadi Liakhovetski - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - return 0; -} - -int board_early_init_f(void) -{ - int i; - - /* CS0: Nor Flash */ - /* - * CS0L and CS0A values are from the RedBoot sources by Freescale - * and are also equal to those used by Sascha Hauer for the Phytec - * i.MX31 board. CS0U is just a slightly optimized hardware default: - * the only non-zero field "Wait State Control" is set to half the - * default value. - */ - static const struct mxc_weimcs cs0 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) - }; - - mxc_setup_weimcs(0, &cs0); - - /* setup pins for UART1 */ - mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); - mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); - mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); - mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); - - /* SPI2 */ - mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B); - mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); - mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); - mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); - mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); - mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); - mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B); - - /* start SPI2 clock */ - __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); - - /* PBC setup */ - /* Enable UART transceivers also reset the Ethernet/external UART */ - readw(CS4_BASE + 4); - - writew(0x8023, CS4_BASE + 4); - - /* RedBoot also has an empty loop with 100000 iterations here - - * clock doesn't run yet */ - for (i = 0; i < 100000; i++) - ; - - /* Clear the reset, toggle the LEDs */ - writew(0xDF, CS4_BASE + 6); - - /* clock still doesn't run */ - for (i = 0; i < 100000; i++) - ; - - /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */ - readb(CS4_BASE + 8); - readb(CS4_BASE + 7); - readb(CS4_BASE + 8); - readb(CS4_BASE + 7); - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */ - - return 0; -} - -int checkboard(void) -{ - printf("Board: MX31ADS\n"); - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_CS8900 - rc = cs8900_initialize(0, CONFIG_CS8900_BASE); -#endif - return rc; -} -#endif diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds deleted file mode 100644 index 71a63f188e..0000000000 --- a/board/freescale/mx31ads/u-boot.lds +++ /dev/null @@ -1,110 +0,0 @@ -/* - * January 2004 - Changed to support H4 device - * Copyright (c) 2004 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.__image_copy_start) - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - * (.vectors) - arch/arm/cpu/arm1136/start.o (.text*) - board/freescale/mx31ads/built-in.o (.text*) - arch/arm/lib/built-in.o (.text*) - net/built-in.o (.text*) - drivers/mtd/built-in.o (.text*) - - . = DEFINED(env_offset) ? env_offset : .; - env/embedded.o(.text*) - - *(.text*) - } - . = ALIGN(4); - .rodata : { *(.rodata*) } - - . = ALIGN(4); - .data : { - *(.data*) - } - - . = ALIGN(4); - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN(4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - .hash : { *(.hash*) } - - .end : - { - *(.__end) - } - - _image_binary_end = .; - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - .dynsym _image_binary_end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .gnu.hash : { *(.gnu.hash) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } -} diff --git a/configs/mx31ads_defconfig b/configs/mx31ads_defconfig deleted file mode 100644 index 9a4622577c..0000000000 --- a/configs/mx31ads_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_MX31ADS=y -CONFIG_SYS_TEXT_BASE=0xA0000000 -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_MXC_GPIO=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_MXC_SPI=y diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h deleted file mode 100644 index 0fe37c71da..0000000000 --- a/include/configs/mx31ads.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (C) 2008, Guennadi Liakhovetski - * - * Configuration settings for the MX31ADS Freescale board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - - /* High Level Configuration Options */ -#define CONFIG_MX31 1 /* This is a mx31 */ - -#define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) - -/* - * Hardware drivers - */ - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -#define CONFIG_HARD_SPI 1 -#define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) - -/* PMIC Controller */ -#define CONFIG_POWER -#define CONFIG_POWER_SPI -#define CONFIG_POWER_FSL -#define CONFIG_FSL_PMIC_BUS 1 -#define CONFIG_FSL_PMIC_CS 0 -#define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_FSL_PMIC_BITLEN 32 -#define CONFIG_RTC_MC13XXX - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 - -#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot_addr=0xa0000000\0" \ - "uboot=mx31ads/u-boot.bin\0" \ - "kernel=mx31ads/uImage\0" \ - "nfsroot=/opt/eldk/arm\0" \ - "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ - "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "bootcmd=run bootcmd_net\0" \ - "bootcmd_net=run bootargs_base bootargs_nfs; " \ - "tftpboot ${loadaddr} ${kernel}; bootm\0" \ - "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ - "protect off ${uboot_addr} 0xa003ffff; " \ - "erase ${uboot_addr} 0xa003ffff; " \ - "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ - "setenv filesize; saveenv\0" - -#define CONFIG_CS8900 -#define CONFIG_CS8900_BASE 0xb4020300 -#define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */ - -/* - * The MX31ADS board seems to have a hardware "peculiarity" confirmed under - * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A - * controller inverted. The controller is capable of detecting and correcting - * this, but it needs 4 network packets for that. Which means, at startup, you - * will not receive answers to the first 4 packest, unless there have been some - * broadcasts on the network, or your board is on a hub. Reducing the ARP - * timeout from default 5 seconds to 200ms we speed up the initial TFTP - * transfer, should the user wish one, significantly. - */ -#define CONFIG_ARP_TIMEOUT 200UL - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x10000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 CSD0_BASE -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE CS0_BASE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */ - -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/*----------------------------------------------------------------------- - * CFI FLASH driver setup - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ -#define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ - -/* - * JFFS2 partitions - */ -#define CONFIG_JFFS2_DEV "nor0" - -#endif /* __CONFIG_H */ -- cgit v1.2.1 From f916757300c15aa1a3f0ccc98e7abb8a84c97da0 Mon Sep 17 00:00:00 2001 From: Trent Piepho Date: Fri, 6 Apr 2018 17:11:27 -0700 Subject: imx: Create distinct pre-processed mkimage config files Each imx image is created by a separate sub-make and during this process the mkimage config file is run though cpp. The cpp output is to the same file no matter what imx image is being created. This means if two imx images are generated in parallel they will attempt to independently produce the same pre-processed mkimage config file at the same time. Avoid the problem by making the pre-processed config file name unique based on the imx image it will be used in. This way each image will create a unique config file and they won't clobber each other when run in parallel. This should fixed the build bug referenced in b5b0e4e3 ("imximage: Remove failure when no IVT offset is found"). Cc: Breno Lima Cc: Thomas Petazzoni Cc: Fabio Estevam Signed-off-by: Trent Piepho Tested-by: Fabio Estevam --- arch/arm/mach-imx/Makefile | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 95a542fa01..306f779392 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -78,9 +78,11 @@ endif quiet_cmd_cpp_cfg = CFGS $@ cmd_cpp_cfg = $(CPP) $(cpp_flags) -x c -o $@ $< -IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%).cfgtmp +# mkimage source config file +IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%) -$(IMX_CONFIG): %.cfgtmp: % FORCE +# How to create a cpp processed config file, they all use the same source +%.cfgout: $(IMX_CONFIG) FORCE $(Q)mkdir -p $(dir $@) $(call if_changed_dep,cpp_cfg) @@ -88,7 +90,7 @@ MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T imxim -e $(CONFIG_SYS_TEXT_BASE) u-boot.imx: MKIMAGEOUTPUT = u-boot.imx.log -u-boot.imx: u-boot.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE +u-boot.imx: u-boot.bin u-boot.cfgout $(PLUGIN).bin FORCE $(call if_changed,mkimage) ifeq ($(CONFIG_OF_SEPARATE),y) @@ -96,16 +98,15 @@ MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T i -e $(CONFIG_SYS_TEXT_BASE) u-boot-dtb.imx: MKIMAGEOUTPUT = u-boot-dtb.imx.log -u-boot-dtb.imx: u-boot-dtb.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE +u-boot-dtb.imx: u-boot-dtb.bin u-boot-dtb.cfgout $(PLUGIN).bin FORCE $(call if_changed,mkimage) endif MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T imximage \ -e $(CONFIG_SPL_TEXT_BASE) - SPL: MKIMAGEOUTPUT = SPL.log -SPL: spl/u-boot-spl.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE +SPL: spl/u-boot-spl.bin spl/u-boot-spl.cfgout $(PLUGIN).bin FORCE $(call if_changed,mkimage) MKIMAGEFLAGS_u-boot.uim = -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \ @@ -133,7 +134,7 @@ cmd_u-boot-nand-spl_imx = (printf '\000\000\000\000\106\103\102\040\001' && \ spl/u-boot-nand-spl.imx: SPL FORCE $(call if_changed,u-boot-nand-spl_imx) -targets += $(addprefix ../../../,$(IMX_CONFIG) SPL u-boot.uim spl/u-boot-nand-spl.imx) +targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx) obj-$(CONFIG_ARM64) += sip.o -- cgit v1.2.1 From b4e9bdcd05ac83146ad16802a94db3e78f530d1a Mon Sep 17 00:00:00 2001 From: Jon Nettleton Date: Tue, 10 Apr 2018 17:05:35 -0300 Subject: mx6cuboxi: Fix some memory configuration errors These changes bring mainline back into line with the configurations that were originally set in our stable BSP. Signed-off-by: Jon Nettleton Signed-off-by: Fabio Estevam --- board/solidrun/mx6cuboxi/mx6cuboxi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index ee9e4f7c01..727b639943 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -428,7 +428,7 @@ static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = { .dram_sdclk_1 = 0x00020030, .dram_cas = 0x00020030, .dram_ras = 0x00020030, - .dram_reset = 0x00020030, + .dram_reset = 0x000c0030, .dram_sdcke0 = 0x00003000, .dram_sdcke1 = 0x00003000, .dram_sdba2 = 0x00000000, @@ -584,7 +584,6 @@ static struct mx6_ddr3_cfg mem_ddr_2g = { .trcd = 1375, .trcmin = 4875, .trasmin = 3500, - .SRT = 1, }; static struct mx6_ddr3_cfg mem_ddr_4g = { -- cgit v1.2.1