From d58acf644f6e79ff36b990cb2ed4d88541c990df Mon Sep 17 00:00:00 2001 From: Neal Frager Date: Thu, 23 Mar 2023 08:25:06 +0000 Subject: arch: arm: zynqmp: mp.c: tcminit halt both cores in split mode The "zynqmp tcminit split" command should halt both cores and not just RPU1 when configuring the TCM memory for split mode. Signed-off-by: Neal Frager Link: https://lore.kernel.org/r/20230323082506.31576-1-neal.frager@amd.com Signed-off-by: Michal Simek --- arch/arm/mach-zynqmp/mp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index 2891878973..d98c34ea8a 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -247,8 +247,10 @@ void initialize_tcm(bool mode) release_r5_reset(ZYNQMP_CORE_RPU0, LOCK); } else { set_r5_tcm_mode(SPLIT); + set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, SPLIT); set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, SPLIT); enable_clock_r5(); + release_r5_reset(ZYNQMP_CORE_RPU0, SPLIT); release_r5_reset(ZYNQMP_CORE_RPU1, SPLIT); } } -- cgit v1.2.1 From 9c10a69e103d3473c1a43485f81f4e09c3612c74 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 23 Mar 2023 15:52:11 +0100 Subject: xilinx: Enable virtio mmio transport and devices Qemu can create virtio mmio transports and passing devices through it that's why enable virtio by default on all arm64 based SoCs. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/a2ee18e7e8c1881ce72c5cd13127794a02410696.1679583129.git.michal.simek@amd.com --- configs/xilinx_versal_net_virt_defconfig | 5 +++++ configs/xilinx_versal_virt_defconfig | 5 +++++ configs/xilinx_zynqmp_virt_defconfig | 4 ++++ 3 files changed, 14 insertions(+) diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index fb8f86cd69..97904bdec0 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -48,6 +48,7 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y +CONFIG_CMD_RNG=y CONFIG_CMD_TIMER=y CONFIG_CMD_SMC=y CONFIG_CMD_EXT4_WRITE=y @@ -109,6 +110,7 @@ CONFIG_ZYNQ_GEM=y CONFIG_POWER_DOMAIN=y CONFIG_ZYNQMP_POWER_DOMAIN=y CONFIG_RESET_ZYNQMP=y +CONFIG_DM_RNG=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y CONFIG_XILINX_UARTLITE=y @@ -134,3 +136,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x03FD CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_BLK=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 86cfbd6f4f..28fef84c6a 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -48,6 +48,7 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y +CONFIG_CMD_RNG=y CONFIG_CMD_TIMER=y CONFIG_CMD_SMC=y CONFIG_CMD_EXT4_WRITE=y @@ -112,6 +113,7 @@ CONFIG_ZYNQ_GEM=y CONFIG_POWER_DOMAIN=y CONFIG_ZYNQMP_POWER_DOMAIN=y CONFIG_RESET_ZYNQMP=y +CONFIG_DM_RNG=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y CONFIG_XILINX_UARTLITE=y @@ -138,3 +140,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x03FD CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_BLK=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index e1b241f843..df27cd742f 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -91,6 +91,7 @@ CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_RTC=y CONFIG_CMD_TIME=y CONFIG_CMD_GETTIME=y +CONFIG_CMD_RNG=y CONFIG_CMD_TIMER=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_SMC=y @@ -230,6 +231,9 @@ CONFIG_SPLASH_SCREEN=y CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_BLK=y CONFIG_PANIC_HANG=y CONFIG_TPM=y CONFIG_SPL_GZIP=y -- cgit v1.2.1 From 0da6d5a9e2f1d559b4e81e10eec35c9d17025f26 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 28 Mar 2023 09:17:31 +0200 Subject: ARM: zynq: Switch from earlyprintk to earlycon Switch to earlycon which is preffered over earlyprintk. It is also sync with Linux kernel (zynq-microzed). Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/d280fa18068f80412cf12c235c5245651e7062e2.1679987839.git.michal.simek@amd.com --- arch/arm/dts/zynq-dlc20-rev1.0.dts | 2 +- arch/arm/dts/zynq-microzed.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynq-dlc20-rev1.0.dts b/arch/arm/dts/zynq-dlc20-rev1.0.dts index cbf52c88b9..cfe0710229 100644 --- a/arch/arm/dts/zynq-dlc20-rev1.0.dts +++ b/arch/arm/dts/zynq-dlc20-rev1.0.dts @@ -26,7 +26,7 @@ }; chosen { - bootargs = "earlyprintk"; + bootargs = "earlycon"; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts index 875ee080df..b95eb3ed24 100644 --- a/arch/arm/dts/zynq-microzed.dts +++ b/arch/arm/dts/zynq-microzed.dts @@ -23,7 +23,7 @@ }; chosen { - bootargs = "earlyprintk"; + bootargs = "earlycon"; stdout-path = "serial0:115200n8"; }; -- cgit v1.2.1 From 9b4d52b2e16a7862ad969bf0469dc88fcdaa0999 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 28 Mar 2023 09:21:33 +0200 Subject: ARM: zynq: Sync Microzed board with Linux kernel Fix model name, node locations and also add pinctrl description for usb. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/3295fde73db13a712b65f4967eb5f39ced895ad4.1679988091.git.michal.simek@amd.com --- arch/arm/dts/zynq-microzed.dts | 42 +++++++++++++++++++++++++++++++++++------- 1 file changed, 35 insertions(+), 7 deletions(-) diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts index b95eb3ed24..5f280f4d8e 100644 --- a/arch/arm/dts/zynq-microzed.dts +++ b/arch/arm/dts/zynq-microzed.dts @@ -8,7 +8,7 @@ #include "zynq-7000.dtsi" / { - model = "Zynq MicroZED Board"; + model = "Avnet MicroZed board"; compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000"; aliases { @@ -19,7 +19,7 @@ memory@0 { device_type = "memory"; - reg = <0 0x40000000>; + reg = <0x0 0x40000000>; }; chosen { @@ -42,11 +42,6 @@ status = "okay"; }; -&uart1 { - bootph-all; - status = "okay"; -}; - &gem0 { status = "okay"; phy-mode = "rgmii-id"; @@ -62,8 +57,41 @@ status = "okay"; }; +&uart1 { + bootph-all; + status = "okay"; +}; + &usb0 { status = "okay"; dr_mode = "host"; usb-phy = <&usb_phy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; +}; + +&pinctrl0 { + pinctrl_usb0_default: usb0-default { + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + + conf { + groups = "usb0_0_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-rx { + pins = "MIO29", "MIO31", "MIO36"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", + "MIO35", "MIO37", "MIO38", "MIO39"; + bias-disable; + }; + }; }; -- cgit v1.2.1 From 66e8b8128b523f43c86f54dd64075b2cf34b117d Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Wed, 5 Apr 2023 15:06:45 +0200 Subject: arm64: zynqmp: Fix issue of apps executing from R5 core 1 In current implementation, applications can execute only on R5 core 0. The boot address for R5 core 1 is not supplied. Pass TCM address for R5 core 1 based on the argument to fix the issue. Remove incomplete comment. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/da865717d26648ab7a84345ca8749712efdddee5.1680699999.git.michal.simek@amd.com --- arch/arm/mach-zynqmp/mp.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index d98c34ea8a..7a12f4b2b6 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -32,7 +32,8 @@ #define ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK 0x02 #define ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000 -#define ZYNQMP_TCM_START_ADDRESS 0xFFE00000 +#define ZYNQMP_R5_0_TCM_START_ADDR 0xFFE00000 +#define ZYNQMP_R5_1_TCM_START_ADDR 0xFFE90000 #define ZYNQMP_TCM_BOTH_SIZE 0x40000 #define ZYNQMP_CORE_APU0 0 @@ -215,9 +216,14 @@ static void set_r5_start(u8 high) writel(tmp, &rpu_base->rpu1_cfg); } -static void write_tcm_boot_trampoline(u32 boot_addr) +static void write_tcm_boot_trampoline(u32 nr, u32 boot_addr) { if (boot_addr) { + u64 tcm_start_addr = ZYNQMP_R5_0_TCM_START_ADDR; + + if (nr == ZYNQMP_CORE_RPU1) + tcm_start_addr = ZYNQMP_R5_1_TCM_START_ADDR; + /* * Boot trampoline is simple ASM code below. * @@ -229,12 +235,12 @@ static void write_tcm_boot_trampoline(u32 boot_addr) * bx r1 */ debug("Write boot trampoline for %x\n", boot_addr); - writel(0xea000000, ZYNQMP_TCM_START_ADDRESS); - writel(boot_addr, ZYNQMP_TCM_START_ADDRESS + 0x4); - writel(0xe59f0004, ZYNQMP_TCM_START_ADDRESS + 0x8); - writel(0xe5901000, ZYNQMP_TCM_START_ADDRESS + 0xc); - writel(0xe12fff11, ZYNQMP_TCM_START_ADDRESS + 0x10); - writel(0x00000004, ZYNQMP_TCM_START_ADDRESS + 0x14); // address for + writel(0xea000000, tcm_start_addr); + writel(boot_addr, tcm_start_addr + 0x4); + writel(0xe59f0004, tcm_start_addr + 0x8); + writel(0xe5901000, tcm_start_addr + 0xc); + writel(0xe12fff11, tcm_start_addr + 0x10); + writel(0x00000004, tcm_start_addr + 0x14); } } @@ -328,7 +334,7 @@ int cpu_release(u32 nr, int argc, char *const argv[]) enable_clock_r5(); release_r5_reset(nr, LOCK); dcache_disable(); - write_tcm_boot_trampoline(boot_addr_uniq); + write_tcm_boot_trampoline(nr, boot_addr_uniq); dcache_enable(); set_r5_halt_mode(nr, RELEASE, LOCK); mark_r5_used(nr, LOCK); @@ -341,7 +347,7 @@ int cpu_release(u32 nr, int argc, char *const argv[]) enable_clock_r5(); release_r5_reset(nr, SPLIT); dcache_disable(); - write_tcm_boot_trampoline(boot_addr_uniq); + write_tcm_boot_trampoline(nr, boot_addr_uniq); dcache_enable(); set_r5_halt_mode(nr, RELEASE, SPLIT); mark_r5_used(nr, SPLIT); -- cgit v1.2.1 From b250bd6139f7ccbb7c14a8e8f569447dcd3a7225 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 12 Apr 2023 16:30:27 +0200 Subject: arm64: zynqmp: Fix User MTD partition size The commit c8630167e0dc ("arm64: zynqmp: Add mtd partition for secure OS storage area") didn't update User partition size that's why size was beyond actual device size. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/0a56405553b87a75e066cd71697cafe7c1c97eef.1681309812.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sm-k26-revA.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index ed75049741..f6ed047f3d 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -224,7 +224,7 @@ }; partition@22A0000 { label = "User"; - reg = <0x22A0000 0x1db0000>; /* 29.5 MB */ + reg = <0x22A0000 0x1d60000>; /* 29.375 MB */ }; }; }; -- cgit v1.2.1 From e0406f35e1e8964cb0971526f44410991d0c4207 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Thu, 20 Apr 2023 02:56:44 -0600 Subject: arm64: zynqmp: Enable ADIN ethernet phy Some of the Kria SOM and ZynqMP boards are using Analog Devices ethernet phy. So, enable CONFIG_PHY_ADIN for all ZynqMP platforms. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230420085645.21260-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index df27cd742f..c4bbde2206 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -172,6 +172,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ADIN=y CONFIG_PHY_MARVELL=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y -- cgit v1.2.1 From 04d66e76d1624ce0dcc184a007eb2c1583a164e1 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Thu, 20 Apr 2023 02:56:45 -0600 Subject: arm64: versal: Enable ADIN ethernet phy Versal VEK280 board has Analog Devices ethernet phy. So, enable CONFIG_PHY_ADIN config in Versal defconfig. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230420085645.21260-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- configs/xilinx_versal_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 28fef84c6a..a1feafc49b 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -99,6 +99,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ADIN=y CONFIG_PHY_MARVELL=y CONFIG_PHY_NATSEMI=y CONFIG_PHY_REALTEK=y -- cgit v1.2.1 From 99c1abae411d8e4f6ad2ba8b151bfc8ea163c93a Mon Sep 17 00:00:00 2001 From: Stefan Herbrechtsmeier Date: Thu, 27 Apr 2023 08:53:54 +0200 Subject: Revert "spi: zynq_qspi: Use dummy buswidth in dummy byte calculation" This reverts commit e09784728689de7949d4cdd559a9590e0bfcc702. The commit wrongly divides the dummy bytes by dummy bus width to calculate the dummy bytes. The framework already converts the dummy cycles to the number of bytes and the controller use the SPI flash command to determine the dummy cycles via the address width. Signed-off-by: Stefan Herbrechtsmeier Acked-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230427065355.7413-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek --- drivers/spi/zynq_qspi.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index 00e3ffcd1d..d1d4048966 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -676,7 +676,6 @@ static int zynq_qspi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) { int op_len, pos = 0, ret, i; - u32 dummy_bytes = 0; unsigned int flag = 0; const u8 *tx_buf = NULL; u8 *rx_buf = NULL; @@ -689,11 +688,6 @@ static int zynq_qspi_exec_op(struct spi_slave *slave, } op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; - if (op->dummy.nbytes) { - op_len = op->cmd.nbytes + op->addr.nbytes + - op->dummy.nbytes / op->dummy.buswidth; - dummy_bytes = op->dummy.nbytes / op->dummy.buswidth; - } u8 op_buf[op_len]; @@ -707,8 +701,8 @@ static int zynq_qspi_exec_op(struct spi_slave *slave, pos += op->addr.nbytes; } - if (dummy_bytes) - memset(op_buf + pos, 0xff, dummy_bytes); + if (op->dummy.nbytes) + memset(op_buf + pos, 0xff, op->dummy.nbytes); /* 1st transfer: opcode + address + dummy cycles */ /* Make sure to set END bit if no tx or rx data messages follow */ -- cgit v1.2.1 From 0407903e8c5685670be5a2feaae83e06567c0a6e Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Wed, 26 Apr 2023 00:01:03 -0600 Subject: .mailmap: Sort the mailmap ids in dictionary order The mailmap ids are not arranged in the dictionary order. So, sort the mailmap ids in the dictionary order. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230426060104.10412-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- .mailmap | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/.mailmap b/.mailmap index 4b3532ea9c..80076f7206 100644 --- a/.mailmap +++ b/.mailmap @@ -30,26 +30,28 @@ Eugen Hristev Fabio Estevam Heinrich Schuchardt Heinrich Schuchardt xypron.glpk@gmx.de +Igor Opaniuk +Igor Opaniuk Jagan Teki <402jagan@gmail.com> Jagan Teki Jagan Teki Jagan Teki Jagan Teki Jernej Skrabec -Igor Opaniuk -Igor Opaniuk +Lukasz Majewski Marek Behún Marek Behún Marek Behun Marek Vasut Marek Vasut Marek Vasut Markus Klotzbuecher -Masahiro Yamada Masahiro Yamada +Masahiro Yamada Michal Simek -Michal Simek Michal Simek +Michal Simek Michal Simek +Mirza Neil Armstrong Nicolas Saenz Julienne Patrice Chotard @@ -57,8 +59,8 @@ Patrick Delaunay Paul Burton Prabhakar Kushwaha Rajeshwari Shinde -Ricardo Ribalda Ricardo Ribalda +Ricardo Ribalda Ruchika Gupta Sandeep Paulraj Shaohui Xie @@ -66,17 +68,15 @@ Stefan Roese Stefano Babic Tom Rini TsiChung Liew -Wolfgang Denk -Wolfgang Denk -Wolfgang Denk -Wolfgang Denk -Wolfgang Denk Wolfgang Denk Wolfgang Denk -Wolfgang Denk +Wolfgang Denk Wolfgang Denk -York Sun +Wolfgang Denk +Wolfgang Denk +Wolfgang Denk +Wolfgang Denk +Wolfgang Denk York Sun +York Sun Łukasz Majewski -Lukasz Majewski -Mirza -- cgit v1.2.1 From 3f71daa16bf39561984dfbab9b1047e180c9e8ea Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Wed, 26 Apr 2023 00:01:04 -0600 Subject: .mailmap: Map all Xilinx users mail ids to AMD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The mail ids of all the current Xilinx users are to be mapped to AMD following the merger with AMD. The mailmap file is updated accordingly. The ids of Marek Behún and Michal Simek are taken as reference. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230426060104.10412-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- .mailmap | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 52 insertions(+), 3 deletions(-) diff --git a/.mailmap b/.mailmap index 80076f7206..312a428dc9 100644 --- a/.mailmap +++ b/.mailmap @@ -17,27 +17,47 @@ Alexander Graf Allen Martin +Amanda Baze +Amit Kumar Mahapatra Andreas Bießmann Andreas Bießmann Aneesh V Anup Patel +Anurag Kumar Vulisha +Appana Durga Kedareswara rao +Ashok Reddy Soma Atish Patra +Bharat Kumar Gogada +Bharat Kumar Gogada +Bhargava Sreekantappa Gayathri Bin Meng Boris Brezillon Boris Brezillon +Christian Kohn Dirk Behme +Durga Challa Eugen Hristev Fabio Estevam +Harini Katakam +Harsha Heinrich Schuchardt Heinrich Schuchardt xypron.glpk@gmx.de +Ibai Erkiaga Igor Opaniuk Igor Opaniuk +Izhar Ameer Shaikh Jagan Teki <402jagan@gmail.com> Jagan Teki Jagan Teki Jagan Teki Jagan Teki +Jay Buddhabhatti Jernej Skrabec +John Linn +Jyotheeswar Reddy Mutthareddyvari +Jyotheeswar Reddy Mutthareddyvari +Kalyani Akula +Love Kumar Lukasz Majewski Marek Behún Marek Behún Marek Behun @@ -47,27 +67,56 @@ Marek Vasut Markus Klotzbuecher Masahiro Yamada Masahiro Yamada +Michal Simek Michal Simek -Michal Simek -Michal Simek -Michal Simek +Michal Simek +Michal Simek Mirza +Mounika Grace Akula +Mubin Usman Sayyed +Nathalie Chan King Choy +Nathalie Chan King Choy +Nava kishore Manne +Neal Frager Neil Armstrong Nicolas Saenz Julienne Patrice Chotard Patrick Delaunay Paul Burton +Piyush Mehta Prabhakar Kushwaha +Punnaiah Choudary Kalluri +Radhey Shyam Pandey Rajeshwari Shinde +Raju Kumar Pothuraju +Ravi Patel Ricardo Ribalda Ricardo Ribalda +Rohit Visavalia Ruchika Gupta +Saeed Nowshadi +Sai Krishna Potthuri +Sai Pavan Boddu +Sandeep Gundlupet Raju Sandeep Paulraj +Sandeep Reddy Ghanapuram Shaohui Xie +Shravya Kumbham +Shubhrajyoti Datta +Siva Durga Prasad Paladugu +Siva Durga Prasad Paladugu +Srinivas Goud +Srinivas Neeli Stefan Roese Stefano Babic +Stefano Stabellini Tom Rini +Tomas Thoresen TsiChung Liew +Varalaxmi Bingi +Venkatesh Yadav Abbarapu +Vikhyat Goyal +Vishal Patel Wolfgang Denk Wolfgang Denk Wolfgang Denk -- cgit v1.2.1