From 9c76df518cf419a9d7db89c85627049c5d11520f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 2 Aug 2015 16:55:45 +0200 Subject: ddr: altera: sequencer: Move qts-generated files to board dir Move the files generated by QTS into the board directory, they should not be part of the driver files at all. Signed-off-by: Marek Vasut Acked-by: Dinh Nguyen --- board/altera/socfpga/qts/sequencer_auto.h | 128 ++++++++++ board/altera/socfpga/qts/sequencer_auto_ac_init.h | 84 +++++++ .../altera/socfpga/qts/sequencer_auto_inst_init.h | 268 +++++++++++++++++++++ board/altera/socfpga/qts/sequencer_defines.h | 121 ++++++++++ drivers/ddr/altera/sequencer.c | 13 +- drivers/ddr/altera/sequencer_auto.h | 128 ---------- drivers/ddr/altera/sequencer_auto_ac_init.h | 84 ------- drivers/ddr/altera/sequencer_auto_inst_init.h | 268 --------------------- drivers/ddr/altera/sequencer_defines.h | 121 ---------- 9 files changed, 610 insertions(+), 605 deletions(-) create mode 100644 board/altera/socfpga/qts/sequencer_auto.h create mode 100644 board/altera/socfpga/qts/sequencer_auto_ac_init.h create mode 100644 board/altera/socfpga/qts/sequencer_auto_inst_init.h create mode 100644 board/altera/socfpga/qts/sequencer_defines.h delete mode 100644 drivers/ddr/altera/sequencer_auto.h delete mode 100644 drivers/ddr/altera/sequencer_auto_ac_init.h delete mode 100644 drivers/ddr/altera/sequencer_auto_inst_init.h delete mode 100644 drivers/ddr/altera/sequencer_defines.h diff --git a/board/altera/socfpga/qts/sequencer_auto.h b/board/altera/socfpga/qts/sequencer_auto.h new file mode 100644 index 0000000000..0c5d83bbdf --- /dev/null +++ b/board/altera/socfpga/qts/sequencer_auto.h @@ -0,0 +1,128 @@ +/* + * Copyright Altera Corporation (C) 2012-2015 + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#define RW_MGR_READ_B2B_WAIT2 0x6A +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31 +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_ZQCL 0x06 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23 +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_INIT_RESET_0_CKE_0 0x6E +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_MRS2 0x04 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34 +#define RW_MGR_MRS1 0x03 +#ifdef CONFIG_SOCFPGA_ARRIA5 +/* The if..else... is not required if generated by tools */ +#define RW_MGR_IDLE_LOOP1 0x7A +#else +#define RW_MGR_IDLE_LOOP1 0x7C +#endif /* CONFIG_SOCFPGA_ARRIA5 */ +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18 +#define RW_MGR_MRS3 0x05 +#ifdef CONFIG_SOCFPGA_ARRIA5 +/* The if..else... is not required if generated by tools */ +#define RW_MGR_IDLE_LOOP2 0x79 +#else +#define RW_MGR_IDLE_LOOP2 0x7B +#endif /* CONFIG_SOCFPGA_ARRIA5 */ +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C +#ifdef CONFIG_SOCFPGA_ARRIA5 +/* The if..else... is not required if generated by tools */ +#define RW_MGR_RDIMM_CMD 0x78 +#else +#define RW_MGR_RDIMM_CMD 0x7A +#endif /* CONFIG_SOCFPGA_ARRIA5 */ +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38 +#define RW_MGR_GUARANTEED_READ_CONT 0x53 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_IDLE 0x00 +#define RW_MGR_READ_B2B 0x58 +#define RW_MGR_INIT_RESET_0_CKE_0_inloop 0x6F +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37 +#define RW_MGR_GUARANTEED_WRITE 0x17 +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74 +#ifdef CONFIG_SOCFPGA_ARRIA5 +/* The if..else... is not required if generated by tools */ +#define RW_MGR_SGLE_READ 0x7C +#else +#define RW_MGR_SGLE_READ 0x7E +#endif /* CONFIG_SOCFPGA_ARRIA5 */ +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_RETURN 0x01 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_GUARANTEED_READ 0x4B +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_INIT_RESET_1_CKE_0 0x73 +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_LFSR_WR_RD_BANK_0 0x21 +#define RW_MGR_CLEAR_DQS_ENABLE 0x48 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_READ_B2B_WAIT1 0x60 +#define RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680 +#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680 +#define RW_MGR_CONTENT_REFRESH_ALL 0x000980 +#define RW_MGR_CONTENT_ZQCL 0x008380 +#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700 +#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00 +#define RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800 +#define RW_MGR_CONTENT_MRS2_MIRR 0x008580 +#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000 +#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680 +#define RW_MGR_CONTENT_ACTIVATE_1 0x000880 +#define RW_MGR_CONTENT_MRS2 0x008280 +#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00 +#define RW_MGR_CONTENT_MRS1 0x008200 +#define RW_MGR_CONTENT_IDLE_LOOP1 0x00A680 +#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8 +#define RW_MGR_CONTENT_MRS3 0x008300 +#define RW_MGR_CONTENT_IDLE_LOOP2 0x008680 +#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88 +#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0 +#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88 +#define RW_MGR_CONTENT_RDIMM_CMD 0x009180 +#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700 +#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8 +#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0 +#define RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168 +#define RW_MGR_CONTENT_MRS3_MIRR 0x008600 +#define RW_MGR_CONTENT_IDLE 0x080000 +#define RW_MGR_CONTENT_READ_B2B 0x040E88 +#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0_inloop 0x000000 +#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00 +#define RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68 +#define RW_MGR_CONTENT_PRECHARGE_ALL 0x000900 +#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0_inloop_1 0x000080 +#define RW_MGR_CONTENT_SGLE_READ 0x040F08 +#define RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400 +#define RW_MGR_CONTENT_RETURN 0x080680 +#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80 +#define RW_MGR_CONTENT_MRS0_USER 0x008100 +#define RW_MGR_CONTENT_GUARANTEED_READ 0x001168 +#define RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480 +#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080 +#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680 +#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00 +#define RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180 +#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680 +#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80 +#define RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158 +#define RW_MGR_CONTENT_MRS1_MIRR 0x008500 +#define RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680 + diff --git a/board/altera/socfpga/qts/sequencer_auto_ac_init.h b/board/altera/socfpga/qts/sequencer_auto_ac_init.h new file mode 100644 index 0000000000..c46421b212 --- /dev/null +++ b/board/altera/socfpga/qts/sequencer_auto_ac_init.h @@ -0,0 +1,84 @@ +/* + * Copyright Altera Corporation (C) 2012-2015 + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +const uint32_t ac_rom_init[] = { +#ifdef CONFIG_SOCFPGA_ARRIA5 +/* The if..else... is not required if generated by tools */ + 0x20700000, + 0x20780000, + 0x10080831, + 0x10080930, + 0x10090004, + 0x100a0008, + 0x100b0000, + 0x10380400, + 0x10080849, + 0x100808c8, + 0x100a0004, + 0x10090010, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +#else + 0x20700000, + 0x20780000, + 0x10080431, + 0x10080530, + 0x10090004, + 0x100a0008, + 0x100b0000, + 0x10380400, + 0x10080449, + 0x100804c8, + 0x100a0004, + 0x10090010, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +#endif /* CONFIG_SOCFPGA_ARRIA5 */ +}; diff --git a/board/altera/socfpga/qts/sequencer_auto_inst_init.h b/board/altera/socfpga/qts/sequencer_auto_inst_init.h new file mode 100644 index 0000000000..ad0395b496 --- /dev/null +++ b/board/altera/socfpga/qts/sequencer_auto_inst_init.h @@ -0,0 +1,268 @@ +/* + * Copyright Altera Corporation (C) 2012-2015 + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifdef CONFIG_SOCFPGA_ARRIA5 +/* The if..else... is not required if generated by tools */ +const u32 inst_rom_init[] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; +#else +const u32 inst_rom_init[] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x0, + 0xa000, + 0x8000, + 0x80000, + 0x80, + 0x80, + 0x80, + 0x80, + 0xa080, + 0x8080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; +#endif /* CONFIG_SOCFPGA_ARRIA5 */ diff --git a/board/altera/socfpga/qts/sequencer_defines.h b/board/altera/socfpga/qts/sequencer_defines.h new file mode 100644 index 0000000000..32f13ac9f8 --- /dev/null +++ b/board/altera/socfpga/qts/sequencer_defines.h @@ -0,0 +1,121 @@ +/* + * Copyright Altera Corporation (C) 2012-2015 + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _SEQUENCER_DEFINES_H_ +#define _SEQUENCER_DEFINES_H_ + +#define AC_ROM_MR1_MIRR 0000000000100 +#define AC_ROM_MR1_OCD_ENABLE +#define AC_ROM_MR2_MIRR 0000000010000 +#define AC_ROM_MR3_MIRR 0000000000000 +#define AC_ROM_MR0_CALIB +#ifdef CONFIG_SOCFPGA_ARRIA5 +/* The if..else... is not required if generated by tools */ +#define AC_ROM_MR0_DLL_RESET_MIRR 0100011001000 +#define AC_ROM_MR0_DLL_RESET 0100100110000 +#define AC_ROM_MR0_MIRR 0100001001001 +#define AC_ROM_MR0 0100000110001 +#else +#define AC_ROM_MR0_DLL_RESET_MIRR 0010011001000 +#define AC_ROM_MR0_DLL_RESET 0010100110000 +#define AC_ROM_MR0_MIRR 0010001001001 +#define AC_ROM_MR0 0010000110001 +#endif /* CONFIG_SOCFPGA_ARRIA5 */ +#define AC_ROM_MR1 0000000000100 +#define AC_ROM_MR2 0000000001000 +#define AC_ROM_MR3 0000000000000 +#ifdef CONFIG_SOCFPGA_ARRIA5 +/* The if..else... is not required if generated by tools */ +#define AFI_CLK_FREQ 534 +#else +#define AFI_CLK_FREQ 401 +#endif /* CONFIG_SOCFPGA_ARRIA5 */ +#define AFI_RATE_RATIO 1 +#define AVL_CLK_FREQ 67 +#define BFM_MODE 0 +#define BURST2 0 +#ifdef CONFIG_SOCFPGA_ARRIA5 +/* The if..else... is not required if generated by tools */ +#define CALIB_LFIFO_OFFSET 8 +#define CALIB_VFIFO_OFFSET 6 +#else +#define CALIB_LFIFO_OFFSET 7 +#define CALIB_VFIFO_OFFSET 5 +#endif /* CONFIG_SOCFPGA_ARRIA5 */ +#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define GUARANTEED_READ_BRINGUP_TEST 0 +#define HARD_PHY 1 +#define HARD_VFIFO 1 +#define HPS_HW 1 +#define HR_DDIO_OUT_HAS_THREE_REGS 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#ifdef CONFIG_SOCFPGA_ARRIA5 +/* The if..else... is not required if generated by tools */ +#define IO_DELAY_PER_OPA_TAP 234 +#else +#define IO_DELAY_PER_OPA_TAP 312 +#endif /* CONFIG_SOCFPGA_ARRIA5 */ +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DM_OUT_RESERVE 0 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#ifdef CONFIG_SOCFPGA_ARRIA5 +/* The if..else... is not required if generated by tools */ +#define IO_DQS_EN_DELAY_MAX 15 +#define IO_DQS_EN_DELAY_OFFSET 16 +#else +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#endif /* CONFIG_SOCFPGA_ARRIA5 */ +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 6 +#define IO_DQ_OUT_RESERVE 0 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MARGIN_VARIATION_TEST 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define MEM_ADDR_WIDTH 13 +#define READ_VALID_FIFO_SIZE 16 +#ifdef CONFIG_SOCFPGA_ARRIA5 +/* The if..else... is not required if generated by tools */ +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c +#else +#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550483 +#endif /* CONFIG_SOCFPGA_ARRIA5 */ +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_ADDRESS_WIDTH 15 +#define RW_MGR_MEM_BANK_WIDTH 3 +#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1 +#define RW_MGR_MEM_CLK_EN_WIDTH 1 +#define RW_MGR_MEM_CONTROL_WIDTH 1 +#define RW_MGR_MEM_DATA_MASK_WIDTH 5 +#define RW_MGR_MEM_DATA_WIDTH 40 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 5 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 5 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_ODT_WIDTH 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_MR0_BL 1 +#define RW_MGR_MR0_CAS_LATENCY 3 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 5 +#define RW_MGR_WRITE_TO_DEBUG_READ 1.0 +#define SKEW_CALIBRATION 0 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TINIT_CNTR0_VAL 132 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 +#define TRESET_CNTR0_VAL 132 + +#endif /* _SEQUENCER_DEFINES_H_ */ diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 37f735475b..bc2e4571fb 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -9,10 +9,15 @@ #include #include #include "sequencer.h" -#include "sequencer_auto.h" -#include "sequencer_auto_ac_init.h" -#include "sequencer_auto_inst_init.h" -#include "sequencer_defines.h" + +/* + * FIXME: This path is temporary until the SDRAM driver gets + * a proper thorough cleanup. + */ +#include "../../../board/altera/socfpga/qts/sequencer_auto.h" +#include "../../../board/altera/socfpga/qts/sequencer_auto_ac_init.h" +#include "../../../board/altera/socfpga/qts/sequencer_auto_inst_init.h" +#include "../../../board/altera/socfpga/qts/sequencer_defines.h" static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs = (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800); diff --git a/drivers/ddr/altera/sequencer_auto.h b/drivers/ddr/altera/sequencer_auto.h deleted file mode 100644 index 0c5d83bbdf..0000000000 --- a/drivers/ddr/altera/sequencer_auto.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright Altera Corporation (C) 2012-2015 - * - * SPDX-License-Identifier: BSD-3-Clause - */ - - -#define RW_MGR_READ_B2B_WAIT2 0x6A -#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31 -#define RW_MGR_REFRESH_ALL 0x14 -#define RW_MGR_ZQCL 0x06 -#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22 -#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23 -#define RW_MGR_ACTIVATE_0_AND_1 0x0D -#define RW_MGR_MRS2_MIRR 0x0A -#define RW_MGR_INIT_RESET_0_CKE_0 0x6E -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45 -#define RW_MGR_ACTIVATE_1 0x0F -#define RW_MGR_MRS2 0x04 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34 -#define RW_MGR_MRS1 0x03 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define RW_MGR_IDLE_LOOP1 0x7A -#else -#define RW_MGR_IDLE_LOOP1 0x7C -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18 -#define RW_MGR_MRS3 0x05 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define RW_MGR_IDLE_LOOP2 0x79 -#else -#define RW_MGR_IDLE_LOOP2 0x7B -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E -#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24 -#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define RW_MGR_RDIMM_CMD 0x78 -#else -#define RW_MGR_RDIMM_CMD 0x7A -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36 -#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38 -#define RW_MGR_GUARANTEED_READ_CONT 0x53 -#define RW_MGR_MRS3_MIRR 0x0B -#define RW_MGR_IDLE 0x00 -#define RW_MGR_READ_B2B 0x58 -#define RW_MGR_INIT_RESET_0_CKE_0_inloop 0x6F -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37 -#define RW_MGR_GUARANTEED_WRITE 0x17 -#define RW_MGR_PRECHARGE_ALL 0x12 -#define RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define RW_MGR_SGLE_READ 0x7C -#else -#define RW_MGR_SGLE_READ 0x7E -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define RW_MGR_MRS0_USER_MIRR 0x0C -#define RW_MGR_RETURN 0x01 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35 -#define RW_MGR_MRS0_USER 0x07 -#define RW_MGR_GUARANTEED_READ 0x4B -#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 -#define RW_MGR_INIT_RESET_1_CKE_0 0x73 -#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 -#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20 -#define RW_MGR_MRS0_DLL_RESET 0x02 -#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E -#define RW_MGR_LFSR_WR_RD_BANK_0 0x21 -#define RW_MGR_CLEAR_DQS_ENABLE 0x48 -#define RW_MGR_MRS1_MIRR 0x09 -#define RW_MGR_READ_B2B_WAIT1 0x60 -#define RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680 -#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680 -#define RW_MGR_CONTENT_REFRESH_ALL 0x000980 -#define RW_MGR_CONTENT_ZQCL 0x008380 -#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700 -#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00 -#define RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800 -#define RW_MGR_CONTENT_MRS2_MIRR 0x008580 -#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000 -#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680 -#define RW_MGR_CONTENT_ACTIVATE_1 0x000880 -#define RW_MGR_CONTENT_MRS2 0x008280 -#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00 -#define RW_MGR_CONTENT_MRS1 0x008200 -#define RW_MGR_CONTENT_IDLE_LOOP1 0x00A680 -#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8 -#define RW_MGR_CONTENT_MRS3 0x008300 -#define RW_MGR_CONTENT_IDLE_LOOP2 0x008680 -#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88 -#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0 -#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88 -#define RW_MGR_CONTENT_RDIMM_CMD 0x009180 -#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700 -#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8 -#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0 -#define RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168 -#define RW_MGR_CONTENT_MRS3_MIRR 0x008600 -#define RW_MGR_CONTENT_IDLE 0x080000 -#define RW_MGR_CONTENT_READ_B2B 0x040E88 -#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0_inloop 0x000000 -#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00 -#define RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68 -#define RW_MGR_CONTENT_PRECHARGE_ALL 0x000900 -#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0_inloop_1 0x000080 -#define RW_MGR_CONTENT_SGLE_READ 0x040F08 -#define RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400 -#define RW_MGR_CONTENT_RETURN 0x080680 -#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80 -#define RW_MGR_CONTENT_MRS0_USER 0x008100 -#define RW_MGR_CONTENT_GUARANTEED_READ 0x001168 -#define RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480 -#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080 -#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680 -#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00 -#define RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180 -#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680 -#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80 -#define RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158 -#define RW_MGR_CONTENT_MRS1_MIRR 0x008500 -#define RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680 - diff --git a/drivers/ddr/altera/sequencer_auto_ac_init.h b/drivers/ddr/altera/sequencer_auto_ac_init.h deleted file mode 100644 index c46421b212..0000000000 --- a/drivers/ddr/altera/sequencer_auto_ac_init.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright Altera Corporation (C) 2012-2015 - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -const uint32_t ac_rom_init[] = { -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ - 0x20700000, - 0x20780000, - 0x10080831, - 0x10080930, - 0x10090004, - 0x100a0008, - 0x100b0000, - 0x10380400, - 0x10080849, - 0x100808c8, - 0x100a0004, - 0x10090010, - 0x100b0000, - 0x30780000, - 0x38780000, - 0x30780000, - 0x10680000, - 0x106b0000, - 0x10280400, - 0x10480000, - 0x1c980000, - 0x1c9b0000, - 0x1c980008, - 0x1c9b0008, - 0x38f80000, - 0x3cf80000, - 0x38780000, - 0x18180000, - 0x18980000, - 0x13580000, - 0x135b0000, - 0x13580008, - 0x135b0008, - 0x33780000, - 0x10580008, - 0x10780000 -#else - 0x20700000, - 0x20780000, - 0x10080431, - 0x10080530, - 0x10090004, - 0x100a0008, - 0x100b0000, - 0x10380400, - 0x10080449, - 0x100804c8, - 0x100a0004, - 0x10090010, - 0x100b0000, - 0x30780000, - 0x38780000, - 0x30780000, - 0x10680000, - 0x106b0000, - 0x10280400, - 0x10480000, - 0x1c980000, - 0x1c9b0000, - 0x1c980008, - 0x1c9b0008, - 0x38f80000, - 0x3cf80000, - 0x38780000, - 0x18180000, - 0x18980000, - 0x13580000, - 0x135b0000, - 0x13580008, - 0x135b0008, - 0x33780000, - 0x10580008, - 0x10780000 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -}; diff --git a/drivers/ddr/altera/sequencer_auto_inst_init.h b/drivers/ddr/altera/sequencer_auto_inst_init.h deleted file mode 100644 index ad0395b496..0000000000 --- a/drivers/ddr/altera/sequencer_auto_inst_init.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Copyright Altera Corporation (C) 2012-2015 - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -const u32 inst_rom_init[] = { - 0x80000, - 0x80680, - 0x8180, - 0x8200, - 0x8280, - 0x8300, - 0x8380, - 0x8100, - 0x8480, - 0x8500, - 0x8580, - 0x8600, - 0x8400, - 0x800, - 0x8680, - 0x880, - 0xa680, - 0x80680, - 0x900, - 0x80680, - 0x980, - 0x8680, - 0x80680, - 0xb68, - 0xcce8, - 0xae8, - 0x8ce8, - 0xb88, - 0xec88, - 0xa08, - 0xac88, - 0x80680, - 0xce00, - 0xcd80, - 0xe700, - 0xc00, - 0x20ce0, - 0x20ce0, - 0x20ce0, - 0x20ce0, - 0xd00, - 0x680, - 0x680, - 0x680, - 0x680, - 0x60e80, - 0x61080, - 0x61080, - 0x61080, - 0xa680, - 0x8680, - 0x80680, - 0xce00, - 0xcd80, - 0xe700, - 0xc00, - 0x30ce0, - 0x30ce0, - 0x30ce0, - 0x30ce0, - 0xd00, - 0x680, - 0x680, - 0x680, - 0x680, - 0x70e80, - 0x71080, - 0x71080, - 0x71080, - 0xa680, - 0x8680, - 0x80680, - 0x1158, - 0x6d8, - 0x80680, - 0x1168, - 0x7e8, - 0x7e8, - 0x87e8, - 0x40fe8, - 0x410e8, - 0x410e8, - 0x410e8, - 0x1168, - 0x7e8, - 0x7e8, - 0xa7e8, - 0x80680, - 0x40e88, - 0x41088, - 0x41088, - 0x41088, - 0x40f68, - 0x410e8, - 0x410e8, - 0x410e8, - 0xa680, - 0x40fe8, - 0x410e8, - 0x410e8, - 0x410e8, - 0x41008, - 0x41088, - 0x41088, - 0x41088, - 0x1100, - 0xc680, - 0x8680, - 0xe680, - 0x80680, - 0x0, - 0x8000, - 0xa000, - 0xc000, - 0x80000, - 0x80, - 0x8080, - 0xa080, - 0xc080, - 0x80080, - 0x9180, - 0x8680, - 0xa680, - 0x80680, - 0x40f08, - 0x80680 -}; -#else -const u32 inst_rom_init[] = { - 0x80000, - 0x80680, - 0x8180, - 0x8200, - 0x8280, - 0x8300, - 0x8380, - 0x8100, - 0x8480, - 0x8500, - 0x8580, - 0x8600, - 0x8400, - 0x800, - 0x8680, - 0x880, - 0xa680, - 0x80680, - 0x900, - 0x80680, - 0x980, - 0x8680, - 0x80680, - 0xb68, - 0xcce8, - 0xae8, - 0x8ce8, - 0xb88, - 0xec88, - 0xa08, - 0xac88, - 0x80680, - 0xce00, - 0xcd80, - 0xe700, - 0xc00, - 0x20ce0, - 0x20ce0, - 0x20ce0, - 0x20ce0, - 0xd00, - 0x680, - 0x680, - 0x680, - 0x680, - 0x60e80, - 0x61080, - 0x61080, - 0x61080, - 0xa680, - 0x8680, - 0x80680, - 0xce00, - 0xcd80, - 0xe700, - 0xc00, - 0x30ce0, - 0x30ce0, - 0x30ce0, - 0x30ce0, - 0xd00, - 0x680, - 0x680, - 0x680, - 0x680, - 0x70e80, - 0x71080, - 0x71080, - 0x71080, - 0xa680, - 0x8680, - 0x80680, - 0x1158, - 0x6d8, - 0x80680, - 0x1168, - 0x7e8, - 0x7e8, - 0x87e8, - 0x40fe8, - 0x410e8, - 0x410e8, - 0x410e8, - 0x1168, - 0x7e8, - 0x7e8, - 0xa7e8, - 0x80680, - 0x40e88, - 0x41088, - 0x41088, - 0x41088, - 0x40f68, - 0x410e8, - 0x410e8, - 0x410e8, - 0xa680, - 0x40fe8, - 0x410e8, - 0x410e8, - 0x410e8, - 0x41008, - 0x41088, - 0x41088, - 0x41088, - 0x1100, - 0xc680, - 0x8680, - 0xe680, - 0x80680, - 0x0, - 0x0, - 0xa000, - 0x8000, - 0x80000, - 0x80, - 0x80, - 0x80, - 0x80, - 0xa080, - 0x8080, - 0x80080, - 0x9180, - 0x8680, - 0xa680, - 0x80680, - 0x40f08, - 0x80680 -}; -#endif /* CONFIG_SOCFPGA_ARRIA5 */ diff --git a/drivers/ddr/altera/sequencer_defines.h b/drivers/ddr/altera/sequencer_defines.h deleted file mode 100644 index 32f13ac9f8..0000000000 --- a/drivers/ddr/altera/sequencer_defines.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright Altera Corporation (C) 2012-2015 - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _SEQUENCER_DEFINES_H_ -#define _SEQUENCER_DEFINES_H_ - -#define AC_ROM_MR1_MIRR 0000000000100 -#define AC_ROM_MR1_OCD_ENABLE -#define AC_ROM_MR2_MIRR 0000000010000 -#define AC_ROM_MR3_MIRR 0000000000000 -#define AC_ROM_MR0_CALIB -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define AC_ROM_MR0_DLL_RESET_MIRR 0100011001000 -#define AC_ROM_MR0_DLL_RESET 0100100110000 -#define AC_ROM_MR0_MIRR 0100001001001 -#define AC_ROM_MR0 0100000110001 -#else -#define AC_ROM_MR0_DLL_RESET_MIRR 0010011001000 -#define AC_ROM_MR0_DLL_RESET 0010100110000 -#define AC_ROM_MR0_MIRR 0010001001001 -#define AC_ROM_MR0 0010000110001 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define AC_ROM_MR1 0000000000100 -#define AC_ROM_MR2 0000000001000 -#define AC_ROM_MR3 0000000000000 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define AFI_CLK_FREQ 534 -#else -#define AFI_CLK_FREQ 401 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define AFI_RATE_RATIO 1 -#define AVL_CLK_FREQ 67 -#define BFM_MODE 0 -#define BURST2 0 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define CALIB_LFIFO_OFFSET 8 -#define CALIB_VFIFO_OFFSET 6 -#else -#define CALIB_LFIFO_OFFSET 7 -#define CALIB_VFIFO_OFFSET 5 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0 -#define ENABLE_SUPER_QUICK_CALIBRATION 0 -#define GUARANTEED_READ_BRINGUP_TEST 0 -#define HARD_PHY 1 -#define HARD_VFIFO 1 -#define HPS_HW 1 -#define HR_DDIO_OUT_HAS_THREE_REGS 0 -#define IO_DELAY_PER_DCHAIN_TAP 25 -#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define IO_DELAY_PER_OPA_TAP 234 -#else -#define IO_DELAY_PER_OPA_TAP 312 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define IO_DLL_CHAIN_LENGTH 8 -#define IO_DM_OUT_RESERVE 0 -#define IO_DQDQS_OUT_PHASE_MAX 0 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define IO_DQS_EN_DELAY_MAX 15 -#define IO_DQS_EN_DELAY_OFFSET 16 -#else -#define IO_DQS_EN_DELAY_MAX 31 -#define IO_DQS_EN_DELAY_OFFSET 0 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define IO_DQS_EN_PHASE_MAX 7 -#define IO_DQS_IN_DELAY_MAX 31 -#define IO_DQS_IN_RESERVE 4 -#define IO_DQS_OUT_RESERVE 6 -#define IO_DQ_OUT_RESERVE 0 -#define IO_IO_IN_DELAY_MAX 31 -#define IO_IO_OUT1_DELAY_MAX 31 -#define IO_IO_OUT2_DELAY_MAX 0 -#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 -#define MARGIN_VARIATION_TEST 0 -#define MAX_LATENCY_COUNT_WIDTH 5 -#define MEM_ADDR_WIDTH 13 -#define READ_VALID_FIFO_SIZE 16 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c -#else -#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550483 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define RW_MGR_MEM_ADDRESS_MIRRORING 0 -#define RW_MGR_MEM_ADDRESS_WIDTH 15 -#define RW_MGR_MEM_BANK_WIDTH 3 -#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1 -#define RW_MGR_MEM_CLK_EN_WIDTH 1 -#define RW_MGR_MEM_CONTROL_WIDTH 1 -#define RW_MGR_MEM_DATA_MASK_WIDTH 5 -#define RW_MGR_MEM_DATA_WIDTH 40 -#define RW_MGR_MEM_DQ_PER_READ_DQS 8 -#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 -#define RW_MGR_MEM_IF_READ_DQS_WIDTH 5 -#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 5 -#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 -#define RW_MGR_MEM_ODT_WIDTH 1 -#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 -#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 -#define RW_MGR_MR0_BL 1 -#define RW_MGR_MR0_CAS_LATENCY 3 -#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 5 -#define RW_MGR_WRITE_TO_DEBUG_READ 1.0 -#define SKEW_CALIBRATION 0 -#define TINIT_CNTR1_VAL 32 -#define TINIT_CNTR2_VAL 32 -#define TINIT_CNTR0_VAL 132 -#define TRESET_CNTR1_VAL 99 -#define TRESET_CNTR2_VAL 10 -#define TRESET_CNTR0_VAL 132 - -#endif /* _SEQUENCER_DEFINES_H_ */ -- cgit v1.2.1