From 08afd714d006e528812e407cfc2d92264fc79785 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Aug 2019 12:09:37 +0300 Subject: tools: Add ifwitool to .gitignore Follow up fix to the commit 56bf4f863075 ("x86: Add ifwitool for Intel Integrated Firmware Image") in order to ignore created binary. Cc: Simon Glass Signed-off-by: Andy Shevchenko Reviewed-by: Bin Meng --- tools/.gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/.gitignore b/tools/.gitignore index 767b056b87..bd03d32f68 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -14,6 +14,7 @@ /gen_eth_addr /gen_ethaddr_crc /ifdtool +/ifwitool /img2srec /kwboot /lib/ -- cgit v1.2.1 From 03f78868aec3057b141d5e1866b8f8b6a7db778e Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 26 Aug 2019 09:48:15 +0800 Subject: x86: acpi: Slightly reduce binary size of ACPI tables for Tangier Using ACPI predefined macros, such as Zero or One, will reduce a binary size of resulting ACPI tables. Signed-off-by: Andy Shevchenko Reviewed-by: Bin Meng [bmeng: manually fixed the conflicts when applying] Signed-off-by: Bin Meng --- arch/x86/include/asm/arch-tangier/acpi/platform.asl | 2 +- arch/x86/include/asm/arch-tangier/acpi/southcluster.asl | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/arch-tangier/acpi/platform.asl b/arch/x86/include/asm/arch-tangier/acpi/platform.asl index 353b879918..a75b388c47 100644 --- a/arch/x86/include/asm/arch-tangier/acpi/platform.asl +++ b/arch/x86/include/asm/arch-tangier/acpi/platform.asl @@ -18,7 +18,7 @@ Method(_PTS, 1) /* The _WAK method is called on system wakeup */ Method(_WAK, 1) { - Return (Package() {0, 0}) + Return (Package() { Zero, Zero }) } Scope (_SB) diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl index b8b783b82e..1b9d808b7b 100644 --- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl +++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl @@ -10,8 +10,8 @@ Device (PCI0) Name (_HID, EISAID("PNP0A08")) /* PCIe */ Name (_CID, EISAID("PNP0A03")) /* PCI */ - Name (_ADR, 0) - Name (_BBN, 0) + Name (_ADR, Zero) + Name (_BBN, Zero) Name (MCRS, ResourceTemplate() { -- cgit v1.2.1 From d2860c0088cb8e0303547b2130dd237374e91fde Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 29 Aug 2019 02:53:03 -0700 Subject: x86: Drop weak version board_get_usable_ram_top() Every x86 platform provides board_get_usable_ram_top(), hence there is no need to provide a weak version board_get_usable_ram_top(), not to mention there is another weak version board_get_usable_ram_top() in common/board_f.c. Signed-off-by: Bin Meng Reviewed-by: Heinrich Schuchardt Reviewed-by: Aiden Park --- arch/x86/lib/init_helpers.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index 5e19f13720..4774a9bdb7 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -10,12 +10,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* Get the top of usable RAM */ -__weak ulong board_get_usable_ram_top(ulong total_size) -{ - return gd->ram_size; -} - int init_cache_f_r(void) { #if CONFIG_IS_ENABLED(X86_32BIT_INIT) && !defined(CONFIG_HAVE_FSP) && \ -- cgit v1.2.1 From f4c0030074544e8d3105bc9e4debb82e964ab126 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 29 Aug 2019 02:53:04 -0700 Subject: x86: qemu: Extract getting memory size to a separate routine This extracts getting memory size logic in dram_init() to a separate routine qemu_get_low_memory_size(). No functional changes. Signed-off-by: Bin Meng Reviewed-by: Aiden Park --- arch/x86/cpu/qemu/dram.c | 9 +++++++-- arch/x86/include/asm/arch-qemu/qemu.h | 7 +++++++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c index 736c4c3ace..c29b073d7c 100644 --- a/arch/x86/cpu/qemu/dram.c +++ b/arch/x86/cpu/qemu/dram.c @@ -9,7 +9,7 @@ DECLARE_GLOBAL_DATA_PTR; -int dram_init(void) +u32 qemu_get_low_memory_size(void) { u32 ram; @@ -19,7 +19,12 @@ int dram_init(void) ram |= ((u32)inb(CMOS_DATA_PORT)) << 6; ram += 16 * 1024; - gd->ram_size = ram * 1024; + return ram * 1024; +} + +int dram_init(void) +{ + gd->ram_size = qemu_get_low_memory_size(); post_code(POST_DRAM); return 0; diff --git a/arch/x86/include/asm/arch-qemu/qemu.h b/arch/x86/include/asm/arch-qemu/qemu.h index 100eb8e646..c98deb2cd2 100644 --- a/arch/x86/include/asm/arch-qemu/qemu.h +++ b/arch/x86/include/asm/arch-qemu/qemu.h @@ -37,4 +37,11 @@ #define PMREGMISC 0x80 #define PMIOSE (1 << 0) +/** + * qemu_get_low_memory_size() - Get low memory size + * + * @return: size of memory below 4GiB + */ +u32 qemu_get_low_memory_size(void); + #endif /* _ARCH_QEMU_H_ */ -- cgit v1.2.1 From ea67d549b89dbfee2bc78ba75c5b1406950f5e46 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 29 Aug 2019 02:53:05 -0700 Subject: x86: qemu: Support getting high memory size At present only size of memory that is below 4GiB is retrieved from QEMU. Add a function that gets size of memory that is above 4GiB. Signed-off-by: Bin Meng Reviewed-by: Aiden Park --- arch/x86/cpu/qemu/dram.c | 27 +++++++++++++++++++++++++-- arch/x86/include/asm/arch-qemu/qemu.h | 11 +++++++++++ 2 files changed, 36 insertions(+), 2 deletions(-) diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c index c29b073d7c..6707b7b363 100644 --- a/arch/x86/cpu/qemu/dram.c +++ b/arch/x86/cpu/qemu/dram.c @@ -22,9 +22,24 @@ u32 qemu_get_low_memory_size(void) return ram * 1024; } +u64 qemu_get_high_memory_size(void) +{ + u64 ram; + + outb(HIGH_HIGHRAM_ADDR, CMOS_ADDR_PORT); + ram = ((u64)inb(CMOS_DATA_PORT)) << 22; + outb(MID_HIGHRAM_ADDR, CMOS_ADDR_PORT); + ram |= ((u64)inb(CMOS_DATA_PORT)) << 14; + outb(LOW_HIGHRAM_ADDR, CMOS_ADDR_PORT); + ram |= ((u64)inb(CMOS_DATA_PORT)) << 6; + + return ram * 1024; +} + int dram_init(void) { gd->ram_size = qemu_get_low_memory_size(); + gd->ram_size += qemu_get_high_memory_size(); post_code(POST_DRAM); return 0; @@ -32,8 +47,16 @@ int dram_init(void) int dram_init_banksize(void) { + u64 high_mem_size; + gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->bd->bi_dram[0].size = qemu_get_low_memory_size(); + + high_mem_size = qemu_get_high_memory_size(); + if (high_mem_size) { + gd->bd->bi_dram[1].start = SZ_4G; + gd->bd->bi_dram[1].size = high_mem_size; + } return 0; } @@ -48,5 +71,5 @@ int dram_init_banksize(void) */ ulong board_get_usable_ram_top(ulong total_size) { - return gd->ram_size; + return qemu_get_low_memory_size(); } diff --git a/arch/x86/include/asm/arch-qemu/qemu.h b/arch/x86/include/asm/arch-qemu/qemu.h index c98deb2cd2..061735b298 100644 --- a/arch/x86/include/asm/arch-qemu/qemu.h +++ b/arch/x86/include/asm/arch-qemu/qemu.h @@ -32,6 +32,10 @@ #define LOW_RAM_ADDR 0x34 #define HIGH_RAM_ADDR 0x35 +#define LOW_HIGHRAM_ADDR 0x5b +#define MID_HIGHRAM_ADDR 0x5c +#define HIGH_HIGHRAM_ADDR 0x5d + /* PM registers */ #define PMBA 0x40 #define PMREGMISC 0x80 @@ -44,4 +48,11 @@ */ u32 qemu_get_low_memory_size(void); +/** + * qemu_get_high_memory_size() - Get high memory size + * + * @return: size of memory above 4GiB + */ +u64 qemu_get_high_memory_size(void); + #endif /* _ARCH_QEMU_H_ */ -- cgit v1.2.1 From 2495c3a3fd41e64af6fdc86677fb6cd07e44cd6d Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 29 Aug 2019 02:53:06 -0700 Subject: x86: qemu: Report high memory in the E820 table Now that we are able to get the size of high memory from QEMU, report its memory range as usable ram. Signed-off-by: Bin Meng Reviewed-by: Aiden Park --- arch/x86/cpu/qemu/e820.c | 59 ++++++++++++++++++++++++++++++++---------------- 1 file changed, 40 insertions(+), 19 deletions(-) diff --git a/arch/x86/cpu/qemu/e820.c b/arch/x86/cpu/qemu/e820.c index e682486547..a4136eb98c 100644 --- a/arch/x86/cpu/qemu/e820.c +++ b/arch/x86/cpu/qemu/e820.c @@ -1,46 +1,67 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * QEMU x86 specific E820 table generation + * * (C) Copyright 2015 Miao Yan + * (C) Copyright 2019 Bin Meng */ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; unsigned int install_e820_map(unsigned int max_entries, struct e820_entry *entries) { - entries[0].addr = 0; - entries[0].size = ISA_START_ADDRESS; - entries[0].type = E820_RAM; + u64 high_mem_size; + int n = 0; - entries[1].addr = ISA_START_ADDRESS; - entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS; - entries[1].type = E820_RESERVED; + entries[n].addr = 0; + entries[n].size = ISA_START_ADDRESS; + entries[n].type = E820_RAM; + n++; + + entries[n].addr = ISA_START_ADDRESS; + entries[n].size = ISA_END_ADDRESS - ISA_START_ADDRESS; + entries[n].type = E820_RESERVED; + n++; /* * since we use memalign(malloc) to allocate high memory for * storing ACPI tables, we need to reserve them in e820 tables, * otherwise kernel will reclaim them and data will be corrupted */ - entries[2].addr = ISA_END_ADDRESS; - entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS; - entries[2].type = E820_RAM; + entries[n].addr = ISA_END_ADDRESS; + entries[n].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS; + entries[n].type = E820_RAM; + n++; /* for simplicity, reserve entire malloc space */ - entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN; - entries[3].size = TOTAL_MALLOC_LEN; - entries[3].type = E820_RESERVED; + entries[n].addr = gd->relocaddr - TOTAL_MALLOC_LEN; + entries[n].size = TOTAL_MALLOC_LEN; + entries[n].type = E820_RESERVED; + n++; + + entries[n].addr = gd->relocaddr; + entries[n].size = qemu_get_low_memory_size() - gd->relocaddr; + entries[n].type = E820_RESERVED; + n++; - entries[4].addr = gd->relocaddr; - entries[4].size = gd->ram_size - gd->relocaddr; - entries[4].type = E820_RESERVED; + entries[n].addr = CONFIG_PCIE_ECAM_BASE; + entries[n].size = CONFIG_PCIE_ECAM_SIZE; + entries[n].type = E820_RESERVED; + n++; - entries[5].addr = CONFIG_PCIE_ECAM_BASE; - entries[5].size = CONFIG_PCIE_ECAM_SIZE; - entries[5].type = E820_RESERVED; + high_mem_size = qemu_get_high_memory_size(); + if (high_mem_size) { + entries[n].addr = SZ_4G; + entries[n].size = high_mem_size; + entries[n].type = E820_RAM; + n++; + } - return 6; + return n; } -- cgit v1.2.1 From 5a8558053dfc11056228aa71359915098aa1c4cb Mon Sep 17 00:00:00 2001 From: "Park, Aiden" Date: Thu, 22 Aug 2019 21:31:31 +0000 Subject: doc: slimbootloader: Update Linux booting steps on QEMU Add steps to test Linux booting on QEMU with Yocto image. Signed-off-by: Aiden Park Reviewed-by: Bin Meng Tested-by: Bin Meng --- doc/board/intel/slimbootloader.rst | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/doc/board/intel/slimbootloader.rst b/doc/board/intel/slimbootloader.rst index 07c9b126f7..375e676804 100644 --- a/doc/board/intel/slimbootloader.rst +++ b/doc/board/intel/slimbootloader.rst @@ -86,6 +86,28 @@ The PayloadId can be any 4 Bytes value. $ qemu-system-x86_64 -machine q35 -nographic -serial mon:stdio -pflash Outputs/qemu/SlimBootloader.bin +Test Linux booting on QEMU target +--------------------------------- + +Let's use LeafHill (APL) Yocto image for testing. +Download it from http://downloads.yoctoproject.org/releases/yocto/yocto-2.0/machines/leafhill/. + +1. Prepare Yocto hard disk image:: + + $ wget http://downloads.yoctoproject.org/releases/yocto/yocto-2.0/machines/leafhill/leafhill-4.0-jethro-2.0.tar.bz2 + $ tar -xvf leafhill-4.0-jethro-2.0.tar.bz2 + $ ls -l leafhill-4.0-jethro-2.0/binary/core-image-sato-intel-corei7-64.hddimg + +2. Launch Slim Bootloader on QEMU with disk image:: + + $ qemu-system-x86_64 -machine q35 -nographic -serial mon:stdio -pflash Outputs/qemu/SlimBootloader.bin -drive id=mydrive,if=none,file=/path/to/core-image-sato-intel-corei7-64.hddimg,format=raw -device ide-hd,drive=mydrive + +3. Update boot environment values on shell:: + + => setenv bootfile vmlinuz + => setenv bootdev scsi + => boot + Build Instruction for Slim Bootloader for LeafHill (APL) target --------------------------------------------------------------- -- cgit v1.2.1 From 74b76357dfd75550cd9a511e71990d414a4d023e Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 25 Aug 2019 19:55:12 +0200 Subject: x86: show UEFI images involved in crash If a crash occurs, show the loaded UEFI images to facilitate analysis. This is an example output: => bootefi 0x1000000 Found 0 disks Hello world of bugs! Invalid Opcode (Undefined Opcode) EIP: 0010:[<06ceb06e>] EFLAGS: 00010206 Original EIP :[] EAX: 00000000 EBX: 06cec000 ECX: 00000fd0 EDX: 00000001 ESI: 06ced18a EDI: 07d0fe10 EBP: 07fe27a0 ESP: 07d0fde0 DS: 0018 ES: 0018 FS: 0020 GS: 0018 SS: 0018 CR0: 00000033 CR2: 00000000 CR3: 00000000 CR4: 00000000 DR0: 00000000 DR1: 00000000 DR2: 00000000 DR3: 00000000 DR6: ffff0ff0 DR7: 00000400 Stack: 0x07d0fde8 : 0x00000000 0x07d0fde4 : 0x06ced040 --->0x07d0fde0 : 0x07fe27a0 0x07d0fddc : 0x00010206 0x07d0fdd8 : 0x00000010 0x07d0fdd4 : 0x06ceb06e UEFI image [0x06cea000:0x06cf0fff] pc=0x106e '/bug-i386.efi' ### ERROR ### Please RESET the board ### With the additional information provided by this patch we know that the problem occurred 0x106e after the load address of bug-i386.efi. Signed-off-by: Heinrich Schuchardt Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/x86/cpu/i386/interrupt.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c index 47df3172b7..1445204878 100644 --- a/arch/x86/cpu/i386/interrupt.c +++ b/arch/x86/cpu/i386/interrupt.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -64,6 +65,18 @@ static char *exceptions[] = { "Reserved" }; +/** + * show_efi_loaded_images() - show loaded UEFI images + * + * List all loaded UEFI images. + * + * @eip: instruction pointer + */ +static void show_efi_loaded_images(uintptr_t eip) +{ + efi_print_image_infos((void *)eip); +} + static void dump_regs(struct irq_regs *regs) { unsigned long cs, eip, eflags; @@ -144,6 +157,7 @@ static void dump_regs(struct irq_regs *regs) printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp)); sp -= 4; } + show_efi_loaded_images(eip); } static void do_exception(struct irq_regs *regs) -- cgit v1.2.1 From 5793553fa24077e3b91028f8097fb1fdbede1480 Mon Sep 17 00:00:00 2001 From: "Park, Aiden" Date: Tue, 3 Sep 2019 17:43:46 +0000 Subject: x86: efi_loader: Use efi_add_conventional_memory_map() Use efi_add_conventional_memory_map() to configure EFI conventional memory properly with ram_top value. This will give 32-bit mode U-Boot proper conventional memory regions even if e820 has an entry which is greater than 32-bit address space. Signed-off-by: Aiden Park Tested-by: Heinrich Schuchardt Reviewed-by: Heinrich Schuchardt [bmeng: fixed some typos in the commit message] Signed-off-by: Bin Meng --- arch/x86/lib/e820.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/x86/lib/e820.c b/arch/x86/lib/e820.c index d6ae2c4e9d..26da4d2f27 100644 --- a/arch/x86/lib/e820.c +++ b/arch/x86/lib/e820.c @@ -41,14 +41,17 @@ void efi_add_known_memory(void) { struct e820_entry e820[E820MAX]; unsigned int i, num; - u64 start, pages; + u64 start, pages, ram_top; int type; num = install_e820_map(ARRAY_SIZE(e820), e820); + ram_top = (u64)gd->ram_top & ~EFI_PAGE_MASK; + if (!ram_top) + ram_top = 0x100000000ULL; + for (i = 0; i < num; ++i) { start = e820[i].addr; - pages = ALIGN(e820[i].size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT; switch (e820[i].type) { case E820_RAM: @@ -69,7 +72,15 @@ void efi_add_known_memory(void) break; } - efi_add_memory_map(start, pages, type, false); + if (type == EFI_CONVENTIONAL_MEMORY) { + efi_add_conventional_memory_map(start, + start + e820[i].size, + ram_top); + } else { + pages = ALIGN(e820[i].size, EFI_PAGE_SIZE) + >> EFI_PAGE_SHIFT; + efi_add_memory_map(start, pages, type, false); + } } } #endif /* CONFIG_IS_ENABLED(EFI_LOADER) */ -- cgit v1.2.1 From 19b6e1ba8c67e413d73df9db7e0c88c379e033a7 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 29 Aug 2019 17:04:18 +0300 Subject: x86: acpi: Annotate struct acpi_table_header with __packed MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit GCC 9.2 starts complaining about possible pointer misalignment of pointers to the unpacked (alignment=4) structures in the packed (alignment=1) ones: CC arch/x86/cpu/tangier/acpi.o arch/x86/cpu/tangier/acpi.c: In function ‘acpi_create_fadt’: arch/x86/cpu/tangier/acpi.c:22:37: warning: taking address of packed member of ‘struct acpi_fadt’ may result in an unaligned pointer value [-Waddress-of-packed-member] 22 | struct acpi_table_header *header = &(fadt->header); CC arch/x86/lib/acpi_table.o arch/x86/lib/acpi_table.c: In function ‘acpi_create_spcr’: arch/x86/lib/acpi_table.c:366:37: warning: taking address of packed member of ‘struct acpi_spcr’ may result in an unaligned pointer value [-Waddress-of-packed-member] 366 | struct acpi_table_header *header = &(spcr->header); Fix the potential issues by annotating embedded structures with __packed even though they are packed naturally. Signed-off-by: Andy Shevchenko Reviewed-by: Bin Meng [bmeng: add GCC version number in the commit message] Signed-off-by: Bin Meng --- arch/x86/include/asm/acpi_table.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 02aea127c1..7588913f93 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -34,7 +34,7 @@ struct acpi_rsdp { }; /* Generic ACPI header, provided by (almost) all tables */ -struct acpi_table_header { +struct __packed acpi_table_header { char signature[4]; /* ACPI signature (4 ASCII characters) */ u32 length; /* Table length in bytes (incl. header) */ u8 revision; /* Table version (not ACPI version!) */ -- cgit v1.2.1 From 0c6352ec2a238c1f89b0f394b34da57ab0849f6a Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 29 Aug 2019 17:04:19 +0300 Subject: x86: tangier: Reserve PCI ECAM in motherboard resources Per PCI firmware specification the ACPI has to reserve the memory which is defined as PCI ECAM. Fixes: 39665beed6f7 ("x86: tangier: Enable ACPI support for Intel Tangier") Signed-off-by: Andy Shevchenko Reviewed-by: Bin Meng --- arch/x86/cpu/tangier/acpi.c | 3 ++- arch/x86/include/asm/arch-tangier/acpi/platform.asl | 1 + arch/x86/include/asm/arch-tangier/acpi/southcluster.asl | 17 +++++++++++++++++ arch/x86/include/asm/arch-tangier/iomap.h | 10 ++++++++++ 4 files changed, 30 insertions(+), 1 deletion(-) create mode 100644 arch/x86/include/asm/arch-tangier/iomap.h diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c index 61b2642aa9..362e133cf1 100644 --- a/arch/x86/cpu/tangier/acpi.c +++ b/arch/x86/cpu/tangier/acpi.c @@ -14,6 +14,7 @@ #include #include #include +#include void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, void *dsdt) @@ -63,7 +64,7 @@ u32 acpi_fill_mcfg(u32 current) /* TODO: Derive parameters from SFI MCFG table */ current += acpi_create_mcfg_mmconfig ((struct acpi_mcfg_mmconfig *)current, - 0x3f500000, 0x0, 0x0, 0x0); + MCFG_BASE_ADDRESS, 0x0, 0x0, 0x0); return current; } diff --git a/arch/x86/include/asm/arch-tangier/acpi/platform.asl b/arch/x86/include/asm/arch-tangier/acpi/platform.asl index a75b388c47..cf75ca7543 100644 --- a/arch/x86/include/asm/arch-tangier/acpi/platform.asl +++ b/arch/x86/include/asm/arch-tangier/acpi/platform.asl @@ -6,6 +6,7 @@ */ #include +#include /* * The _PTS method (Prepare To Sleep) is called before the OS is diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl index 1b9d808b7b..f73a6b351c 100644 --- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl +++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl @@ -66,6 +66,23 @@ Device (PCI0) Return (MCRS) } + /* Device Resource Consumption */ + Device (PDRC) + { + Name (_HID, EISAID("PNP0C02")) + Name (_UID, One) + + Name (PDRS, ResourceTemplate() + { + Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE) + }) + + Method (_CRS, 0, Serialized) + { + Return (PDRS) + } + } + Method (_OSC, 4) { /* Check for proper GUID */ diff --git a/arch/x86/include/asm/arch-tangier/iomap.h b/arch/x86/include/asm/arch-tangier/iomap.h new file mode 100644 index 0000000000..b0fc03e015 --- /dev/null +++ b/arch/x86/include/asm/arch-tangier/iomap.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (c) 2019 Intel Corporation */ + +#ifndef _TANGIER_IOMAP_H +#define _TANGIER_IOMAP_H + +#define MCFG_BASE_ADDRESS 0x3f500000 +#define MCFG_BASE_SIZE 0x00100000 + +#endif /* _TANGIER_IOMAP_H */ -- cgit v1.2.1 From 980fe1ab2ad6a449639928d7a7e9c0aadb41a495 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 29 Aug 2019 17:04:20 +0300 Subject: x86: tangier: Fix off-by-one error when preparing CSRT Intel iDMA 32-bit controller has 17 bits for the maximum block size value. Due to nature of the binary number representation the maximum value is 2^17 - 1. The original code misses the latter part in equation. Fixes: 5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller") Signed-off-by: Andy Shevchenko Reviewed-by: Bin Meng --- arch/x86/cpu/tangier/acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c index 362e133cf1..8b128138b0 100644 --- a/arch/x86/cpu/tangier/acpi.c +++ b/arch/x86/cpu/tangier/acpi.c @@ -95,7 +95,7 @@ static u32 acpi_fill_csrt_dma(struct acpi_csrt_group *grp) si->dma_address_width = 32; si->base_request_line = 0; si->num_handshake_signals = 16; - si->max_block_size = 0x20000; + si->max_block_size = 0x1ffff; return grp->length; } -- cgit v1.2.1 From dd4faa964f0741c314b4f1c09f27c07aedc5cdf0 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 29 Aug 2019 17:04:21 +0300 Subject: x86: tangier: Use spaces over TABs in ASL code For sake of consistency use spaces over TABs in ASL code. Signed-off-by: Andy Shevchenko Reviewed-by: Bin Meng --- .../include/asm/arch-tangier/acpi/southcluster.asl | 26 +++++++++++----------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl index f73a6b351c..c622783f44 100644 --- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl +++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl @@ -382,19 +382,19 @@ Device (PCI0) Name (RBUF, ResourceTemplate() { /* - * Shadow registers in SRAM for PMIC: - * SRAM PMIC register - * -------------------- - * 0x00- Unknown - * 0x03 THRMIRQ (0x04) - * 0x04 BCUIRQ (0x05) - * 0x05 ADCIRQ (0x06) - * 0x06 CHGRIRQ0 (0x07) - * 0x07 CHGRIRQ1 (0x08) - * 0x08- Unknown - * 0x0a PBSTATUS (0x27) - * 0x0b- Unknown - */ + * Shadow registers in SRAM for PMIC: + * SRAM PMIC register + * -------------------- + * 0x00- Unknown + * 0x03 THRMIRQ (0x04) + * 0x04 BCUIRQ (0x05) + * 0x05 ADCIRQ (0x06) + * 0x06 CHGRIRQ0 (0x07) + * 0x07 CHGRIRQ1 (0x08) + * 0x08- Unknown + * 0x0a PBSTATUS (0x27) + * 0x0b- Unknown + */ Memory32Fixed(ReadWrite, 0xFFFFF610, 0x00000010) Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 30 } Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 23 } -- cgit v1.2.1